KR930000733B1 - Level 2 protocol processing apparatus having separated distributed memory - Google Patents

Abstract

The level 2 protocol processing apparatus adapts a pair of RAM and arbitrator to improve reliability of a relay system. The apparatus includes a first and a second RAM (810a,810b) for storing message transmitted between a level 2 and a level 3 unit temporary, a first and a second internal abitrator (870a,870b) for abitrating between signal to access the RAMs through a first and a second connector, and signal generated by an internal processor, a processor (820) for processing message transmitted between the RAMs and the internal abitrators according to level 2 protocol, a ROM (830) for storing initilization program and debugging program, a RAM (840) for storing a level 2 protocol processing program, and a HDLC chip (850) for executing HDLC protocol.

Description

Level 2 protocol processing unit having a separate distributed memory structure of a signal relay system.

1 is a signal repeater configuration diagram.

2 is a redundant configuration of signal message processing module.

3 is a redundancy diagram of a signal message processing submodule.

4 is a flowchart of a signal message input to one level 2 unit.

5 is a functional block diagram of a level 3 unit.

6 is a functional block diagram of a level 3-3 network unit.

7 is a functional block diagram of a level 2 unit.

8 is a configuration diagram of a level 2 protocol processing unit of the present invention.

* Explanation of symbols for main parts of the drawings

100a, 100b: level 3-3 network 110: signal message processing module

120: signal network management module

130: O & M (operation and maintenance) system 140: terminal (console)

200a, 200b: Level 3-3 network 210: Signal message processing module

220 to 220n: level 3 unit

320a, 320b: Level 3-3 network unit

330a, 330b: Level 2-3 network (parallel bus)

340a to 340n: level 2 unit

350a, 350b: Distributed memory distributed in level 3 units

360a, 360b: Distributed memory distributed in level 3-3 network unit

370a to 370n: distributed memory distributed in level 2 units

800a, 800b: Parallel Bus Connector 810a, 810b: Commercially Available RAM

820: processor chip 830: ROM

840: RAM 850: HDLC chip

860: 64 Kbps Serial Connector 840: Internal Arbitr

The present invention relates to a level 2 protocol processing unit for a redundant structure of a signal repeater that performs a message transfer function in a NO.7 common line signaling network recommended by the International Telegraph and Telephone Advisory Committee (CCITT). A level 2 protocol processing apparatus having a structure.

Level 2 of the units that implement the message delivery protocol is the board that performs the message delivery protocol level 2 protocol, and level 3 unit performs the message handling protocol which mainly performs message routing among the level 3 protocols of the message delivery protocol. That's the board. Level 2-3 networks are used by Level 3 units to connect multiple Level 2 units, and Level 3 and Level 2 units and Level 3-3 network units that are connected by a Level 2-3 network handle one signal message. Configure the module.

The existing signal repeater system (application 1988-8738) used a single path level 2-3 network to connect level 2 units with level 3 units. A single path level 3-3 network was used to connect these modules. Because these systems use a single path network, if one path fails, many Level 2 units or modules will be unavailable.

Accordingly, in order to solve the above problem, the present applicant has filed a signal repeater redundancy structure system (No. 13721, filed on September 23, 1989) in the NO.7 common line signal network. Is a redundant 3-3 network and 2-3 network connected to the level 3-3 network for connecting the level 2 unit and the level 3 unit to the level 2 unit and the level 3-3 network unit. A signal message processing module, a signal network management module connected to the redundant level 3-3 network, and an O & M (operation and maintenance) system connected to the redundant level 3-3 network, The message processing module, the signal network management module and the O & M (operation and maintenance) system are connected through the redundant level 3-3 network, and the level 3 unit in the signal message processing module is connected through the level 2-3 network. Level 2 and level-unit 3-3 connected to the network units, and the level was allowed to 3-3 connected to the network via the 3-3 level network unit.

The present invention improves the reliability of the system by using two pairs of completely separate RAMs and arbitrators in a signal repeater redundant structure system to improve the conventional problems as described above, and economically benefits from using a large capacity RAM in general. It aims to provide a level 2 protocol processing device.

In order to achieve the above object, the present invention provides the first and second parallel bus connecting means connected to the redundant parallel bus, and the first and second parallel bus connecting means separately and connected to the level 3 unit and the level 2, respectively. First and second independent temporary storage memory means for temporarily storing transmission and reception messages between units, and the first and second connectors connected in parallel to the first and second independent temporary storage memory means, respectively. First and second internal arbitration means for preventing a collision between a signal accessed via a signal accessed by an internal processor and the first and second independent temporary storage means and a first and a second A processor for level 2 protocol processing of messages transmitted and received connected to internal mediation means, and an initialization program and a debugging program connected to the processor A ROM provided to the processor, a RAM connected to the processor, a level 2 protocol processing program, a RAM provided to the processor, and an HDLC connected to the processor, the RAM, and the ROM to perform an HDLC protocol, which is a bit-oriented communication method. And a serial connector connected to the HDLC chip and connected to a level 2 signal link to perform a level 2 protocol of a message transfer function.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

In order to explain the level 2 processing unit of the present invention, the structure of the signal repeater system is described first.

1 is a signal repeater system centered on a duplicated level 3-3 network, wherein the level 3-3 network 100a, 100b, the signal message processing module 110, the signal network management module 1 20, and O & M ( Operation and maintenance) system 130, the terminal (1400).

2 is a redundant configuration of the signal message processing module, and is composed of the level 3-3 network (200a, 2 00b), the signal message processing module 210, and the signal message processing submodules 220a to 220n.

3 is a redundant configuration of signal message processing sub-modules, which include level 3-3 network 300a and 300b, level 3 units 310a and 310b, level 3-3 network unit 320a and 320b, and parallel buses (level 2). -3 network (330a, 330b), level 2 units (340a to 340n), distributed memory (350a, 350b) divided into level 3 units, distributed memory (36 0a, 360b) distributed in level 3-3 network units, It is composed of distributed memories 370a to 370n distributed in level 2 units.

The signal message processing submodule used two separate boards of level 3-3 network units 310a and 310b for connection to the redundant level 3-3 network 300a and 300b. In one system configured as described above, even if one level 3-3 network unit and one parallel bus fail, one signal message processing submodule is not possible using the level 3-3 network unit and the parallel bus that do not fail. The reliability of the system is improved because it is prevented from being used. In particular, level 3 units 310a and 310b connect to a plurality of level 2 units 340a to 340b via two and parallel buses 330a and 330b. In a system configured as such, when a parallel bus fails, a Level 3 unit communicates with a Level 3 unit using an uninterrupted parallel bus, which prevents multiple Level 2 units from failing on a single bus. This prevents the system from increasing the reliability of the system and ensures that the entire system can operate normally until maintenance.

In addition, since the redundant RAM is electrically separated, even if a failure occurs on one side, the reliability of the circuit is also improved since the ram on the other side is not affected. And because it uses regular RAM, it takes some overhead for mediation, but it is easy to make a large amount economically.

In addition, the Level 3 unit consists of two pieces and can perform different functions under normal conditions or can share the same functions. Level 3 units operate as masters on one bus each.

Therefore, if one parallel bus fails, the level 3 unit connected to the uninterrupted parallel bus functions as the master.

The signal message processing module accommodates signal links that process hundreds of level 2 functions. This Level 2 feature can be implemented at the board level, with hundreds of modes. Currently used parallel buses cannot accommodate more than 20 boards. Therefore, using a parallel bus, Chapter 8 configures a redundant signal message submodule that connects 16 Level 2 units, and then connects multiple signal message processing submodules again using a redundant level 3-3 network. Hundreds of Level 2 units are connected using a conventional architecture.

4 is a flowchart of signal messages input to one level 2 unit.

The following signaling messages <flow 1> and <flow 2> show that the signal messages are processed in the normal state. Here, <flow1> is a case where a path is selected to a level 2 unit in which the signal messages processed by the level 3 unit are in the same signal message processing submodule, in the order of 1-2-3-8-9. 2> proceeds in the order of 1-2-3-5-6-10-13-17-19 and indicates that the level 2 unit path is selected when the signal message processed by the level 3 unit is in another signal message processing module. Shows. Flow 3 proceeds in the order of 1-2-4-8-9 and shows that when one parallel bus fails, the signal message is processed through the parallel bus without failure. At this time, the level 3 main function is performed by a level 3 unit that accesses a bus that has not failed. <Flow 4> proceeds in the order of 1-2-3-11-7-12-13-17-19. When one level 3-3 network unit or level 3-3 network fails, the signal message fails. It shows that processing is done through level 3-3 network and level 3-3 network units.

5A and 5B are functional block diagrams of a level 3 unit that mainly performs a routing function among the level 3 functions of the message transfer protocol, and include a CPU, a read only memory (ROM), and a random access memory (RAM). It is composed of DPRAM (Dual Ported RAM).

The level 3 unit can be implemented using a general processor (MC6800, Intel 80286), the level 3 protocol of the message transfer protocol is mounted in a ROM (ROM) or RAM (RAM). Level 3 units are connected to the redundant parallel bus via connectors a and b. A level 3 unit is composed of two types, one of which is a level 3 unit accessing one of the redundant parallel buses through connector a as shown in FIG. 5A, and the other of the parallel buses is connected to connector b through memory. That is, the connector b only functions as a memory.

The other level 3 unit accesses one of the dual parallel buses through the connector b as shown in FIG. 5B, and the other of the redundant parallel buses is connected to the connector a through the memory. That is, the connector a only functions as a memory. Since these two Level 3 units can only access one of the redundant parallel buses, using parallel buses without an arbitrator can speed up parallel bus access, resulting in improved system performance. And because only one bus can be accessed and the other buses only appear to each other as memory, no circuitry such as an arbiter is needed, and the hardware for access can be simplified, which increases system reliability. In particular, since the arbitrator is technically difficult to duplicate, it has the advantage of being easily implemented by redundancy. In this case, two different types of Level 3 units are connected to a redundant parallel bus, and when one Level 3 unit fails, multiple Level 3 units connected to one Level 3 unit perform the functions of the non-faulting Level 3 unit instead. 2 Prevent the unit from becoming unusable.

6 is a functional block diagram of a level 3-3 network unit, which is composed of a CPU, a RAM, a ROM, a DPRAM, a network control chip, and an arbiter.

Level 3-3 network units are used to connect a module or submodule to a level 3-3 network. Like level 3 units, a level 3-3 network unit consists of a common processor and memory, especially the network control required to access a level 3-3 network. Chips are used. A network control chip is a commercially available local area network (LAN) chip. Token Ring, Token Bus, and Ethernet can be used. The protocol chip driving program for level 3-3 network control is carried out in ROM and RAM. As depicted in Figure 6, the level 3-3 network units all appear as memory on the redundant parallel bus. An internal arbiter is then required to prevent concurrent access of memory through connector a and connector b. Unlike the arbiter used on the bus, the arbiter is configured independently on the board, so that a failure in one does not affect the entire system.

7 is a functional block diagram of a level 2 unit, which is composed of a CPU, a RAM, a ROM, a DPRAM, an HDLC chip, and an arbiter. The level 2 unit performs the level 2 protocol of the message transfer protocol. The level 3 protocol performs functions related to signal network management and signal message routing, while the level 2 unit performs signal message delivery. That is, an error message signal retransmits for error-free signal message transmission. The signal message transmission is performed at 64Kbps, and the level 2 unit is configured using commercially available HDLC chips (Z8530, SCN68562) and level 2 processing processor (MK5072) to perform the level 2 protocol. As described in Figure 7, level 2 units, like level 3-3 network units, all appear as memory on a redundant parallel bus. An arbitrator is then required to prevent concurrent access to memory through connector a and connector b. Unlike the arbiter used on the bus, as in Figure 6, this arbiter is configured independently on the board, so that a failure in one does not affect the entire system.

As described in Figs. 5, 6 and 7, only one level 3 unit is accessed to each of the redundant parallel buses, so that no arbitrator is required for the parallel bus. That is, all the remaining units appear as memory only on the parallel bus, simplifying the circuit used for configuration, and redundancy is easy because there is no arbiter on the parallel bus.

As described above, the redundant signal repeater system has a configuration as described above, so that a plurality of level 2 units and modules become available even when one level 2-3 network and a level 3-3 network fail. Maintenance can be performed through a single path where a failure occurs. In other words, in order to replace one module in the existing system, the whole system was stopped or the system function was adversely affected. However, in the redundant signal repeater system, the module can be replaced under normal available conditions.

The present invention improves the performance and reliability of the redundant signal repeater as described above, and implements by reconfiguring the level 2 protocol processing apparatus as shown in FIG.

8 is a configuration diagram of a level 2 protocol processing unit according to the present invention, which is separated from the first and second parallel bus connectors 800a and 800b and the first and second parallel bus connectors respectively connected to the redundant parallel bus. To the first and second independent RAMs 810a and 810b, and to the first and second independent RAMs 810a and 810b, which are connected to each other and are connected to each other, and store and store the transmission and reception messages between the level 3 and level 2 units. First and second internal arbiters 870a, which are connected in parallel with each other for each other to prevent a collision between a signal accessed through the first and second connectors 800a and 800b and a signal accessed by an internal processor. 870b and a processor 820 coupled to the first and second independent RAMs 810a and 810b and the first and second internal arbiters 870a and 870b to process Level 2 protocols for messages sent and received. And an initialization program connected to the processor 820. And a ROM 830 loaded with a debugging program and provided to the processor 820, a RAM 840 connected to the processor 820 and loaded with a level 2 protocol processing program and provided to the processor 820. 820, an HDLC chip 850 connected to the RAM 840 and a ROM 830 to perform an HDLC protocol, which is a bit-oriented communication method, and an HDLC chip 850 connected to a level 2 signal link. And a serial connector 860.

The level 2 protocol of the message transfer unit function is performed on the level 2 unit NO.7 common line signal network configured as described above. Use a level 2 processing processor.

As such, the present invention uses two completely independent RAMs 810a and 810b to isolate the redundant parallel bus in hardware and communicate with other level 2 units through two parallel bus connectors 800a and 800b. Improved the performance and reliability of the system by eliminating the arbitrators needed to prevent memory from being accessed at the same time, and by providing the arbitrators (870a and 870b) for level 2 processors and level 3 processors to access RAM at the same time. , Using a commercially available HDLC chip 850, and equipped with a level 2 protocol in the ROM (830) and RAM (840) to allow the processor 820 to perform the level 2 protocol, completely separated RAM (810a, 810b) In order to communicate with the level 3 unit, the ROM 830 includes a program for controlling the level 2 protocol processing chip and a program for communicating with the level 3 unit.

Signal messages input through the 64 Kbps serial connector 860 are stored in the receiving buffer in the RAM 840 and the signal messages to be transmitted to the level 3 unit among the processed signal messages are completely separated from the independent RAMs 810a and 810b. Is transmitted to the level 3 unit, and the signal message received from the level 3 unit is stored in the transmission buffer in the RAM 840 and then transmitted to the outside through the 64 Kbps serial connector 960.

In addition, by setting the receiving buffer in the independent RAM 810a, 810b, the level 3 unit can process the signal without moving the input signal message and transmit the signal message received from the level 3 unit through the 64Kbps serial connector without moving. Do it.

Therefore, the present invention constructed and operated as described above uses a general RAM, which makes it easy to increase the capacity and can be directly used as an input buffer for input signal messages. Therefore, after the level 2 processor processes the input signal message, the level 3 processor can immediately process the signal message without moving. That is, in the existing system, the signal message input to the level 2 protocol unit is first loaded into the local RAM 840 of the level 2 unit, and then processed by the level 2 processor. The processed signal message is moved to RAM 810 by a level 2 processor to communicate with a level 3 unit. However, if the capacity of the RAM 810 is large, the receive buffer of the level 2 unit can be placed in the RAM 810 so that the level 2 unit can process and the level 3 unit can process it without moving the signal message. Signal messages sent from level 3 units to level 2 units can also be used to reduce the movement of messages by one level, improving system performance.

Claims (6)

No. 7 A redundant structure system of a signal repeater performing a message transfer function in a common line signal network, comprising: first and second parallel bus connectors 800a and 800b connected to a redundant parallel bus, and the first and second signals. First and second independent RAMs 810a and 810b, each separately connected to a second parallel bus connector and temporarily storing transmission and reception messages between level 3 and level 2 units, and the first and second independent A first and second connection in parallel to the inks 810a and 810b, respectively, to prevent a collision between a signal accessed through the first and second connectors 800a and 800b and a signal accessed by an internal processor; Levels for messages sent to and received from second internal arbiters 870a and 870b, the first and second independent RAMs 810a and 810b, and first and second internal arbiters 870a and 870b. Processor 820 for processing two protocols, and the processor 820 ROM (830) connected to the processor 820 and mounted with an initialization program and a debugging program, and a RAM connected to the processor 820 and provided to the processor 820 with a level 2 protocol processing program. 840 and the HDLC chip 850 and the HDLC chip 850 connected to the processor 8 20, the RAM 840, and the ROM 830 to perform an HDLC protocol, which is a bit-oriented communication method. And a serial connector (860) connected to the two signal links to perform the level 2 protocol of the function of the message transfer unit. The RAM of claim 1, wherein the first and second independent RAMs 810a and 810b are separated by hardware to separate the redundant parallel buses so as to prevent electrical connection between the two RAMs. Level 2 protocol processing apparatus having a separate distributed memory structure of the signal repeater system, characterized in that it is configured to be used. 2. The signal message according to claim 1, wherein the signal message input through the serial connector 860 is stored in a reception buffer in a program for driving a level 2 protocol mounted in the RAM 840, and then the processed signal message is a level 3 unit. And a separate distributed memory structure of the signal relay system, characterized in that configured to transmit through the independent RAM (810a, 810b) when transmitting. The signal message from the level 3 unit received through the independent RAMs 810a and 810b is stored in a transmission buffer in the RAM 840, and then configured to be transmitted on a level 2 signal link. Level 2 protocol processing apparatus having a separate distributed memory structure of the signal relay system. 2. The signal relay according to claim 1, wherein the independent RAMs 810a and 810b are configured to process the input signal message in a level 2 unit by setting a buffer therein and then immediately processing the level 3 unit without moving. Level 2 protocol processing unit having a separate distributed memory structure of the system. 2. The independent RAMs 810a and 810b set a buffer therein to process a signal message sent from a level 3 unit to a level 2 unit in a level 3 unit and then immediately move to another level 3 unit without moving to the level 3 unit. A level 2 protocol processing apparatus having a separate distributed memory structure of a signal relay system, configured to transmit to a level 2 unit.

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