CN1163826C - 改进的微处理器 - Google Patents
改进的微处理器 Download PDFInfo
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- CN1163826C CN1163826C CNB971822735A CN97182273A CN1163826C CN 1163826 C CN1163826 C CN 1163826C CN B971822735 A CNB971822735 A CN B971822735A CN 97182273 A CN97182273 A CN 97182273A CN 1163826 C CN1163826 C CN 1163826C
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Priginal C code While((n--)>0 { *s++=C } Win32×86 instructions produced by a compiler compiling this C code. mov %ecx,[%ebp+0xc] // load c from memory address into %ecx mov %eax,[%ebp+0x8] // load s from memory address into %eax mov [%eax],%ecx // store c into memory address s held in %eax add %eax,#4 // increment s by 4 mov [%ebp+0x8],%eax // store(s+4)back into memory. mov %eax,[%ebp+0x10] // load n from memory address into %eax lea %ecx,[%eax-1] // decrement n and store result in %ecx mov [%ebp+0x10],%ecx // store(n-1)into memory and %eax,%eax // test n to set condition codes jg .-0x1b // branch to top of this section if ″n>0″ Notation:[...]indicates an address expression for a memory operand. In the example above,the address for a memory operand is formed from the contents of a register added to a hexadecimal constant indicated by the Ox prefix.Target registers are indicated with the % prefix, e.g.%ecx is the ecx register.The destination of an operation is tothe left. Target instruction key: jg=jump if greater mov=move lea=load effective address and=AND
Shows each X86 Instruction shown above followed by the host <dp n="d25"/> instructions necessary to implement the X86 Instruction mov %ecx,[%ebp+0xc] // load c from memory address into ecx add R0,Rebp,0xc ; form memory address and put it in R0 ld Recx,[R0] ; load c from memory address in R0 into Recx mov %eax,[%ebp+0x8] // load s from memory address into %eax add R2,Rebp,0x8 ; form memory address and put it in R2 ld Reax,[R2] ; load s from memory address in R2 into Recx mov [%eax],%ecx // store c into memory address s held in %eax st [Reax],Recx ; store c into memory address s held in Reax add %eax,#4 // increment s by 4 add Reax,Reax,4 ; increment S by 4 mov [%ebp+0x8],%eax // store(s+4)back into memory add R5,Rebp,0x8 ; form memory address and put it in R5 st [R5],Reax ; store(s+4) back into memory mov %eax,[%ebp+0x10] // load n from memory address into %eax add R7,Rebp,0x10 ; form memory address and put it in R7 ld Reax,[R7] ; load n from memory address into Reax lea %ecx,[%eax-1] // decrement n and store result in %ecx sub Recx,Reax,1 ; decrement n and store result in Recx mov [%ebp+0x10],%ecx// store(n-1)into memory add R9,Rebp,0x10 ; form memory address and put it in R9 st [R9],Recx ; store(n-1)into memory and %eax,%eax // test n to set condition codes andcc R11,Reax,Reax ; test n to set condition codes jg .-0x1b // branch to top of this section if ″n>0″ jg mainloop,mainloop ; jump to main loop Host Instruction key: ld=load add=ADD st=store sub=subtract jg=jump if condition codes indicate greater andcc=and set the condition codes
Adds host instructions necessary to perform X86 address computation and upper and lower segment limit checks. mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ; form logical address into R0 chkl R0,Rss_limit ; Check logical address against segment lower limit chku R0,R_FFFFFFFF ; Check logical address against segment upper limit add R1,R0,Rss_base ; add segment base to form linear address ld Recx,[R1] ; load c from memory address in R1 into Recx mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ; form logical address into R0 chkl R2,Rss_limit ; Check logical address against segment lower limit chku R2,R_FFFFFFFF ; Check logical address against segment upper limit add R3,R2,Rss_base ; add segment base to form linear address ld Reax,[R3] ; load s from memory address in R3 into Ra mov [%eax],%ecx // store c into[s] chku Reax,Rds_limit ; Check logical address against segment upper limit add R4,Reax,Rds_base ; add segment base to form linear address st [R4],Recx ; store c into memory address s add %eax,#4 // increment s by 4 addcc Reax,Reax,4 ; increment s by 4 mov [%ebp+0x8],%eax // store(s+4) to memory add R5,Rebp,0x8 ; form logical address into R5 chkl R5,Rss_limit ; Check logical address against segment lower limit chku R5,R_FFFFFFFF ; Check logical address against segment upper limit add R6,R5,Rss_base ; add segment base to form linear address st [R6],Reax ; store(s+4)to memory address in R6 <dp n="d27"/> mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 ; form logical address into R7 chkl R7,Rss_limit ; Check logical address against segment lower limit chku R7,R_FFFFFFFF ; Check logical address against segment upper limit add R8,R7,Rss_base ; add segment base to form linear address ld Reax,[R8] ; load n from memory address in R8 into Reax lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 ; decrement n mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 ; form logical address into R9 chkl R9,Rss_limit ; Check the logical address against segment lower limit chku R9,R_FFFFFFFF ; Check logical address against segment upper limit add R10,R9,Rss_base ; add segment base to form the linear address st [R10],Recx ; store n-1 in Recx into memory using address in R10 and %eax,%eax // test n to set condition codes andcc R11,Reax,Reax ; test n to set condition codes jg .-0x1b // branch to top of this section if ″n>0″ jg mainloop,mainloop ; jump to main loop Host Instruction key: chkl+check lower limit chku=check upper limit
Adds instructions to maintain the target X86 instruction pointer “eip”and the commit instructions that use the special morph host hardware to update X86 state. mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc chkl R0,Rss_limit chku R0,R_FFFFFFFF add R1,R0,Rss_base ld Recx,[R1] add Reip,Reip,3 ; add X86 instruction length to eip in Reip commit ; commits working state to official state mov %eax, [%ebp+0x8] // load s add R2,Rebp,0x8 chkl R2,Rss_limit chku R2,R_FFFFFFFF add R3,R2,Rss_base ld Reax,[R3] add Reip,Reip,3 ; add X86 instruction length to eip in Reip commit ; commits working state to official state mov [%eax],%ecx // store c into[s] chku Reax,Rds_limit add R4,Reax,Rds_base st [R4],Recx add Reip,Reip,2 ; add X86 instruction length to eip in Reip commit ; commits working state to official state add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Reip,5 ; add X86 instruction length to eip in Reip commit ; commits working state to official state mov [%ebp+0x8],%eax // store(s+4) add R5,Rebp,0x8 chkl R5,Rss_limit chku R5,R_FFFFFFFF add R6,R5,Rss_base st [R6],Reax add Reip,Reip,3 ; add X86 instruction length to aip in Reip commit ; commits working state to official state <dp n="d29"/> mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 chkl R7,Rss_limit chku R7,R_FFFFFFFF add R8,R7,Rss_base ld Reax,[R8] add Reip,Reip,3 ; add X86 instruction length to eip in Reip commit ; commits working state to official state lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 ; add X86 instruction length to eip in Reip commit ; commits working state to official state mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 chkl R9,Rss_limit chku R9,R_FFFFFFFF add R10,R9,Rss_base st [R10],Recx add Reip,Reip,3 ; add X86 instruction length to eip in Reip commit ; commits working state to official state and %eax,%eax // test n andcc R11,Reax,Reax add Reip,Reip,3 commit ; commits working state to official state jg .-0x1b // branch ″n>0″ add Rseq,Reip,Length(jg) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit ; commits working state to official state jg mainloop,mainloop Host Instruction key: commit=copy contents of working registers to official target registers and send working stores to memory
Optimization Assumes 32 bit flat address space which allows the elimination of segment base additions and some limit checks. Win32 uses Flat 32b segmentation Record Assumptions: Rss_base==0 Rss_limit==0 Rds_base==0 Rds_limit==FFFFFFFF SS and DS protection check <dp n="d31"/> mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc chku R0,R_FFFFFFFF ld Recx,[R0] add Reip,Reip,3 commit mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 chku R2,R_FFFFFFFF ld Reax,[R2] add Reip,Reip,3 commit mov [%eax],%ecx // store c into [s] chku Reax,R_FFFFFFFF st [Reax],Recx add Reip,Reip,2 commit add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Reip,5 commit mov [%ebp+0x8],%eax //store(s+4) add R5,Rebp,0x8 chku R5,R_FFFFFFFF st [R5],Reax add Reip,Reip,3 commit mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 chku R7,R_FFFFFFFF ld Reax,[R7] add Reip,Reip,3 commit <dp n="d32"/> lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 commit mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 chku R9,R_FFFFFFFF st [R9],Recx add Reip,Reip,3 commit and %eax,%eax // test n andcc R11,Reax,Reax add Reip,Reip,3 commit jg .-0x1b // branch ″n>0″ add Rseq,Reip,Length(jg) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
Assume data addressed includes no bytes outside of computer memory limits which can only occur on unaligned page crossing memory references at the upper memory limit,and can be handled by special case software or hardware. mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ld Recx,[R0] add Reip,Reip,3 commit mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ld Reax,[R2] add Reip,Reip,3 commit mov [%eax],%ecx // store c into[s] st [Reax],Recx add Reip,Reip,2 commit add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Raip,5 commit mov [%ebp+0x8],%eax // store(s+4) add R5,Rebp,0x8 st [R5],Reax add Reip,Reip,3 commit mov %eax,[%ebp+0x10]// load n <dp n="d34"/> add R7,Rebp,0x10 ld Reax,[R7] add Reip,Reip,3 commit lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 commit mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 st [R9],Recx add Reip,Reip,3 commit and %eax,%eax // test n andcc R11,Reax,Reax add Reip,Reip,3 commit jg .-0x1b // branch ″n>0″ add Rseq,Reip,Length(jg) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop Host Instruction key: selcc=Select one of source registers and copy its contents to destination register based on condition codes.
Detect and eliminate redundant address calculations.The example shows the codeafter eliminating the redundant operation. <dp n="d35"/> after eliminating the redundant operations. mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ld Recx,[R0] add Reip,Reip,3 commit mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ld Reax,[R2] add Reip,Reip,3 commit mov [%eax],%ecx // store c into[s] st [Reax],Recx add Reip,Reip,2 commit add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Reip,5 commit mov [%ebp+0x8],%eax // store(s+4) st [R2],Reax add Reip,Reip,3 commit mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 ld Reax,[R7] add Reip,Reip,3 commit lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 commit mov [%ebp+0x10],%ecx // store(n-1) st [R7],Recx add Reip,Reip,3 commit and %eax,%eax // test n <dp n="d36"/> andcc R11,Reax,Reax add Reip,Reip,3 commit jg .-0x1b // branch ″n>0″ add Rseq,Reip,Length(jg) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
Assume that target exceptions will not occur within the translation so delay updating eip and target state mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ld Recx,[R0] mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ld Reax,[R2] mov [%eax],%ecx // store c into[s] st [Reax],Recx <dp n="d37"/> add %eax,#4 // increment s by 4 add Reax,Reax,4 mov [%ebp+0x8],%eax // store(s+4) st [R2],Reax mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 ld Reax,[R7] lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 mov [%ebp+0x10],%ecx // store(n-1) st [R7],Recx and %eax,%eax // test n andcc R11,Reax,Reax jg .-0x1b // branch ″n>0″ add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
In summary: add R0,Rebp,0xc ld Recx,[R0] add R2,Rebp,0x8 ld Reax,[R2] st [Reax],Recx add Reax,Reax,4 st [R2],Reax add R7,Rebp,0x10 ld Reax,[R7] // Live out sub Recx,Reax,1 // Live out st [R7],Recx andcc R11,Reax,Reax add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop The comment ″Live out″ refers to the need to actually maintain Reax and Recx correctly prior to the commit. otherwise further optimization might be possible.
Renaming to reduce register resource dependencies.This will allow subsequent scheduling to be more effective. From this point on, the original target X86 code is omitted as the relationship between individual target X86 instructions and host instructions becomes increasingly blurred. add R0,Rebp,0xc ld R1,[R0] add R2,Rebp,0x8 <dp n="d39"/> ld R3,[R2] st [R3],R1 add R4,R3,4 st [R2],R4 add R7,Rebp,0x10 ld Reax,[R7] // Live out sub Recx,Reax,1 // Live out st [R7],Recx andcc R11,Reax,Reax add Rseq,Reip,Length (block) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
After the scheduling process which organizes the primitive host operations as multiple operations that can execute in the parallel on the host VLIW hardware.Each line shows the parallel operations that the VLIW machine executes,and the “&” indicates the parallelism. add R2,Rebp,0x8 & add R0,Rebp,0xc nop & add R7,Rebp,0x10 ld R3, [R2] & add Rseq,Reip,Length(block) ld R1, [R0] & add R4,R3,4 st [R3],R1 & ldc Rtarg,EIP(target) ld Reax, [R7] & nop st [R2],R4 & sub Recx,Reax,1 st [R7],Recx & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg mainloop,mainloop & commit Host Instruction key: nop=no operation
Resolve host branch targets and chain stored translations add R2,Rebp,0x8 & add R0,Rebp,0xc nop & add R7,Rebp,0x10 ld R3,[R2] & add Rseq,Reip,Length(block) ld R1,[R0] & add R4,R3,4 st [R3],R1 &ldc Rtarg,EIP(target) ld Reax,[R7] & nop st [R2],R4 & sub Recx,Reax,1 st [R7],Recx & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg Sequential,Target & commit
Advanced Optirnizations,Backward Code Motion: This and subsequent examples start with the code prior to scheduling. This optimization first depends on detecting that the code is a loop. Then invariant operations can be moved out of the loop body and executed once before entering the loop body. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) Loop: ld R1,[R0] ld R3,[R2] st [R3],R1 add R4,R3,4 st [R2],R4 ld Reax,[R7] sub Recx,Reax,1
Schedule the loop body after backward code motion. For example purposes,only the code in the loop body is shown scheduled Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) Loop: ld R3,[R2] & nop ld R1,[R0] & add R4,R3,4 st [R3],R1 & nop ld Reax,[R7] & nop st [R2],R4 & sub Recx,Reax,1 st [R7],Recx & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg Sequential,Loop & commit
After Backward Code Motion: Target: add R0,Rebp,0xc add R2,Rebp,0x8 <dp n="d42"/> add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) Loop: ld R1,[R0] ld R3,[R2] st [R3],R1 add R4,R3,4 st [R2],R4 ld Reax,[R7] //Live out sub Recx,Reax,1 //Live out st [R7],Recx andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg commit jg mainloop,Loop Register allocation: This shows the use of register alias detection hardware of the morph host that allows variables to be safely moved from memory into registers.The starting point is the code after ″backward code motion″.This shows the optimization that can eliminate loads. First the loads are performed.The address is protected by the alias hardware,such that should a store to the address occur,an ″alias″ exception is raised.The loads in the loop body are then replaced with copies.After the main body of the loop,the alias hardware is freed. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) ld Rc,[R0] ;First do the load of variable from memory prot [R0],Alias1 ;Then protect memory location from stores ld Rs,[R2] prot [R2],Alias2 ld Rn,[R7] prot [R7],Alias3 Loop: copy R1,Rc copy R3,Rs st [R3],R1 add R4,Rs,4 copy Rs,R4 st [R2],Rs,NoAliasCheck copy Reax,Rn //Live out sub Recx,Reax, 1 //Live out copy Rn,Recx st [R7],Rn,noAliasCheck <dp n="d43"/> andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg commit jg Epilog,Loop Epilog: FA Alias1 Free the alias detection hardware FA Alias2 Free the alias detection hardware FA Alias3 Free the alias detection hardware j Sequential Host Instruction key: protect=protect address from loads FA=free alias copy=copy j=jump
Copy Propagation: After using the alias hardware to turn loads within the loop body into copies,copy propagation allows the elimination of some copies. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) ld Rc,[R0] prot [R0],Aliasl ld Rs,[R2] prot [R2],Alias2 ld Recx,[R7] prot [R7],Alias3 Loop: st [Rs],Rc add Rs,Rs,4 <dp n="d44"/> st [R7],Recx,NoAliasCheck andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg commit jg Epilog,Loop Epilog: FA Alias1 FA Alias2 FA Alias3 j Sequential
Example illustrating scheduling of the loop body only. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) ld Rc,[R0] prot [R0],Alias1 ld Rs,[R2] prot [R2],Alias2 ld Recx,[R7] prot [R7],Alias3 Loop: st [Rs],Rc, & add Rs,Rs,4 & copy Reax,Recx st [R2],Rs,NAC & sub Recx,Reax,1 st [R7],Recx,NAC & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg Epilog,Loop & commit <dp n="d45"/> Epilog: FA Alias1 FA Alias2 FA Alias3 j Sequential Host Instruction key: NAC=No Alias Check
Store Elimination by use ofthe alias hardware. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) ld Rc,[R0] prot [R0],Alias1 ;protect address from loads and stores ld Rs,[R2] prot [R2],Alias2 ;protect address from loads and stores ld Recx,[R7] prot [R7],Alias3 ;protect address from loads and stores Loop: st [Rs],Rc, & add Rs,Rs,4 & copy Reax,Recx sub Recx,Reax,1 & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg Epilog,Loop & commit Epilog: FA Alias1 FA Alias2 FA Alias3 st [R2],Rs ;writeback final value of Rs st [R7],Recx ;writeback final value of Recx j Sequential
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