CN1141647C - 赋予高级微处理器内存储器数据别名的方法和装置 - Google Patents
赋予高级微处理器内存储器数据别名的方法和装置 Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 194
- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000013519 translation Methods 0.000 claims description 139
- 238000003860 storage Methods 0.000 claims description 136
- 238000005457 optimization Methods 0.000 claims description 48
- 238000013461 design Methods 0.000 claims description 33
- 238000012545 processing Methods 0.000 claims description 24
- 230000004044 response Effects 0.000 claims description 12
- 238000011068 loading method Methods 0.000 claims description 10
- 238000013500 data storage Methods 0.000 claims description 7
- 230000005055 memory storage Effects 0.000 claims description 3
- 230000000052 comparative effect Effects 0.000 claims 7
- 230000014616 translation Effects 0.000 description 139
- 239000000872 buffer Substances 0.000 description 65
- 230000008569 process Effects 0.000 description 35
- 238000005516 engineering process Methods 0.000 description 30
- 238000012546 transfer Methods 0.000 description 19
- 230000008707 rearrangement Effects 0.000 description 18
- 238000012360 testing method Methods 0.000 description 15
- 241001673391 Entandrophragma candollei Species 0.000 description 13
- 230000006870 function Effects 0.000 description 13
- 238000007792 addition Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 239000000284 extract Substances 0.000 description 11
- 230000008859 change Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 238000001514 detection method Methods 0.000 description 8
- 101150006084 CHKB gene Proteins 0.000 description 6
- 230000002860 competitive effect Effects 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- 238000000605 extraction Methods 0.000 description 4
- 238000004321 preservation Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008030 elimination Effects 0.000 description 3
- 238000003379 elimination reaction Methods 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000007726 management method Methods 0.000 description 3
- 238000013507 mapping Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 241000282341 Mustela putorius furo Species 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008571 general function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 230000005291 magnetic effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000001256 tonic effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45554—Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45583—Memory management, e.g. access or allocation
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
Original C code while((n--)>0){ *s++=c } ==================================================================== Win32x86 instructions produced by a compiler compiling this C code. mov %ecx,[%ebp+0xc ] // load c from memory address into the %ecx mov %eax,[%ebp+0x8] // load s from memory address into the %eax mov [%eax],%ecx // store c into memory address s held in %eax add %eax,#4 // increment s by 4. mov [%ebp+0x8],%eax // store (s+4)back into memory mov %eax,[%ebp+0x10] // load n from memory address into the %eax lea %ecx,[%eax-1] // decrement n and store the result in %ecx mov [%ebp+0x10],%ecx // store (n-1) into memory and %eax,%eax // test n to set the condition codes jg .-0xlb // branch to the top of this section if ″n>0″
Shows each X86 Instruction shown above followed by the host instructions necessary to implement the X86 Instruction. mov %ecx,[%ebp+0xc] // load c from memory address into ecx add R0,Rebp,0xc ;form the memory address and put it in R0 ld Recx,[R0] ;load c from memory address in R0 into Recx mov %eax,[%ebp+0x8] // load s from memory address into %eax add R2,Rebp,0x8 ;form the memory address and put it in R2 ld Reax,[R2] ;load s from memory address in R2 into Recx <dp n="d29"/> mov [%eax],%ecx // store c into memory address s held in %eax st [Reax],Recx ;store c into memory address s held in Reax add %eax,#4 // increment s by 4 add Reax,Reax,4 ;increment S by 4 mov [%ebp+0x8],%eax // store (s+4) back into memory add R5,Rebp,0x8 ;form the memory address and put it in R5 st [R5],Reax ;store (s+4) back into memory mov %eax,[%ebp+0x10] // load n from memory address into %eax add R7,Rebp,0x10 ;form the memory address and put it in R7 ld Reax,[R7] ;load n from memory address into the Reax lea %ecx,[%eax-1] // decrement n and store the result in %ecx sub Recx,Reax,1 ;decrement n and store the result in Recx mov [%ebp+0x10],%ecx // store.(n-1)into memory add R9,Rebp,0x10 ;form the memory address and put it in R9 st [R9],Recx ;store (n-1) into memory and %eax,%eax // test n to set the condition codes andcc R11,Reax,Reax ;test n to set the condition codes jg .-0x1b // branch to the top of this section if ″n>0″ jg mainloop,mainloop ;jump to the main loop Host Instruction key: ld=load add=ADD st=store sub=subtract jg=jump if condition codes indicate greater andcc=and set the condition codes
mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ;form logical address into R0 chkl R0,Rss_limit ;Check the logical address against segment lower limit chku R0,R_FFFFFFFF ;Check the logical address against segment upper limit add R1,R0,Rss_base ;add the segment base to form the linear address ld Recx,[R1] ;load c from memory address in R1 into Recx mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ;form logical address into R0 chkl R2,Rss_limit ;Check the logical address against segment lower limit chku R2,R_FFFFFFFF ;Check the logical address against segment upper limit add R3,R2,Rss_base ;add the segment base to form the linear address ld Reax,[R3] ;load s from memory address in R3 into Ra mov [%eax],%ecx // store c into [s] chku Reax,Rds_limit ;Check the logical address against segment upper limit add R4,Reax,Rds_base ;add the segment base to form the linear address st [R4],Recx ;store c into memory address s add %eax,#4 // increment s by 4 addcc Reax,Reax,4 ;increment s by 4 mov [%ebp+0x8],%eax // store (s+4) to memory add R5,Rebp,0x8 ;form logical address into R5 chkl R5,Rss_limit ;Check the logical address against segment lower limit chku R5,R_FFFFFFFF ;Check the logical address against segment upper limit add R6,R5,Rss_base ;add the segment base to form the linear address st [R6],Reax ;store (s+4) to memory address in R6 mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 ;form logical address into R7 chkl R7,Rss_limit ;Check the logical address against segment <dp n="d31"/> lower limit chku R7,R_FFFFFFFF ;Check the logical address against segment upper limit add R8,R7,Rss_base ;add the segment base to form the linear address ld Reax,[R8] ;load n from memory address in R8 into Reax lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 ;decrement n mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 ;form logical address into R9 chkl R9,Rss_limit ;Check the logical address against segment lower limit chku R9,R_FFFFFFFF ;Check the logical address against segment upper limit add R10,R9,Rss_base ;add the segment base to form the linear address st [R10],Recx ;store n-1 in Recx into memory using address in R10 and %eax,%eax // test n to set the condition codes andcc R11,Reax,Reax ;test n to set the condition codes jg .-0x1b // branch to the top of this section if ″n>0″ jg mainloop,mainloop ;jump to the main loop Host Instruction key: chkl+check lower limit chku=check upper limit
Adds instructions to maintain the target X86 instruction pointer“eip”and the commit instructions that use the special morph host hardware to update X86 state. mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc chkl R0,Rss_limit chku R0,R_FFFFFFFF add R1,R0,Rss_baseld Recx,[R1] add Reip,Reip,3 ;add X86 instruction length to eip in Reip commit ;commits working state to official state mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 chkl R2,Rss_limit chku R2,R_FFFFFFFF add R3,R2,Rss_base ld Reax,[R3] add Reip,Reip,3 ;add X86 instruction length to eip in Reip commit ;commits working state to official state mov [%eax],%ecx // store c into[s] chku Reax,Rds_limit add R4,Reax,Rds_base st [R4],Recx add Reip,Reip,2 ;add X86 instruction length to eip in Reip commit ;commits working state to official state add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Reip,5 ;add X86 imstruction length to eip in Reip commit ;commits working state to official state mov [%ebp+0x8],%eax // store(s+4) add R5,Rebp,0x8 chkl R5,Rss_limit chku R5,R_FFFFFFFF add R6,R5,Rss_base st [R6],Reax add Reip,Reip,3 ;add X86 instruction length to eip in Reip commit ;commits working state to official state <dp n="d33"/> mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 chkl R7,Rss_limit chku R7,R_FFFFFFFF add R8,R7,Rss_base ld Reax,[R8] add Reip,Reip,3 ;add X86 instruction length to eip in Reip commit ;commits working state to official state lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 ;add X86 instruction length to eip in Reip commit ;commits working state to official state mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 chkl R9,Rss_limit chku R9,R_FFFFFFFF add R10,R9,Rss_base st [R10],Recx add Reip,Reip,3 add X86 instruction length to eip in Reip commit ;commits working state to official state and %eax,%eax // test n andcc R11,Reax,Reax add Reip,Reip,3 commit ;commits working state to official state jg .-0x1b // branch″n>0 ″ add Rseq,Reip,Length(jg) ldc Rtarg,EIp(target) selcc Reip,Rseq,Rtarg commit ;commits working state to official state jg mainloop,mainloop Host Instruction key: commit= copy the contents of the working registers to the official target registers and send working stores to memory
Assumes 32 bit flat address space which allows the elimination of segment base additions and some limit checks. Win32 uses Flat 32b segmentation Record Assumptions: Rss_base==0 Rss_limit==0 Rds_base==0 Rds_limit==FFFFFFFF SS and DS protection check <dp n="d35"/> mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc chku R0,R_FFFFFFFF ld Recx,[R0] add Reip,Reip,3 commit mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 chku R2,R_FFFFFFFF ld Reax,[R2] add Reip,Reip,3 commit mov [%eax],%ecx // store c into[s] chku Reax,R_FFFFFFFF st [Reax],Recx add Reip,Reip,2 commit add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Reip,5 commit mov [%ebp+0x8],%eax // store(s+4) add R5,Rebp,0x8 chku R5,R_FFFFFFFF st [R5],Reax add Reip,Reip,3 commit mov %eax,[%ebp+0x10] // load n <dp n="d36"/> add R7,Rebp,0x10 chku R7,R_FFFFFFFF ld Reax,[R7] add Reip,Reip,3 commit lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 commit mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 chku R9,R_FFFFFFFF st [R9],Recx add Reip,Reip,3 commit and %eax,%eax // test n andcc R11,Reax,Reax add Reip,Reip,3 commit jg .-0x1b // branch″n>0″ add Rseq,Reip,Length(jg) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ld Recx,[R0] add Reip,Reip,3 commit mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ld Reax,[R2] add Reip,Reip,3 commit mov [%eax],%ecx // store c into [s] st [Reax],Recx add Reip,Reip,2 commit add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Reip,5 commit mov [%ebp+0x8],%eax // store(s+4) add R5,Rebp,0x8 st [R5],Reax add Reip,Reip,3 commit mov %eax,[%ebp+0x10] // load n <dp n="d38"/> add R7,Rebp,0x10 ld Reax,[R7] add Reip,Reip,3 commit lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 commit mov [%ebp+0x10],%ecx // store(n-1) add R9,Rebp,0x10 st [R9],Recx add Reip,Reip,3 commit and %eax,%eax // test n andcc R11,Reax,Reax add Reip,Reip,3 commit jg .-0x1b // branch″n>0″ add Rseq,Reip,Length(jg) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop Host Instruction key: selcc = Select one of the source registers and copy its contents to the destination register based on the condition codes.
Detect and eliminate redundant address calculations.The example shows the code after eliminating the redundant operations. mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ld Recx,[R0] add Reip,Reip,3 commit mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ld Reax,[R2] add Reip,Reip,3 commit mov [%eax],%ecx // store c into [s] st [Reax],Recx add Reip,Reip,2 commit add %eax,#4 // increment s by 4 addcc Reax,Reax,4 add Reip,Reip,5 commit mov [%ebp+0x8],%eax // store(s+4) st [R2],Reax add Reip,Reip,3 commit mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 ld Reax,[R7] add Reip,Reip,3 commit lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 add Reip,Reip,3 commit mov [%ebp+0x10],%ecx // store(n-1) st [R7],Recx add Reip,Reip,3 commit <dp n="d40"/> and %eax,%eax // test n andcc R11,Reax,Reax add Reip,Reip,3 commit jg .-0x1b // branch″n>0″ add Rseq,Reip,Length(jg) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
Assume that target exceptions will not occur within the translation so delay updating eip and target state. mov %ecx,[%ebp+0xc] // load c add R0,Rebp,0xc ld Recx,[R0] mov %eax,[%ebp+0x8] // load s add R2,Rebp,0x8 ld Reax,[R2] mov [%eax],%ecx // store c into [s] st [Reax],Recx <dp n="d41"/> add %eax,#4 // increment s by 4 add Reax,Reax,4 mov [%ebp+0x8],%eax // store(s+4) st [R2],Reax mov %eax,[%ebp+0x10] // load n add R7,Rebp,0x10 ld Reax,[R7] lea %ecx,[%eax-1] // decrement n sub Recx,Reax,1 mov [%ebp+0x10],%ecx // store(n-1) st [R7],Recx and %eax,%eax // test n andcc R11,Reax,Reax jg .-0x1b // branch″n>0″ add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
In summary: add R0,Rebp,0xc ld Recx,[R0] add R2,Rebp,0x8 ld Reax,[R2] st [Reax],Recx add Reax,Reax,4 st [R2],Reax add R7,Rebp,0x10 ld Reax,[R7] // Live out sub Recx,Reax,1 // Live out st [R7],Recx andcc R11,Reax,Reax add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop The comment″Live Out″refers to the need to actually maintain Reax and Recx correctly prior to the commit.Otherwise further optimization might be possible. ====================================================================
Renaming to reduce register resource dependencies.This will allow subsequent scneduling to be more effective.From this point on,the original target X86 code is omitted as the relationship between individual target X86 instructions and host instructions becomes increasingly blurred. add R0,Rebp,0xc ld R1,[R0] add R2,Rebp,0x8 ld R3,[R2] st [R3],R1 <dp n="d43"/> add R4, R3,4 st [R2],R4 add R7,Rebp,0x10 ld Reax,[R7] // Live out sub Recx,Reax,1 // Live out st [R7],Recx andcc R11,Reax,Reax add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) selcc Reip,Rseq,Rtarg commit jg mainloop,mainloop
After the scheduling process which organizes the primitive host operations as multiple operations that can execute in the parallel on the host VLIW hardware.Each line shows the parallel operations that the VLIW machine executes,and the“&”indicates the parallelism. add R2,Rebp,0x8 & add R0,Rebp,0xc nop & add R7,Rebp,0x10 ld R3,[R2] & add Rseq,Reip,Length(block) ld R1,[R0] & add R4,R3,4 st [R3],R1 & ldc Rtarg,EIP(target) ld Reax,[R7] & nop st [R2],R4 & sub Recx,Reax,1 st [R7],Recx & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg mainloop,mainloop & commit Host Instruction key: nop=no operation
Resolve host branch targets and chain stored translations add R2,Rebp,0x8 & add R0,Rebp,0xc nop & add R7,Rebp,0x10 ld R3,[R2] & add Rseq,Reip,Length(block) ld R1,[R0] & add R4,R3,4 st [R3],R1 & ldc Rtarg,EIP(target) ld Reax,[R7] & nop st [R2],R4 & sub Recx,Reax,1 st [R7],Recx & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg Sequential,Target & commit
Advanced Optimizations,Backward Code Motion: This and subsequent examples start with the code prior to scheduling. This optimization first depends on detecting that the code is a loop. Then invariant operations can be moved out of the loop body and executed once before entering the loop body. entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) Loop: ld R1,[R0] ld R3,[R2] st [R3],R1 add R4,R3,4 st [R2],R4 ld Reax,[R7] sub Recx,Reax,1 st [R7],Recx andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg commit jg mainloop,Loop
Schedule the loop body after backward code motion.For example purposes,only the code in the loop body is shown scheduled Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIp(target) Loop: ld R3,[R2] & nop ld R1,[R0] & add R4,R3,4 st [R3],R1 & nop ld Reax,[R7] & nop st [R2],R4 & sub Recx,Reax,1
After Backward Code Motion: Target: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) Loop: <dp n="d46"/> ld R1,[R0] ld R3,[R2] st [R3],R1 add R4,R3,4 st [R2],R4 ld Reax,[R7] // Live out sub Recx,Reax,1 // Live out st [R7],Recx andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg commit jg mainloop,Loop ==================================================================== Register Allocation: This shows the use of register alias detection hardware of the morph host that allows variables to be safely moved from memory into reqisters.The starting point is the code after″backward code motion″. This shows the optimization that can eliminate loads. First the loads are performed.The address is protected by the alias hardware,such that should a store to the address occur,an″alias″ exception is raised. The loads in the loop body are then replaced with copies.After the main body of the loop,the alias hardware is freed. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIp(target) ld Rc,[R0] ;First do the load of the variable from memory prot [R0],Alias1 ;Then protect the memory location from stores ld Rs,[R2] prot [R2],Alias2 ld Rn,[R7] prot [R7],Alias3 Loop: copy R1,Rc copy R3,Rs st [R3],R1 add R4,Rs,4 copy Rs,R4 st [R2],Rs,NoAliasCheck copy Reax,Rn // Live out sub Recx,Reax,1 // Live out copy Rn,Recx <dp n="d47"/> Epilog: FA Alias1 Free the alias detection hardware FA Alias2 Free the alias detection hardware FA Alias3 Free the alias detection hardware j Sequential Host Instruction key: protect=protect address from loads FA=free alias copy=copy j=jump
Copy Propagation: After using the alias hardware to turn loads within the loop body into copies,copy propagation allows the elimination of some copies. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) ld Rc,[R0] prot [R0],Alias1 ld Rs,[R2] prot [R2],Alias2 ld Recx,[R7] prot [R7],Alias3 <dp n="d48"/> Loop: st [Rs],Rc add Rs,Rs,4 st [R2],Rs,NoAliasCheck copy Reax,Recx // Live out sub Recx,Reax,1 // Live out st [R7],Recx,NoAliasCheck andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg commit jg Epilog,Loop Epilog: FA Alias1 FA Alias2 FA Alias3 j sequential
Example illustrating scheduling of the loop body only. Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) ld Rc,[R0] prot [R0],Alias1 ld Rs,[R2] prot [R2],Alias2 ld Recx,[R7] prot [R7],Alias3 Loop: <dp n="d49"/> st [Rs],Rc, & add Rs,Rs,4 & copy Reax,Recx st [R2],Rs,NAC & sub Recx,Reax,1 st [R7],Recx,NAC & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg Epilog,Loop & commit Epilog: FA Alias1 FA Alias2 FA Alias3 j sequential
Store Elimination by use of the alias hardware Entry: add R0,Rebp,0xc add R2,Rebp,0x8 add R7,Rebp,0x10 add Rseq,Reip,Length(block) ldc Rtarg,EIP(target) ld Rc,[R0] prot [R0],Alias1 ;protect the address from loads and stores ld Rs,[R2] prot [R2],Alias2 ;protectthe address from loads and stores ld Recx,[R7] prot [R7],Alias3 ;protect the address from loads and stores Loop: st [Rs ],Rc, & add Rs,Rs,4 & copy Reax,Recx sub Recx,Reax,1 & andcc R11,Reax,Reax selcc Reip,Rseq,Rtarg & jg Epilog,Loop & commit Epilog: FA Alias1 FA Alias2 FA Alias3 st [R2],Rs ;writeback the final value of Rs st [R7],Recx ;writeback the final value of Recx j sequential
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US08/721,698 US5926832A (en) | 1996-09-26 | 1996-09-26 | Method and apparatus for aliasing memory data in an advanced microprocessor |
US08/721,698 | 1996-09-26 |
Publications (2)
Publication Number | Publication Date |
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CN1241272A CN1241272A (zh) | 2000-01-12 |
CN1141647C true CN1141647C (zh) | 2004-03-10 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB971800278A Expired - Lifetime CN1141647C (zh) | 1996-09-26 | 1997-09-22 | 赋予高级微处理器内存储器数据别名的方法和装置 |
Country Status (9)
Country | Link |
---|---|
US (1) | US5926832A (zh) |
EP (1) | EP1008050B1 (zh) |
JP (1) | JP3753743B2 (zh) |
KR (1) | KR100385426B1 (zh) |
CN (1) | CN1141647C (zh) |
AT (1) | ATE355558T1 (zh) |
CA (1) | CA2262928C (zh) |
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WO (1) | WO1998013740A2 (zh) |
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-
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- 1997-09-22 DE DE69737423T patent/DE69737423T2/de not_active Expired - Lifetime
- 1997-09-22 EP EP97944366A patent/EP1008050B1/en not_active Expired - Lifetime
- 1997-09-22 KR KR10-1999-7002571A patent/KR100385426B1/ko not_active IP Right Cessation
- 1997-09-22 CA CA002262928A patent/CA2262928C/en not_active Expired - Fee Related
- 1997-09-22 JP JP51579998A patent/JP3753743B2/ja not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
---|---|
KR100385426B1 (ko) | 2003-05-27 |
US5926832A (en) | 1999-07-20 |
JP2001504957A (ja) | 2001-04-10 |
KR20000048630A (ko) | 2000-07-25 |
JP3753743B2 (ja) | 2006-03-08 |
EP1008050B1 (en) | 2007-02-28 |
WO1998013740A3 (en) | 1998-07-02 |
CN1241272A (zh) | 2000-01-12 |
CA2262928C (en) | 2001-01-30 |
EP1008050A2 (en) | 2000-06-14 |
DE69737423D1 (de) | 2007-04-12 |
ATE355558T1 (de) | 2006-03-15 |
EP1008050A4 (en) | 2001-08-16 |
DE69737423T2 (de) | 2007-11-08 |
WO1998013740A2 (en) | 1998-04-02 |
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