CN116382636A - Method and system for generating correlation random bit stream - Google Patents
Method and system for generating correlation random bit stream Download PDFInfo
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Abstract
The invention provides a method and a system for generating a correlation random bit stream, which belong to the technical field of storage and calculation, wherein a series of pulse sequences with fixed amplitude and pulse width are applied to a device with integrated resistance change and selection characteristics, so that the device is randomly started under each pulse, and a 0/1 random bit stream sequence is correspondingly generated; in a pulse sequence under a fixed pulse condition, reset-set pulse pairs are inserted, a device is set to be in a nonvolatile resistance variable mode through the reset pulse, a random bit stream signal generated under the original pulse condition is set to be 0, then the device is reset to be in a volatile threshold switch mode through the set pulse, and the number of the reset-set pulse pairs is controlled to realize the probability of 0-P base The random bit stream adjustment in between, the positions of the inserted 0 s between the control input bit streams are the same, thereby enhancing the correlation between the input bit streams.
Description
Technical Field
The invention belongs to the technical field of novel storage and calculation, and particularly relates to a method, a system, electronic equipment and a storage medium for generating a correlation random bit stream.
Background
As device dimensions continue to shrink toward the nanometer scale, circuit reliability will become an increasingly serious problem.
The random computation (Stochastic Computing, SC) is a new computation method based on a random bit stream sequence consisting of 0/1, and has the advantages of simple circuit, low power consumption, high fault tolerance and the like, and has been paid attention in recent years. Unlike binary coding, each bit in the random bit stream has equal weight, and errors caused by bit flipping on any bit are equal, so that the random calculation has higher fault tolerance. Meanwhile, due to the unique data coding mode, complex arithmetic operations can be realized by using a simple gate circuit, such as multiplication by using only one AND gate.
The accuracy of the random calculation depends on two aspects: firstly, the numerical quantization precision determined by the length of the random bit stream, namely, the data generates certain error after being converted into the random bit stream from binary system; and secondly, the calculation accuracy is affected by the correlation between random bit streams. Quantization errors in the data encoding process can be reduced to some extent by extending the length of the random bit stream. In order to improve the calculation accuracy, it is necessary to use different random bit stream generation circuits that generate strong/weak correlation. The random bit streams require that the input random bit streams have mutually independent characteristics when multiplied by and gate, i.e. the weaker the correlation between the input random bit streams, the higher the calculation accuracy. While an input random bit stream with strong correlation may achieve some specific calculations by simple gates, such as minimum by and gates, maximum by or gates, absolute value subtraction by exclusive or gates, etc.
The need to introduce additional decorrelation or correlation-enhancing circuitry into conventional CMOS-based random computation circuits to generate random bit streams or correlated bit streams that are independent of each other further increases circuit overhead and power consumption, and the circuitry is difficult to reconstruct for different computation tasks. While random bit stream generators designed based on new memory devices such as Resistive Random Access Memory (RRAM), threshold switch select devices, etc. can reduce power consumption and circuit overhead, no technology for controlling the generation of bit stream correlations based on such new memory devices has been disclosed.
Accordingly, there is a need for a technique for implementing control and generation of bit stream dependencies in a new memory device.
Disclosure of Invention
The invention provides a method, a system, electronic equipment and a storage medium for generating a correlation random bit stream based on a novel resistance change storage device, which are used for overcoming at least one technical problem in the prior art.
To achieve the above object, the present invention provides a method of generating a correlation random bit stream, comprising:
a device with integrated resistance change and selection characteristics is adopted, delay time started in the selection characteristics of the device is used as a random source, and a random bit stream is generated under the preset pulse condition; wherein the probability of "1" in the random bit stream is a reference probability;
dividing the pulse sequence of the random bit stream into N averagely segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, putting the device back into a resistive switching mode by using a reset signal, and setting a bit stream signal generated under the preset pulse condition to be 0;
restarting generation of a random bit stream under the preset pulse condition by adopting a set signal so as to reset the device back to a volatile threshold switch mode;
and generating two random bit streams by using the device, controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, and enabling 0 bits inserted into the two random bit streams to coincide so as to enhance the correlation between the random bit streams.
In order to solve the above problems, the present invention also provides a system for generating a correlation random bit stream, comprising:
the device comprises an initial random bit stream generation unit, a random bit stream generation unit and a random bit stream generation unit, wherein the initial random bit stream generation unit is used for adopting a device with integrated resistance change and selection characteristics, taking delay time started in the selection characteristics of the device as a random source, and generating a random bit stream under the preset pulse condition; wherein the probability of "1" in the random bit stream is a reference probability;
a pulse sequence processing unit for equally dividing the pulse sequence of the random bit stream into N segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, putting the device back into a resistive switching mode by using a reset signal, and setting a bit stream signal generated under the preset pulse condition to be 0;
a device reset unit for restarting generation of a random bit stream under the preset pulse condition by adopting a set signal so as to reset the device back to a volatile threshold switch mode;
and the pulse regulating and controlling unit is used for generating two random bit streams by utilizing the device, controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, and enabling 0 bits inserted into the two random bit streams to coincide so as to enhance the correlation between the random bit streams.
In order to solve the above problems, the present invention also provides an electronic device including at least one processor; and a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform steps in a method of generating a dependency random bit stream as previously described.
In order to solve the above-mentioned problems, the present invention also provides a computer readable storage medium having stored therein at least one instruction which when executed by a processor in an electronic device implements the above-mentioned method of generating a dependency random bit stream.
The method, the system, the electronic equipment and the storage medium for generating the correlation random bit stream have the following beneficial effects:
1) Compared with a circuit for controlling the correlation of bit streams in a traditional CMOS circuit, the invention can realize the generation of the correlation random bit streams in the novel resistive random access device without introducing an additional correlation control circuit, thereby reducing the circuit cost and the power consumption.
2) The random bit stream is generated by utilizing the novel resistive device, and the bit generation rate is higher due to the nanosecond conversion speed of the novel resistive device.
3) The invention can realize the probability of 0-P by controlling the number of the inserted reset-set pulse pairs base Random bit stream adjustments in between.
4) The invention can adjust the calculation accuracy of the correlation random bit stream by controlling the segmentation number under the condition of fixed bit stream length.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for generating a correlated random bit stream according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a correlation random bit stream for different calculations by a basic gate unit according to an embodiment of the invention;
FIG. 3 is a diagram of a control-inserted reset-set pulse pair-wise identical resulting correlation random bit stream according to an embodiment of the present invention;
FIG. 4 (a) is a diagram showing the variation of the error of the absolute value subtraction calculation of the generated correlation random bit stream by the exclusive OR gate according to the embodiment of the present invention with the bit stream length and the segment number;
FIG. 4 (b) is a schematic diagram showing the variation of the error of the correlation random bit stream with the bit stream length after the optimized segment number is obtained, and the absolute value of the correlation random bit stream is subtracted by the exclusive OR gate according to the embodiment of the present invention;
FIG. 5 (a) is a graph showing the variation of error in minimum calculation of a correlation random bit stream by AND gate with bit stream length and segment number, according to an embodiment of the present invention;
FIG. 5 (b) is a diagram showing the variation of the error of the correlation random bit stream with the minimum value calculation by AND gate according to the optimized segment number of the embodiment of the present invention;
FIG. 6 (a) is a graph showing the variation of the error of maximum value calculation by OR gate of the generated correlation random bit stream according to the embodiment of the present invention with the bit stream length and the segment number;
FIG. 6 (b) is a diagram showing the variation of the error of the correlation random bit stream with the length of the bit stream after the optimized number of segments is calculated by OR gate maximum value according to the embodiment of the present invention;
FIG. 7 is a block diagram of a system for generating a correlated random bit stream according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of the internal architecture of an electronic device implementing a method of generating a correlated random bit stream according to an embodiment of the invention;
the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Based on the above-mentioned problems in the prior art, the present invention mainly provides a method and a system for generating a correlation random bit stream.
Fig. 1 is a flowchart of a method for generating a correlation random bit stream according to an embodiment of the invention. The method may be performed by a system, which may be implemented in software and/or hardware.
Fig. 1 depicts a method of generating a correlated random bit stream in its entirety. As shown in fig. 1, in the present embodiment, the method of generating a correlation random bit stream includes steps S110 to S140.
S110, using a device with integrated resistance change and selection characteristics as a random source, and generating a random bit stream under a preset pulse condition by taking the delay time started in the selection characteristics of the device as a random source;
s120, equally dividing the pulse sequence of the random bit stream into N segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, putting the device back into a resistive switching mode by using a reset signal, and setting a bit stream signal generated under the preset pulse condition to be 0;
s130, restarting generation of a random bit stream under the preset pulse condition by adopting a set signal so as to reset the device back to a volatile threshold switch mode;
s140, generating two random bit streams by using the device, and controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, so that 0 bits inserted into the two random bit streams are overlapped to enhance the correlation between the random bit streams.
Compared with the traditional scheme of generating the correlation bit stream based on the CMOS circuit, the invention generates the correlation random bit stream based on the novel resistive device, the generation circuit of the random bit stream is simpler and has lower power consumption, and the bit generation rate is higher because of the nanosecond conversion speed of the novel resistive device, if the crisscrossed array structure is utilized at the same time, corresponding pulses are applied to a column/row of devices in the array at the same time, each device generates different responses corresponding to 0 bit and 1 bit in the bit stream, thereby generating the correlation random bit stream in large-scale parallel and further reducing delay.
The steps are described in detail below.
In order to generate a correlation random bit stream based on a novel resistive random access memory, a delay time for turning on a device in a selection characteristic is first required to be used as a random source, and the random bit stream is generated under a preset pulse condition.
The device integrating the resistance change and the selection characteristic is used as a device for generating random bit stream, and the delay time of opening in the selection characteristic of the device is used as a random source to be used in the pre-preparationLet the probability of "1" in the random bit stream generated under the pulse condition be the reference probability P base 。
The device with integrated resistance change and selection characteristics is a two-end device structure or a three-end field effect transistor structure which is formed by superposing a resistance change layer and a phase change layer. The resistance-selection characteristic integrated device is switchable between a nonvolatile resistance change mode and a volatile threshold switch mode by voltage regulation. Namely, the device can be converted into a nonvolatile resistance change mode from a volatile threshold switch mode through a higher negative reset voltage; with a higher forward set voltage, the device can be set from nonvolatile mode to volatile threshold switch mode. And the resistance-variable voltage V of the device in the nonvolatile resistance-variable mode set Greater than threshold transition voltage V in volatile threshold switch mode th 。
In one embodiment of the invention, the device with integrated resistance-selection characteristics used in the random bit stream generator adopts a structure that a resistance-changing layer is overlapped with a phase-changing layer, wherein the resistance-changing layer can adopt metal oxide with resistance-changing characteristics, such as HfO 2 、TaO x Etc.; the phase-change layer may be made of phase-change material having insulator-metal-transition (IMT) characteristics, such as VO x 、NbO x Etc.
Since the device may undergo a metal-insulator transition (IMT) in a volatile threshold switching mode, the transition process may be affected by thermal disturbances, and thus the threshold transition voltage of the corresponding device may fluctuate during different current-voltage scan cycles. With this feature, if a series of pulse sequences of fixed amplitude and pulse width are applied to the device, the device will randomly turn on at each pulse, correspondingly producing a 0/1 random bit stream sequence. Therefore, after the delay time of turning on in the device selection characteristic is used as a random source, the pulse sequence with fixed amplitude and pulse width is used as a fixed pulse, so that the device generates a random bit stream under the fixed pulse, and the probability of the middle '1' of the random bit stream can be regarded as a reference probability P base 。
Specifically, as an example, the preset pulse conditions for generating a random bit stream are: the pulse amplitude is in the fluctuation interval of the threshold voltage, and the pulse width of the pulse is the average value of the device turn-on delay time counted under the corresponding pulse amplitude.
After generating random bit stream under preset pulse condition, dividing pulse sequence of the generated random bit stream into N segment Segments, from which N is arbitrarily selected slot Segment of selected N slot In the segment pulse sequence, a reset-set pulse pair is inserted, and the device is placed into a nonvolatile resistance change mode through the reset pulse, so that the resistance change voltage V of the device in the nonvolatile resistance change mode is realized set Higher than threshold transition voltage V in volatile threshold switch mode th Therefore, the device will not be randomly turned on under the original pulse, all producing 0 bits.
The generation of the random bit stream is then turned back on by a set pulse to reset the device back to the volatile threshold switching mode. At this time, the probability of "1" in the obtained random bit stream is P m ＝P base *
(N segment －N slot )/N segment Thereby achieving probability adjustment of "1" in the random bit stream.
By controlling the number of reset-set pulse pairs, a probability of 0-P can be achieved base Random bit stream adjustments in between.
Thus, by the above method of generating a random bit stream, two random bit streams can be generated using the same device under the control of the reset-set pulse pair, or two random bit streams can be simultaneously generated in parallel by two devices. The reset-set pulse pair corresponds to a control signal generated by the bit stream, and the positions of the reset-set pulse pair inserted in the two random bit streams are controlled to be the same, namely 0 bits inserted in the two random bit streams are overlapped. Since the positions of 0/1 between different random bit streams are identical in the random bit streams with strong correlation, based on the above scheme for generating random bit streams, the positions of 0 inserted between random bit streams can be controlled to be identical, i.e., the positions of reset-set pulse pairs inserted are controlled to be identical, thereby enhancing the correlation between random bit streams for calculation of maximum, minimum and absolute value subtraction.
In the random bit stream generation method, the number of segments N is the same as the number of segments N segment The randomness of the bit stream is affected, so that the calculation accuracy is further affected, and therefore, the calculation accuracy of the correlation random bit stream can be adjusted by controlling the number of segments under the condition of fixed bit stream length.
As an example, in the process of controlling the number of segments, the pulse generating conditions may be adjusted by the pulse sequence processing unit in the process of generating the correlation random bit stream, thereby realizing different number of pulse segments, and further adjusting the calculation accuracy of the correlation random bit stream by the different number of pulse segments.
An example of the application of the method for generating a correlated random bit stream according to the present invention to the calculation of maximum, minimum and absolute subtraction to improve the calculation accuracy will be described in more detail below with reference to fig. 2 to 6 (b).
Fig. 2 is a schematic diagram showing different calculations of the correlation random bit stream by the basic gate circuit unit, and as shown in fig. 2, the calculation of absolute value subtraction, maximum value and minimum value can be completed after the correlation random bit stream passes through the exclusive or gate, the or gate and the and gate. There is more overlap in the 0/1 positions in the random bit stream with correlation.
FIG. 3 is a schematic diagram of a correlated random bit stream obtained by controlling the insertion of reset-set pulses to have the same position in an embodiment of the present invention. As shown in fig. 3, the present invention implements a correlated bit stream by controlling the position overlapping of the inserted reset-set pulse pair, thereby causing the positions of 0 bits in two random bit streams to largely overlap, and thus can enhance the correlation between bit streams.
FIG. 4 (a) is a graph showing the variation of the error of the correlation random bit stream generated in the embodiment of the present invention according to the length of the bit stream and the number of segments by subtracting the absolute value of the correlation random bit stream from the absolute value of the correlation random bit stream by the exclusive OR gate; fig. 4 (b) shows the variation of the error of the correlation random bit stream calculated by subtracting the absolute value of the correlation random bit stream by the xor gate with the length of the bit stream after optimizing the number of segments in the embodiment of the present invention.
As shown in fig. 4 (a), with the method of generating a correlation random bit stream in the present invention, the generated correlation bit stream is subjected to absolute value subtraction calculation by an exclusive or gate. The calculation error fluctuates with the number of segments at different bit stream lengths. After the optimization of the number of segments, the lowest calculation error under the corresponding bit stream length is obtained, as shown in fig. 4 (b). The lowest error at different bit stream lengths decreases with increasing bit stream length, with a corresponding lowest calculated error of 5.4% for a bit stream length of 1024.
FIG. 5 (a) is a graph showing the variation of the error of the correlation random bit stream generated in the embodiment of the present invention, which is calculated by minimum value through AND gate, with the bit stream length and the number of segments; fig. 5 (b) shows the variation of the error of the correlation random bit stream calculated by the and gate with the minimum value after optimizing the number of segments according to the embodiment of the present invention.
As shown in fig. 5 (a), with the method of generating a correlation random bit stream in the present invention, the generated correlation bit stream is subjected to minimum value calculation by and gate. The calculation error fluctuates with the number of segments at different bit stream lengths. After the optimization of the number of segments, the lowest calculation error under the corresponding bit stream length is obtained, as shown in fig. 5 (b). The lowest error at different bit stream lengths decreases with increasing bit stream length, with a corresponding lowest calculated error of 2.9% in the case of 1024 bit stream lengths.
FIG. 6 (a) is a graph showing the variation of the error of maximum value calculation of the correlation random bit stream by OR gate with the bit stream length and the number of segments, which is generated in the embodiment of the present invention; fig. 6 (b) shows the variation of the error of the correlation random bit stream calculated by the maximum value through the or gate with the bit stream length after optimizing the number of segments in the embodiment of the present invention.
As shown in fig. 6 (a), with the method of generating a correlation random bit stream in the present invention, the generated correlation bit stream is subjected to a maximum value calculation by an or gate. The calculation error fluctuates with the number of segments at different bit stream lengths. After the optimization of the number of segments, the lowest calculation error under the corresponding bit stream length is obtained, as shown in fig. 6 (b). The lowest error at different bit stream lengths decreases with increasing bit stream length, with a corresponding lowest calculated error of 2.6% in the case of 1024 bit stream lengths.
Therefore, the random bit stream with stronger correlation can be generated by controlling the position overlapping of the inserted reset-set pulse pair based on the novel resistive random storage device, and higher calculation precision can be obtained by optimizing the segmentation number in the calculation of absolute value subtraction, minimum value and maximum value.
Corresponding to the method for generating the correlation random bit stream, the invention also provides a system for generating the correlation random bit stream, and the invention can be installed in electronic equipment. Fig. 7 is a schematic diagram of a logic structure of a system for generating a correlation random bit stream according to an embodiment of the present invention.
As shown in fig. 7, the system 700 for generating a correlation random bit stream may include an initial random bit stream generating unit 710, a pulse sequence processing unit 720, a device resetting unit 730, and a pulse conditioning unit 740 according to the implemented functions. The inventive unit, which may also be referred to as a module, refers to a series of computer program segments, which are stored in the memory of the electronic device, capable of being executed by the processor of the electronic device and of performing a fixed function.
In the present embodiment, the functions concerning the respective modules/units are as follows:
an initial random bit stream generating unit 710, configured to generate a random bit stream under a preset pulse condition by using a device with integrated resistance-selection characteristics and using a delay time of the device, which is turned on in the selection characteristics, as a random source; wherein the probability of "1" in the random bit stream is the reference probability P base ；
A pulse sequence processing unit 720 for equally dividing the pulse sequence of the random bit stream into N segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, putting the device back into a resistive switching mode by using a reset signal, and setting a bit stream signal generated under the preset pulse condition to be 0;
a device reset unit 730 for restarting the generation of the random bit stream under the preset pulse condition by using a set signal to reset the device back to the volatile threshold switch mode;
and the pulse regulating unit 740 is used for generating two random bit streams by using the device, controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, and enabling the 0 bits inserted into the two random bit streams to coincide so as to enhance the correlation between the random bit streams.
The system 700 for generating the correlation random bit stream generates the correlation random bit stream based on the novel resistive device, the generation circuit of the random bit stream is simpler, the power consumption is lower, the bit generation rate is higher due to the nanosecond conversion speed of the novel resistive device, and meanwhile, the correlation random bit stream can be generated in large-scale parallel by utilizing the crisscrossed array structure of the novel resistive device, so that the delay is further reduced.
As shown in fig. 8, the present invention provides an electronic device for a method of generating a correlation random bit stream.
The electronic device 8 may comprise a processor 80, a memory 81 and a bus, and may further comprise a computer program stored in the memory 81 and executable on said processor 80, such as a program 82 for generating a dependency random bit stream. The memory 81 may also include both internal and external memory units of the system generating the correlated random bit stream. The memory 81 may be used not only for storing codes or the like of programs installed in application software and various types of data, such as a generation of a correlation random bit stream, but also for temporarily storing data that has been output or is to be output.
The memory 81 includes at least one type of readable storage medium including flash memory, a mobile hard disk, a multimedia card, a card memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, etc. The memory 81 may in some embodiments be an internal storage unit of the electronic device 8, such as a removable hard disk of the electronic device 8. The memory 81 may in other embodiments also be an external storage device of the electronic device 8, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the electronic device 8.
The processor 80 may be comprised of integrated circuits in some embodiments, for example, a single packaged integrated circuit, or may be comprised of multiple integrated circuits packaged with the same or different functions, including one or more central processing units (Central Processing unit, CPU), microprocessors, digital processing chips, graphics processors, combinations of various control chips, and the like. The processor 80 is a Control Unit (Control Unit) of the electronic device, connects the respective components of the entire electronic device using various interfaces and lines, executes or executes programs or modules (e.g., programs or the like for generating a correlation random bit stream) stored in the memory 81, and invokes data stored in the memory 81 to perform various functions of the electronic device 8 and process the data.
The bus may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The bus may be classified as an address bus, a data bus, a control bus, etc. The bus is arranged to enable a connection communication between the memory 81 and at least one processor 80 etc.
Fig. 8 shows only an electronic device with components, and it will be understood by those skilled in the art that the structure shown in fig. 8 is not limiting of the electronic device 8 and may include fewer or more components than shown, or may combine certain components, or a different arrangement of components.
For example, although not shown, the electronic device 8 may further include a power source (such as a battery) for powering the various components, and the power source may preferably be logically coupled to the at least one processor 80 via a power management system, such that charge management, discharge management, and power consumption management functions are performed by the power management system. The power supply may also include one or more of any of a direct current or alternating current power supply, a recharging system, a power failure detection circuit, a power converter or inverter, a power status indicator, and the like. The electronic device 8 may further include various sensors, bluetooth modules, wi-Fi modules, etc., which will not be described in detail herein.
Further, the electronic device 8 may also comprise a network interface, optionally comprising a wired interface and/or a wireless interface (e.g. WI-FI interface, bluetooth interface, etc.), typically used for establishing a communication connection between the electronic device 8 and other electronic devices.
The electronic device 8 may optionally further comprise a user interface, which may be a Display, an input unit, such as a Keyboard (Keyboard), or a standard wired interface, a wireless interface. Alternatively, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, or the like. The display may also be referred to as a display screen or display unit, as appropriate, for displaying information processed in the electronic device 8 and for displaying a visual user interface.
It should be understood that the embodiments described are for illustrative purposes only and are not limited to this configuration in the scope of the patent application.
The program 82 stored in the memory 81 of the electronic device 8 for generating a correlation random bit stream is a combination of instructions which, when executed in the processor 80, may implement:
s110, using a device with integrated resistance change and selection characteristics as a random source, and generating a random bit stream under a preset pulse condition by taking the delay time started in the selection characteristics of the device as a random source;
s120, equally dividing the pulse sequence of the random bit stream into N segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, putting the device back into a resistive switching mode by using a reset signal, and setting a bit stream signal generated under the preset pulse condition to be 0;
s130, restarting generation of a random bit stream under the preset pulse condition by adopting a set signal so as to reset the device back to a volatile threshold switch mode;
s140, generating two random bit streams by using the device, and controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, so that 0 bits inserted into the two random bit streams are overlapped to enhance the correlation between the random bit streams.
Specifically, the specific implementation method of the above instructions by the processor 80 may refer to the description of the relevant steps in the corresponding embodiment of fig. 1, which is not repeated herein.
Further, the modules/units integrated by the electronic device 8 may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as a stand alone product. The computer readable medium may include: any entity or system capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM).
Embodiments of the present invention also provide a computer readable storage medium, which may be non-volatile or volatile, storing a computer program which when executed by a processor implements:
s110, using a device with integrated resistance change and selection characteristics as a random source, and generating a random bit stream under a preset pulse condition by taking the delay time started in the selection characteristics of the device as a random source;
s120, equally dividing the pulse sequence of the random bit stream into N segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, using a reset signal to put the device back into a resistive switching mode, and setting a bit stream signal generated under a preset pulse condition to be 0;
s130, restarting generation of a random bit stream under the preset pulse condition by adopting a set signal so as to reset the device back to a volatile threshold switch mode;
s140, generating two random bit streams by using the device, and controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, so that 0 bits inserted into the two random bit streams are overlapped to enhance the correlation between the random bit streams.
In particular, the specific implementation method of the computer program when executed by the processor may refer to descriptions of related steps in the method for generating a correlation random bit stream according to the embodiment, which are not described herein in detail.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus, system and method may be implemented in other manners. For example, the system embodiments described above are merely illustrative, e.g., the division of the modules is merely a logical function division, and other manners of division may be implemented in practice.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units can be realized in a form of hardware or a form of hardware and a form of software functional modules.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned.
Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. Multiple units or systems as set forth in the system claims may also be implemented by means of one unit or system in software or hardware. The terms second, etc. are used to denote a name, but not any particular order.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (10)
1. A method of generating a correlated random bit stream, comprising:
a device with integrated resistance change and selection characteristics is adopted, delay time started in the selection characteristics of the device is used as a random source, and a random bit stream is generated under the preset pulse condition; wherein the probability of "1" in the random bit stream is a reference probability;
dividing the pulse sequence of the random bit stream into N averagely segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, putting the device back into a resistive switching mode by using a reset signal, and setting a bit stream signal generated under the preset pulse condition to be 0;
restarting generation of a random bit stream under the preset pulse condition by adopting a set signal so as to reset the device back to a volatile threshold switch mode;
and generating two random bit streams by using the device, controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, and enabling 0 bits inserted into the two random bit streams to coincide so as to enhance the correlation between the random bit streams.
2. The method of generating a correlated random bit stream of claim 1, wherein the resistance-selection characteristic integrated device is a two-terminal device structure or a three-terminal field effect transistor structure employing a resistance change layer superimposed with a phase change layer.
3. The method of generating a correlated random bit stream of claim 2, wherein the resistive layer is formed using a metal oxide having resistive characteristics and the phase change layer is formed using a phase change material having insulator-metal-transition characteristics.
4. The method of generating a correlated random bit stream of claim 3,
the metal oxide includes HfO 2 And TaO x The phase change material comprises VO x And NbO x 。
5. A method of generating a correlated random bit stream according to any of claims 1 to 4, characterized in that in the selected N slot After the reset-set pulse pair is inserted into the segment pulse sequence, the probability of 1 in the obtained random bit stream is P m ＝P base *(N segment －N slot )/N segment Wherein P is base Is the reference probability.
6. A method of generating a correlated random bit stream according to any of claims 1 to 4, characterized in that generating two random bit streams with the device comprises:
generating two random bit streams using the same device; or,
two random bit streams are generated simultaneously in parallel by two of the devices.
7. The method of generating a correlated random bit stream of claim 6, wherein the predetermined pulse condition is a series of pulse sequences of fixed amplitude and pulse width;
the device is randomly turned on at each pulse, correspondingly generating a 0/1 random bit stream sequence.
8. A system for generating a correlated random bit stream, comprising:
the device comprises an initial random bit stream generation unit, a random bit stream generation unit and a random bit stream generation unit, wherein the initial random bit stream generation unit is used for adopting a device with integrated resistance change and selection characteristics, taking delay time started in the selection characteristics of the device as a random source, and generating a random bit stream under the preset pulse condition; wherein the probability of "1" in the random bit stream is the reference probability P base ；
A pulse sequence processing unit for equally dividing the pulse sequence of the random bit stream into N segment Segments, from which N is arbitrarily selected slot Segment of selected N slot Inserting reset-set pulse pairs into the segment pulse sequence, putting the device back into a resistive switching mode by using a reset signal, and setting a bit stream signal generated under the preset pulse condition to be 0;
a device reset unit for restarting generation of a random bit stream under the preset pulse condition by adopting a set signal so as to reset the device back to a volatile threshold switch mode;
and the pulse regulating and controlling unit is used for generating two random bit streams by utilizing the device, controlling the positions of the reset-set pulse pairs inserted into the two random bit streams to be the same, and enabling 0 bits inserted into the two random bit streams to coincide so as to enhance the correlation between the random bit streams.
9. An electronic device, comprising at least one processor; and a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the steps in the method of generating a dependency random bit stream as claimed in any one of claims 1 to 7.
10. A computer readable storage medium storing at least one instruction, which when executed by a processor in an electronic device implements a method of generating a correlated random bit stream according to any of claims 1 to 7.
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