CN116366055A

CN116366055A - Phase-locked loop and radio frequency communication device

Info

Publication number: CN116366055A
Application number: CN202310297651.0A
Authority: CN
Inventors: 易律凡; 李钰莹
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2023-03-23
Filing date: 2023-03-23
Publication date: 2023-06-30

Abstract

The application provides a phase-locked loop and a radio frequency communication device. The phase-locked loop includes: a voltage controlled oscillator, and first and second loops. The voltage-controlled oscillator generates a first clock signal according to the voltage control signal. The first loop and the second loop together regulate a voltage control signal. The bandwidth of the first loop is smaller than the bandwidth of the second loop, so the second loop locks before the first loop. The frequency division ratio of the second loop is smaller than that of the first loop, so that the reference spurious in the second loop is small, and noise is reduced. The second loop injects the same frequency source with small jitter into the first loop, thereby reducing the noise of the first clock signal. The first loop has good high-frequency noise suppression performance and is a main loop after the phase-locked loop is stable. A local oscillator clock in a radio frequency communication device is generated according to a first clock signal. The radio frequency communication device has lower power consumption.

Description

Phase-locked loop and radio frequency communication device

Technical Field

The embodiment of the application relates to the technical field of electronic circuits, in particular to a phase-locked loop and a radio frequency communication device.

Background

Radio frequency transceivers are widely used in the field of wireless communications. The radio frequency transceiver includes a transmitter for transmitting data and a receiver for receiving data. The receiver receives the radio frequency signal through the antenna, amplifies the received radio frequency signal and frequency-converts the received radio frequency signal with the local oscillation signal. The local oscillation signal is typically generated by a frequency synthesizer. With the development of wireless communication, low noise frequency synthesizers and radio frequency transceivers are desired.

Disclosure of Invention

The application provides a phase-locked loop and a radio frequency communication device.

In a first aspect, a phase locked loop is provided. The phase-locked loop includes: a voltage controlled oscillator for generating a first clock signal; and a first loop and a second loop. Wherein the first loop comprises: a first frequency divider having a first frequency division ratio, the first frequency divider for generating a first feedback signal from the first clock signal; the first phase frequency discriminator is used for generating a first control signal according to the phase difference between a first input signal and the first feedback signal; a first charge pump that generates a first current signal according to the first control signal; and the first filter is connected with the first charge pump and the control end of the voltage-controlled oscillator. The second loop includes: a second divider having a second division ratio, the second division ratio being less than the first division ratio, the second divider for generating a second feedback signal from the first clock signal; the second phase frequency detector is used for generating a second control signal according to the phase difference between a second input signal and the second feedback signal; a second charge pump that generates a second current signal according to the second control signal; and a second filter connected to the second charge pump and the control terminal of the voltage controlled oscillator. Wherein the bandwidth of the first loop is smaller than the bandwidth of the second loop.

In one possible implementation, the first filter has an order that is greater than an order of the second filter.

In one possible implementation, the first loop further includes a third frequency divider, and the second loop further includes a frequency multiplier; the third frequency divider divides the frequency of the reference signal to obtain the first input signal; the frequency multiplier multiplies the reference signal to obtain the second input signal; the reference signal is provided by a crystal oscillator.

In one possible implementation, the voltage controlled oscillator is a differential ring oscillator; the differential ring oscillator comprises an n-level differential amplifier, wherein n is an even number greater than or equal to 4; the non-inverting input end of the (i+1) th differential amplifier is connected with the inverting output end of the i th differential amplifier, the inverting input end of the (i+1) th differential amplifier is connected with the non-inverting output end of the i th differential amplifier, i is more than or equal to 1 and less than or equal to n-1, the non-inverting output end of the n th differential amplifier is connected with the non-inverting input end of the 1 st differential amplifier, and the inverting output end of the n th differential amplifier is connected with the inverting input end of the 1 st differential amplifier; the first clock signal is an output signal of an in-phase output end or an anti-phase output end of a first-stage differential amplifier in the n-stage differential amplifier.

In one possible implementation, the first filter includes: the voltage-controlled oscillator comprises a first node, a second node, a first capacitor, a second capacitor and a first resistor, wherein the first resistor is arranged between the first node and the second node, the first capacitor is arranged between the second node and the ground, the second capacitor is arranged between the first node and the ground, the output end of a first charge pump is connected with the first node, the second filter comprises the first capacitor, the output end of a second charge pump is connected with the second node, and the first node is connected with the control end of the voltage-controlled oscillator.

In one possible implementation, the number of capacitances of the first filter is greater than the number of capacitances of the second filter, which is a subset of the capacitances of the first filter.

In one possible implementation, the bandwidth of the first filter is smaller than the bandwidth of the second filter.

In a second aspect, a phase locked loop is provided. The phase-locked loop includes: a voltage controlled oscillator for generating a first clock signal; and a first loop and a second loop. The first loop includes: a first frequency divider having a first frequency division ratio, the first frequency divider for generating a first feedback signal from the first clock signal; a first phase detector for generating a first control signal according to a phase difference between a first input signal and the first feedback signal; and the first filter is connected with the first phase detector and the control end of the voltage-controlled oscillator. The second loop includes: a second divider having a second division ratio, the second division ratio being less than the first division ratio, the second divider for generating a second feedback signal from the first clock signal; a second phase detector for generating a second control signal according to a phase difference between a second input signal and the second feedback signal; and the second filter is connected with the second phase detector and the control end of the voltage-controlled oscillator. The bandwidth of the first loop is less than the bandwidth of the second loop.

In one possible implementation, the bandwidth of the first filter is smaller than the bandwidth of the second filter; the order of the first filter is larger than the order of the second filter; the number of capacitances of the first filter is greater than the number of capacitances of the second filter, which is a subset of the capacitances of the first filter.

In one possible implementation, the first input signal and the second input signal are generated based on a reference signal, the first input signal being a divided signal of the reference signal, the second input signal being a multiplied signal of the reference signal; the reference signal is provided by a crystal oscillator.

In a second aspect, a radio frequency communication device is provided. The radio frequency communication device includes: a mixer and a phase locked loop of the first or second aspect. Wherein the mixer modulates a radio frequency signal based on a local oscillator signal, the local oscillator signal being generated from the first clock signal obtained from the phase locked loop.

In one possible implementation, the mixer is a down-conversion mixer, and the local oscillator signal includes four clock signals with a duty cycle of 25%, and the phase difference of the clock signals with the duty cycle of 25% is 90 degrees; the local oscillation signal is generated according to a pair of first clock signals with the same frequency and 90-degree phase difference obtained from the phase-locked loop.

In one possible implementation, the radio frequency communication device further includes a low pass filter, a variable gain amplifier, and an analog-to-digital converter, wherein an input terminal of the low pass filter is connected to an output terminal of the mixer, an input terminal of the variable gain amplifier is connected to an output terminal of the low pass filter, and an input terminal of the analog-to-digital converter is connected to an output terminal of the variable gain amplifier. The sampling clock of the analog-to-digital converter is generated according to the first clock signal.

The phase-locked loop of the embodiments of the present application has a dual feedback loop. The first loop includes: the first frequency divider, the first phase-discrimination frequency discriminator, the first charge pump and the first filter, the second loop comprises: the second frequency divider, the second phase-discrimination frequency discriminator, the second charge pump and the second filter. The first filter and the second filter are both connected with the control end of the voltage-controlled oscillator. The bandwidth of the first loop is smaller than that of the second loop, so that the response speed of the second loop is high, and the second loop is locked before the first loop. The frequency division ratio of the second frequency divider is smaller than that of the first frequency divider, so that the multiple of the reference spurious entering the first clock signal of the second loop is small, the reference spurious in the second loop is small, and the accumulation of jitter and noise are reduced. The frequency generated by the first locked second loop is the same, the jitter is small, the signal source with small noise is injected into the first loop, and the first loop is calibrated, so that the first loop generates a high-quality clock signal.

Drawings

Fig. 1 is a schematic circuit diagram of a phase locked loop according to an embodiment of the present application.

Fig. 2 is a schematic circuit diagram of another phase locked loop provided in an embodiment of the present application.

Fig. 3 is a schematic circuit diagram of a first charge pump.

Fig. 4 is a schematic circuit diagram of a second charge pump.

Fig. 5 is a schematic circuit diagram of a first phase frequency detector.

Fig. 6 is a schematic circuit diagram of a voltage controlled oscillator.

Fig. 7 is a schematic circuit diagram of a radio frequency communication device.

Fig. 8 is a schematic circuit diagram of a clock signal processing circuit providing a square wave with a 25% duty cycle.

Fig. 9 is a waveform diagram of a square wave with 25% duty cycle.

Fig. 10 is a schematic circuit diagram of a mixer.

Fig. 11 is a baud diagram of a first loop and a second loop of a phase locked loop.

Fig. 12 is a schematic circuit diagram of the first filter and the second filter.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

In addition, the terms "first," "second," etc. are used merely to distinguish similar objects and should not be construed to indicate or imply relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature.

The present application provides a phase locked loop (Phase Locked Loop, PLL) with dual loops and a radio frequency communication device. The phase-locked loop acts as a frequency synthesizer for the radio frequency communication device and is used for generating a local oscillator signal (local oscillator) of the radio frequency communication device. The voltage controlled oscillator is modulated by the first loop and the second loop. The bandwidth of the first loop is smaller than the bandwidth of the second loop, so the second loop locks before the first loop. The frequency division ratio of the first loop is greater than that of the second loop, so that the reference spurious in the second loop is small, reducing Jitter (Jitter) accumulation and noise. The first locked second loop generates a signal source with the same frequency, small jitter and low noise, and the signal source is injected into the first loop to calibrate the locking process of the first loop, so that the first loop generates a high-quality clock signal. The high-frequency gain of the first loop is fast to decrease, and the high-frequency noise suppression performance of the voltage-controlled oscillator is good, so that the first loop operates as a stable main loop.

Fig. 1 is a circuit schematic diagram of a phase locked loop provided in the present application. The phase-locked loop 100 receives a reference signal, which is a reference clock signal CLK0 with a frequency F0, via an input IN. The reference clock signal CLK0 is provided by a crystal oscillator CO, for example. As shown in fig. 1, the phase-locked loop 100 includes: a first phase detector (101), a first filter (103), a voltage-controlled oscillator (VCO) 110, a first frequency divider (105), a second phase detector (102), a second filter (104), and a second frequency divider (106). In a scenario where the frequency variation is not large, a phase detector may be employed to save costs. The phase detector outputs the signals with different frequencies, so that errors are easy to occur, and the phase detector can work under the scene of different signal frequencies. The phase discriminator refers to a device capable of discriminating the phase difference of input signals, and is a circuit for enabling the output voltage to have a definite relation with the phase difference between two input signals, wherein the average voltage output by the phase discriminator in a period is in direct proportion to the phase difference, namely, the time of multiplying the voltage value by a high level is in direct proportion to the phase difference, the phase discriminator can trigger work by utilizing the jump edge of the input signals, the phase discriminator detects pulses, and the pulse difference can be converted by the current of the charge pump, so that the output charge is in direct proportion to the phase difference.

The voltage-controlled oscillator 110 generates the first clock signal CLK1 according to the voltage control signal Vctrl. The first clock signal CLK1 has a frequency F1. The frequency F1 of the first clock signal CLK1 is determined by the magnitude of the voltage control signal Vctrl.

As shown in fig. 1, the phase-locked loop 100 includes a first loop and a second loop, and the voltage-controlled oscillator 110 is adjusted according to feedback of the first loop and the second loop. The bandwidth (loop bandwidth) of the first loop is smaller than the bandwidth of the second loop. The first loop may include: a first frequency divider 105, a first phase detector 101 and a first filter 103. In fig. 1, the first loop may be formed of a first frequency divider 105, a first phase detector 101, and a first filter 103. The second loop may include: a second frequency divider 106, a second phase detector 102, and a second filter 104. In fig. 1, the second loop may be formed by a second frequency divider 106, a second phase detector 102, and a second filter 104. The first loop and the second loop together control the voltage controlled oscillator 110.

The frequency division ratio of the first frequency divider 105 is N. The first frequency divider 105 is configured to generate a clock signal CLK11 according to a first clock signal CLK1 output from the voltage-controlled oscillator 110. The frequency of the clock signal CLK11 is F1/N. N is a positive integer. The clock signal CLK11 is referred to herein as a first feedback signal.

The frequency division ratio of the second frequency divider 106 is M. The second frequency divider 106 is configured to generate the clock signal CLK12 according to the first clock signal CLK1 output by the voltage-controlled oscillator 110. The frequency of the clock signal CLK12 is F1/M. M is a positive integer, and M is less than N. The clock signal CLK12 is referred to herein as a second feedback signal.

The phase locked loop 100 further comprises a third frequency divider 107 and a frequency multiplier 108.

The frequency division ratio of the third frequency divider 107 is B. The third frequency divider 107 is configured to generate a clock signal CLK01 according to the reference clock signal CLK 0. The clock signal CLK01 has a frequency F0/B. B is a positive integer. The clock signal CLK01 is referred to herein as a first input signal. In the present embodiment, the first frequency divider 105, the second frequency divider 106, and the third frequency divider 107 may be implemented by D flip-flops or counters.

The frequency multiplier 108 has a frequency multiplication ratio R. The frequency multiplier 108 is configured to generate the clock signal CLK02 according to the reference clock signal CLK 0. The frequency of the clock signal CLK02 is f0×r. R is a positive integer. The clock signal CLK02 is referred to herein as the second input signal. In this embodiment, the frequency multiplier 108 may be implemented using a multiplier. That is, the first input signal and the second input signal are generated based on the reference signal.

The first phase detector 101 receives the clock signal CLK01 and the clock signal CLK11, and generates a first control signal according to a phase difference between the clock signal CLK01 and the clock signal CLK 11. The first control signal indicates a phase difference of the clock signal CLK01 and the clock signal CLK 11. The first control signal is a voltage signal. The first filter 103 is connected to the output of the first phase detector 101 and to the control terminal of the voltage controlled oscillator 110. The first filter 103 converts the first control signal into a voltage signal. For example, when the first control signal is at a high level, it indicates that the clock signal CLK01 and the clock signal CLK11 have a phase difference, the output voltage of the first filter 103 increases, and the voltage control signal Vctrl increases.

The second phase detector 102 receives the clock signal CLK02 and the clock signal CLK12, and generates a second control signal according to a phase difference between the clock signal CLK02 and the clock signal CLK 12. The second control signal indicates a phase difference of the clock signal CLK02 and the clock signal CLK 12. The second control signal is a voltage signal. The second filter 104 is connected to the output of the second phase detector 102 and to the control terminal of the voltage controlled oscillator 110. The second filter 104 converts the second control signal into a voltage signal. For example, when the second control signal is at a high level, the output voltage of the second filter 104 increases, and the voltage control signal Vctrl increases, indicating that the clock signal CLK02 and the clock signal CLK12 have a phase difference. The first phase detector 101 and the second phase detector 102 are for example exclusive or gates.

In the present embodiment, the first filter 103 and the second filter 104 are loop filters (loop filters), for example, low-pass loop filters, capable of suppressing high-frequency noise in the first control signal and the second control signal. The order of the first filter 103 is larger than the order of the second filter 104, so that the filtering order of the first control signal by the first filter 103 is larger than the filtering order of the first control signal by the second filter 104. For example, the first filter 103 is a second order low pass filter, and the second filter 104 is a first order low pass filter. Since the order of the first filter 103 is larger than that of the second filter 104, the high-frequency gain of the first filter 103 drops faster and the high-frequency noise suppression performance of the voltage-controlled oscillator 110 is better. The second filter 104 of the second loop may be a low order filter, which saves costs. In some embodiments, the second filter 104 is part of the first filter 103, i.e. a part of the first filter 103 is multiplexed as the second filter 104, the first control signal and the second control signal being input to different nodes of the first filter 103. For example, the first filter 103 and the second filter 104 are RC filters, the number of capacitances of the first filter 103 is larger than the number of capacitances of the second filter 104, and the capacitances of the second filter 104 are a subset of the capacitances of the first filter 103. The capacitance of the first filter 103 is multiplexed by the second filter 104, which can save cost and reduce chip area.

In some embodiments, the bandwidth of the first filter 103 is less than the bandwidth of the second filter 104, thereby helping to achieve that the bandwidth of the first loop is less than the bandwidth of the second loop.

The voltage controlled oscillator 110 is, for example, a differential ring oscillator. Compared with an LC oscillator, the differential ring oscillator does not need inductance and capacitance, and can save power consumption and area. The differential ring oscillator includes an n-stage differential amplifier, n being an even number of 4 or more. The non-inverting input end (non-inverting input) of the (i+1) th level differential amplifier is connected with the inverting output end (inverting input) of the (i+1) th level differential amplifier, the non-inverting input end (non-inverting input) of the (i+1) th level differential amplifier is connected with the non-inverting output end (non-inverting input) of the (i+1) th level differential amplifier, the non-inverting output end (non-inverting input) of the (i+1) th level differential amplifier is connected with the non-inverting input end (non-inverting input) of the (non-inverting input) 1 st level differential amplifier, the non-inverting input end (non-inverting input) of the (non-inverting input) th level differential amplifier is connected with the non-inverting input end (non-inverting input) of the (non-inverting input) 1). The output signal of the in-phase output terminal or the anti-phase output terminal of one of the n-stage differential amplifiers may be the first clock signal CLK1. The differential ring oscillator is, for example, the differential ring oscillator shown in fig. 6.

The output of the first filter 103 and the output of the second filter 104 are both connected to the control terminal of the voltage controlled oscillator 110. The output voltage of the first filter 103 and the output voltage of the second filter 104 are superimposed as a voltage control signal Vctrl. That is, the output voltage of the first filter 103 and the output voltage of the second filter 104 commonly control the voltage-controlled oscillator 110. When one of the first control signal and the second control signal is at a high level, the voltage control signal Vctrl increases, and the voltage-controlled oscillator 110 adjusts the frequency F1 and/or the phase of the first clock signal CLK1 such that the phase of the clock signal CLK11 gradually approaches the phase of the clock signal CLK01, and the phase of the clock signal CLK12 continuously approaches the phase of the clock signal CLK 02. This process may be referred to as a phase lock process.

After the phase-locked loop 100 is stably operated, the frequency F1 of the first clock signal CLK1 satisfies: f1×b/n=f0=f1/(r×m). Thus, m=n/(r×b). M is less than N.

In some embodiments, the third frequency divider 107 may not be provided. In this case, the first phase detector 101 receives the reference clock signal CLK0 and the clock signal CLK11, and generates the first control signal. The first control signal indicates a phase difference of the reference clock signal CLK0 and the clock signal CLK 11. The first control signal being high indicates that there is a phase difference between the reference clock signal CLK0 and the clock signal CLK 11. After the phase-locked loop 100 is stably operated, the frequency F1 of the first clock signal CLK1 satisfies: f1/n=f0=f1/r×m. Thus, m=n/R.

The phase locked loop of the present application has two feedback loops. The bandwidth of the first loop is smaller than the bandwidth of the second loop, which stabilizes prior to the first loop. Since the frequency division ratio M of the second frequency divider 106 is smaller than the frequency division ratio N of the first frequency divider 105, the reference spurs of the second loop are smaller than the reference spurs of the first loop by a small multiple of the first clock signal. The second loop, which is first locked, injects a co-frequency source with small in-band spurious into the first loop, thereby continuously correcting the first clock signal CLK1 output by the vco 110, reducing jitter accumulation, and finally the vco 110 outputs a low-noise first clock signal CLK1.

Fig. 2 is a schematic circuit diagram of another phase locked loop according to an embodiment of the present application. The phase-locked loop 100 receives a reference signal with frequency F0 via the input IN, the reference signal being a reference clock signal CLK0. The reference clock signal CLK0 is provided by a crystal oscillator, for example. As shown in fig. 2, the phase-locked loop 100 includes: a first phase-frequency detector (Phase Frequency Detector) 1011, a first Charge Pump (1013), a voltage-controlled oscillator 110, a first frequency divider 105, a second phase-frequency detector 1021, a second Charge Pump 1014, a second frequency divider 106, a first filter 103, a second filter 104, a third frequency divider 107, and a frequency multiplier 108. The voltage controlled oscillator has a control terminal. The voltage-controlled oscillator generates a first clock signal CLK1 according to a voltage control signal Vctrl at the control terminal. The first clock signal CLK1 has a frequency F1. The frequency F1 of the first clock signal CLK1 is determined by the voltage control signal Vctrl. The phase-locked loop 100 comprises a first loop and a second loop, which together regulate the voltage control signal Vctrl at the control terminal of the voltage controlled oscillator 110. The bandwidth of the first loop is smaller than the bandwidth of the second loop.

In fig. 2, the first loop includes: a first frequency divider 105, a first phase detector 101, a first charge pump 1013, and a first filter 103. The second loop includes: a second frequency divider 106, a second phase detector 102, a second charge pump 1014, and a second filter 104. A part of the first filter 103 is multiplexed as the second filter 104.

As shown in fig. 2, the phase-locked loop 100 includes a first loop and a second loop, and the voltage-controlled oscillator 110 is adjusted according to feedback of the first loop and the second loop. The bandwidth of the first loop is smaller than the bandwidth of the second loop. The first loop includes: a first frequency divider 105, a first phase frequency detector 1011, a first charge pump 1013, a filter 103 and a third frequency divider 107. In fig. 2, the first loop may be formed by the first frequency divider 105, the first phase frequency detector 1011, the first charge pump 1013, the filter 103, and the third frequency divider 107. The second loop comprises a second frequency divider 106, a second phase frequency detector 1021, a second charge pump 1014, a filter 103 and a frequency multiplier 108. In fig. 2, the second loop may be formed by the second frequency divider 106, the second phase frequency detector 1021, the second charge pump 1014, a portion of the filter 103, and the frequency multiplier 108. The first loop and the second loop share the filter 103 and the voltage controlled oscillator 110.

If the first loop and the second loop in fig. 2 include the respective first filter and second filter, i.e. the second filter may not multiplex the first filter, the first loop includes: a first frequency divider 105, a first phase detector 101, a first charge pump 1013, a first filter 103. The second loop includes: a second frequency divider 106, a second phase detector 102, a second charge pump 1014, and a second filter 104. The bandwidth of the first loop is smaller than the bandwidth of the second loop.

The frequency division ratio of the first frequency divider 105 is N. The first frequency divider 105 is configured to generate a clock signal CLK11 according to a first clock signal CLK1 output from the voltage-controlled oscillator 110. The frequency of the clock signal CLK11 is F1/N. N is a positive integer.

The frequency division ratio of the second frequency divider 106 is M. The second frequency divider 106 is configured to generate the clock signal CLK12 according to the first clock signal CLK1 output by the voltage-controlled oscillator 110. The frequency of the clock signal CLK12 is F1/M. M is a positive integer, and M is less than N.

The frequency division ratio of the third frequency divider 107 is B. The first loop further comprises a third frequency divider 107. The third frequency divider 107 is configured to generate a clock signal CLK01 according to the reference clock signal CLK 0. The clock signal CLK01 has a frequency F0/B. B is a positive integer.

The frequency multiplier 108 has a frequency multiplication ratio R. The second loop also includes a frequency multiplier. The frequency multiplier 108 is configured to generate the clock signal CLK02 according to the reference clock signal CLK 0. The frequency of the clock signal CLK02 is f0×r. R is a positive integer.

The first phase frequency detector 1011 receives the clock signal CLK01 and the clock signal CLK11, and generates a first control signal according to a phase difference between the clock signal CLK01 and the clock signal CLK11. The second phase frequency detector 1021 receives the clock signal CLK02 and the clock signal CLK12, and generates a second control signal according to a phase difference between the clock signal CLK02 and the clock signal CLK12.

The first charge pump 1013 generates a first current signal according to a first control signal. The second charge pump 1014 generates a second current signal in accordance with a second control signal. The first control signal and the second control signal each comprise two signals. The output of the first charge pump 1013 is connected to the first node N1 of the first filter 103. The output of the second charge pump 1014 is coupled to a second node N2 of the second filter 104.

Fig. 3 is a schematic circuit diagram of the first charge pump 1013. Fig. 4 is a schematic circuit diagram of a second charge pump 1014. Fig. 5 is a schematic circuit diagram of the first phase-frequency detector 1011 or the second phase-frequency detector 1021.

The first phase-frequency detector 1011 and the second phase-frequency detector 1021 have similar circuit structures. The first phase detector 1011 is described below as an example. As shown in fig. 5, the first phase frequency detector 1011 includes a D flip-flop 801, a D flip-flop 802, and an and gate 803. The clock input of the D flip-flop 801 receives the clock signal CLK01 and the clock input of the D flip-flop 802 receives the clock signal CLK11. The data inputs D of the D flip-flop 801 and the D flip-flop 802 are both connected to the power supply voltage VDD. The data output terminal Q of the D flip-flop 801 outputs the control signal UP1, and the data output terminal Q of the D flip-flop 802 outputs the control signal DOWN1. The first control signal includes a control signal UP1 and a control signal DOWN1. Upon detecting a rising edge of the clock signal CLK01, the control signal UP1 becomes a high level; upon detecting the rising edge of the clock signal CLK11, the control signal DOWN1 becomes a high level. The 2 inputs of the and gate 803 receive the control signal UP1 and the control signal DOWN1, respectively, and the output outputs reset signals to the D flip-flop 801 and the D flip-flop 802. In some embodiments, a delay module is also provided between the output of AND gate 803 and D flip-

flops

801 and 802. That is, after the control signals UP1 and DOWN1 both go high, and gate 803 generates a reset signal to reset D flip-flop 801 and D flip-flop 802, in preparation for detecting the next clock edge of the clock signal, delayed for a period of time.

As shown in fig. 3, the first charge pump 1013 includes a current source 10131, a switch K1, an output terminal, a switch K2, and a current source 10132. The current source 10131, the switch K1, the output terminal, the switch K2, and the current source 10132 are connected in series between the power supply terminal and ground. The output is connected to a first node N1 in the first filter 103. The current source 10131 provides a current to the output, i.e., a charging current. The current source 10132 provides a current from the output terminal to ground, i.e., a discharge current. The control terminal of the switch K1 receives the control signal UP1, and the control terminal of the switch K2 receives the control signal DOWN1. When the control signal UP1 is at a high level, the switch K1 is turned on. When the control signal DOWN1 is at a high level, the switch K2 is turned on. The currents of the current source 10131 and the current source 10132 are equal in magnitude. When the control signals UP1 and DOWN1 are both high, the output terminal does not supply current to the outside. Accordingly, the first charge pump 1013 supplies the first current signal to the first node N1 according to the control signal UP1 and the control signal DOWN1.

Similarly, the second control signal includes a control signal UP2 and a control signal DOWN2. On the rising edge of the clock signal CLK02, the control signal UP2 becomes high level; on the rising edge of the clock signal CLK12, the control signal DOWN2 goes high.

A schematic circuit of the second charge pump 1014 is shown in fig. 4. The second charge pump 1014 includes a current source 10141, a switch K3, an output, a switch K4, and a current source 10142. The current source 10141, the switch K3, the output terminal, the switch K4, and the current source 10142 are connected in series between the power supply terminal and ground. The output is connected to a second node N2 in the second filter 104. The current source 10141 provides a current to the output, i.e., a charging current. The current source 10142 provides a current from the output terminal to ground, i.e., a discharge current. The control terminal of the switch K3 receives the control signal UP2, and the control terminal of the switch K4 receives the control signal DOWN2. When the control signal UP2 is at a high level, the switch K3 is turned on. When the control signal DOWN2 is at a high level, the switch K4 is turned on. The currents of the current source 10141 and the current source 10142 are equal in magnitude. When both control signals UP2 and DOWN2 are high, the output terminal does not supply current to the outside. Accordingly, the first charge pump 1014 supplies a second current signal to the second node N2 according to the control signal UP2 and the control signal DOWN2.

The first filter 103 and the second filter 104 are, for example, RC loop filters. In the present embodiment, a part of the first filter 103 is multiplexed as the second filter 104, and the first current signal and the second current signal are input to different nodes (the first node N1 and the second node N2) of the first filter 103. As shown in fig. 2, the first filter 103 includes: the first node N1, the second node N2, the first resistor R1, the first capacitor C1 and the second capacitor C2. The first resistor R1 is disposed between the first node N1 and the second node N2. The first capacitor C1 is disposed between the second node N2 and ground. The second capacitor C2 is disposed between the first node N1 and ground. The capacitance value of the first capacitor C1 is larger than the capacitance value of the second capacitor C2. For the first current signal input to the first node N1, the first resistor R1, the first capacitor C1, and the second capacitor C2 constitute a 2-order low-pass filter. That is, the first filter in the first loop is a 2-order low-pass filter. The second filter 104 includes a first capacitor C1. For the second current signal input to the second node N2, the first capacitor C1 constitutes a 1 st order low pass filter 1032. That is, the second filter in the second loop is a 1 st order low pass filter, and the first capacitor C1 is multiplexed. Therefore, the filtering order of the first current signal by the first filter 103 is larger than the filtering order of the second current signal by the second filter 104. The first filter 103 and the second filter 104 generate the voltage control signal Vctrl from the first current signal and the second current signal. In other embodiments, the first filter 103 is a 3-order filter, the first filter 103 performs 3-order filtering on the first current signal, and a portion of the first filter 103 is multiplexed as the second filter 104 to perform 1-order filtering or 2-order filtering on the second current signal by coupling the second current signal to an appropriate node in the first filter 103. In the embodiment of fig. 2, the first filter 103 and the second filter 104 are passive filters, and in other embodiments, the first filter 103 and the second filter 104 are active filters, which is not limited in this application.

In some embodiments, the bandwidth of the first filter 103 is less than the bandwidth of the second filter 104, thereby achieving that the bandwidth of the first loop is less than the bandwidth of the second loop.

Referring to fig. 2-5, the first filter 103 and the second filter 104 generate the voltage control signal Vctrl from the first current signal and the second current signal in the following manner. When the phase of the clock signal CLK01 leads the phase of the clock signal CLK11, the control signals UP1 and DOWN1 control the current source 10131 to charge the first capacitor C1 and the second capacitor C2, the first current signal is a charging current, the voltage control signal Vctrl becomes high, and the frequency F1 of the first clock signal CLK1 increases; when the phase of the clock signal CLK01 lags behind the phase of the clock signal CLK11, the first capacitor C1 and the second capacitor C2 are discharged through the current source 10132 under the control of the control signals UP1 and DOWN1, the first current signal is a discharge current (or referred to as a pumping current), the voltage control signal Vctrl becomes low, and the frequency F1 of the first clock signal CLK1 decreases. When the phase of the clock signal CLK02 leads the phase of the clock signal CLK12, the control signals UP2 and DOWN2 control the current source 10141 to charge the first capacitor C1 and the second capacitor C2, the second current signal is a charging current, the voltage control signal Vctrl becomes high, and the frequency F1 of the first clock signal CLK1 increases; when the phase of the clock signal CLK02 lags behind the phase of the clock signal CLK12, the first capacitor C1 and the second capacitor C2 are discharged through the current source 10142 under the control of the control signals UP2 and DOWN2, the second current signal is a discharge current, the voltage control signal Vctrl becomes low, and the frequency F1 of the first clock signal CLK1 decreases.

In the embodiment of fig. 2, the capacitance of the first filter is multiplexed as the capacitance of the second filter. In other embodiments, the second filter 104 is a separate filter. The first loop includes: a first frequency divider 105, a first phase frequency detector 1011, a first charge pump 1013, and a first filter 103. The second loop includes: a second frequency divider 106, a second phase frequency detector 1012, a second charge pump 1014, and a second filter 104. The bandwidth of the first loop is smaller than the bandwidth of the second loop. Fig. 12 is a schematic circuit diagram of the first filter and the second filter. As shown in fig. 12, the first filter 103 is a 2-order filter, and the second filter 104 is a 1-order filter. The first filter 103 includes a first resistor R1, and a first capacitor C1 and a second capacitor C2. The second filter 104 comprises a third capacitance C3. The capacitance value of the third capacitor C3 may be equal to the capacitance value of the first capacitor C1, and the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2. The first filter 103 generates a first voltage control signal Vctrl1 according to the first current signal, and the second filter 104 generates a second voltage control signal Vctrl2 according to the second current signal. The output of the first filter 103 and the output of the second filter 104 are both connected to the control terminal of the voltage controlled oscillator 110. When one of the first voltage control signal Vctrl1 and the second voltage control signal Vctrl2 increases, the voltage control signal Vctrl increases.

The voltage controlled oscillator 110 is, for example, a differential ring oscillator. Fig. 6 is a schematic circuit diagram of the differential ring oscillator 110. As shown in fig. 6, the differential ring oscillator 110 includes 4-stage differential amplifiers 1101-1104. The differential amplifiers 1101-1104 form an oscillation loop. The non-inverting input end of the next-stage differential amplifier is connected with the inverting output end of the previous-stage differential amplifier, and the inverting input end of the next-stage differential amplifier is connected with the non-inverting output end of the previous-stage differential amplifier. The in-phase output end of the last-stage differential amplifier is connected with the in-phase input end of the first-stage differential amplifier, and the anti-phase output end of the last-stage differential amplifier is connected with the anti-phase input end of the first-stage differential amplifier. The frequency of the oscillation loop formed by the differential amplifiers 1101-1104 is determined by the bias current of the differential amplifiers 1101-1104. The voltage controlled oscillator 110 further includes a voltage to current conversion circuit 111. The voltage-current conversion circuit 111 converts the voltage control signal Vctrl into a bias current Ictrl.

Referring to fig. 6, the non-inverting output terminal and the inverting output terminal of each differential amplifier output a pair of clock signals having opposite phases. The non-inverting outputs of the differential amplifiers 1101-1104 output a clock signal CLKD, a clock signal CLKA, a clock signal CLKB, and a clock signal CLKC, respectively. The clock signals CLKA-CLKD have the same frequency. The first clock signal CLK1 provided to the first divider 105 and the second divider 106 may be any one of the clock signals CLKA-CLKD.

As shown in fig. 6, the voltage-current conversion circuit 111 includes a second resistor R2 and transistors M1 to M3. The transistor M2, the transistor M1 and the second resistor R2 are connected in series between the power supply terminal and ground. The gate of the transistor M1 is used as a control terminal of the voltage-controlled oscillator 110 and receives the voltage control signal Vctrl. Transistors M2 and M3 constitute a current mirror. The current IM1 flowing through the transistor M1 is copied to the transistor M3. The current flowing through the transistor M3 is the bias current Ictrl. In some embodiments, transistor M1 is an NMOS transistor and transistors M2-M3 are PMOS transistors. When the voltage control signal Vctrl becomes high, the current IM1 of the transistor M1 increases, and the bias current Ictrl increases; when the voltage control signal Vctrl goes low, the current IM1 of the transistor M1 decreases and the bias current Ictrl decreases.

The transfer function H1(s) of the system of the first loop and the voltage controlled oscillator may be expressed as:

wherein K is _d1 Is the transfer function gain of the first phase-frequency discriminator 1011 and the first charge pump 1013, kvco is the voltage-controlled oscillatorThe gain of the oscillator 110, F1(s), is the transfer function of the filter in the first loop, N is the division ratio of the first divider 105, and B is the division ratio of the third divider 107.

For the phase locked loop shown in fig. 2, the filter in the first loop is a second order filter, and the transfer function of the second order filter can be expressed as:

The transfer function H2(s) of the system of the second loop and the voltage controlled oscillator can be expressed as equation 2:

wherein K is _d2 Is the transfer function gain of the second phase frequency detector 1021 and the second charge pump 1014, kvco is the gain of the voltage controlled oscillator 110, F2(s) is the transfer function of the filter in the second loop, M is the division ratio of the second frequency divider 106, and R is the multiplication ratio of the frequency multiplier 108.

For the phase-locked loop shown in fig. 2, the filter in the second loop is a first order filter, and when the capacitance value of the first capacitor C1 is far greater than that of the second capacitor C2, the transfer function of the first order filter can be expressed as:

fig. 11 is a baud diagram of a phase locked loop. In fig. 11, ω or frequency is on the horizontal axis, gain is on the vertical axis, ω=2pi f, and frequency is f. Wherein ω0 is the zero point of the system formed by the first loop and the voltage-controlled oscillator, ω1 is the pole of the system formed by the first loop and the voltage-controlled oscillator, and ω2 is the pole of the system formed by the second loop and the voltage-controlled oscillator. The system bandwidth of the first loop and the voltage controlled oscillator is omega value when the transfer function H1(s) is 0dB, and the system bandwidth of the second loop and the voltage controlled oscillator is omega value when the transfer function H2(s) is 0 dB.

As shown in fig. 11, the bandwidth of the second loop is larger than that of the first loop, so that the response speed of the second loop is fast, and the second loop is locked before the first loop. Since the frequency division ratio in the second loop is smaller than the frequency division ratio in the first loop, the spurious frequency reference entering the first clock signal CLK1 from the second loop is small. The voltage controlled oscillator 110 is controlled by a superposition of the first loop and the second loop. During the phase-locked loop operation, the second loop is equivalent to injecting a frequency source with small reference spurious in the first loop, and the frequency of the frequency source is equal to the target frequency of the clock signal CLK1, so as to continuously correct the frequency of the clock signal CLK1 generated by the voltage-controlled oscillator 110, thereby realizing the calibration of the phase locking process and reducing the accumulation of jitter (jitter) of the clock signal CLK 1. The filter of the first loop is a 2-order low-pass filter, the filter of the second loop is a 1-order low-pass filter, the high-frequency gain of the filter of the first loop is reduced faster than that of the filter of the second loop, and the first loop has good high-frequency noise suppression performance on the voltage-controlled oscillator 110, so that the first loop operates as a main loop after being stabilized. Thus, the phase locked loop of the present application reduces the accumulation of jitter and is low in noise compared to a single loop phase locked loop (i.e., a phase locked loop comprising only the first loop).

The application also provides a radio frequency communication device. The radio frequency communication device is for example a radio frequency receiver, which is for example based on an intermediate frequency receiver architecture. The phase-locked loop 100 is used as a local oscillation generating circuit of a radio frequency communication device.

Fig. 7 is a schematic circuit diagram of a radio frequency communication device. As shown in fig. 7, the radio frequency communication device includes: antenna 130, matching network 220, low noise amplifier 230, mixer 240, filter 250, variable gain amplifier 260, analog to digital converter 270, digital baseband circuit 280, phase locked loop 100, and clock signal processing circuit 210.

The antenna 130 receives a radio frequency signal RF. The radio frequency signal RF is impedance matched by means of the matching network 220. The low noise amplifier 230 performs noise reduction and amplification on the radio frequency signal RF. The amplified radio frequency signal RF enters the mixer 240.

The phase locked loop 100 may use the phase locked loop shown in fig. 1 or fig. 2. The clock signal processing circuit 210 generates a local oscillation signal LO according to a first clock signal provided by the phase-locked loop 100. The mixer 240 modulates the radio frequency signal RF with the local oscillation signal LO, generating an intermediate frequency signal IF. The local oscillation signal LO has a frequency F2, the radio frequency signal RF has a frequency F3, and the intermediate frequency signal IF modulated by the mixer 240 has a frequency (f2+f3) or (F3-F2). The filter 250 is, for example, a low-pass filter. The part of the intermediate frequency signal IF with the frequency (f2+f3) is filtered out and the part with the frequency (F3-F2) is reserved, so that a down-converted signal IF1 is obtained. Thus, the mixer 240 and the low pass filter 240 implement a down-conversion.

The down-converted signal IF1 is amplified by the variable gain amplifier 260 to obtain a signal with a larger swing. The analog-to-digital converter 270 converts the signal from an analog signal to a digital signal, which is input to the digital baseband circuit 280.

The matching network 220, the low noise amplifier 230, the filter 250, the variable gain amplifier 260, and the analog-to-digital converter 270 may be selected to have a suitable circuit structure according to practical requirements.

The intermediate frequency signal IF comprises, for example, quadrature I-signals and Q-signals. The I signal and the Q signal are both differential signals. The I signal and the Q signal are respectively sent to an I channel and a Q channel for processing. The I and Q channels each include the filter 250, variable gain amplifier 260, and analog-to-digital converter 270 described above. The local oscillator signal LO comprises four square wave signals with a duty cycle of 25% for modulating the radio frequency signal RF to generate an I signal and a Q signal in differential form, respectively.

As shown in fig. 7, the local oscillation signal LO is generated based on a pair of clock signals having the same frequency and a phase difference of 90 degrees obtained from the phase locked loop 100. For example, the pair of clock signals are obtained from

differential amplifiers

1102 and 1104 of voltage controlled oscillator 110. Specifically, the clock signal CLKA is obtained from the differential amplifier 1102 and the clock signal CLKC is obtained from the differential amplifier 1104. The phase difference of the clock signal CLKA and the clock signal CLKC is 90 degrees. As another example, the pair of clock signals are clock signals CLKD and clkb# obtained from

differential amplifiers

1101 and 1103 of the voltage controlled oscillator 110. The clock signal clkb# is a clock signal output from the inverting output terminal of the differential amplifier 1103, and is opposite in phase to the clock signal CLKB.

The clock signal processing circuit 210 generates four square wave signals with a duty ratio of 25% based on the pair of clock signals with the same frequency and a phase difference of 90 degrees. Fig. 8 is a circuit diagram of the clock signal processing circuit 210. As shown in fig. 8, the clock signal processing circuit 210 includes:

inverters

211 and 212, and AND gates 213-216. Inverter 211 receives clock signal CLKA and generates clock signal clka# having an opposite phase. Inverter 212 receives clock signal CLKC and generates clock signal clkc# having an opposite phase. The and gate 213 receives the clock signal CLKA and the clock signal clkc#, and generates the clock signal CLK21. The and gate 214 receives the clock signal CLKA and the clock signal CLKC, and generates the clock signal CLK22. The and gate 215 receives the clock signal clka# and the clock signal clkc# and generates the clock signal CLK23. The AND gate 216 receives the clock signal CLKA# and the clock signal CLKC, and generates the clock signal CLK24. The local oscillator signal LO includes clock signals CLK21-CLK24. The mixer 240 modulates the radio frequency signal RF based on the local oscillation signal LO. Therefore, the local oscillator signal LO is generated according to the first clock signal CLK1, and the frequency F2 of the local oscillator signal LO is equal to the frequency F1 of the first clock signal CLK 1.

In some embodiments, the clock signal processing circuit 210 also includes a deburring (gate) module and/or a non-overlapping clock control module to enhance circuit performance while achieving the desired logic. The deburring module is used for deburring the clock signals CLK21-CLK24. The non-overlapping clock control module is used to ensure that the high-level times of the clock signals CLK21-CLK24 do not overlap.

Fig. 9 shows waveforms of clock signals CLKA, clkb#, CLKC, and CLKD, and waveforms of clock signals CLK21-CLK 24. The duty cycle of the clock signals CLKA, clkb#, CLKC, and CLKD is 50% as shown in fig. 9. For example, the duty cycle of the clock signals CLKA, clkb#, CLKC, and CLKD may be 50% by the shaper circuit. The frequency of the clock signals CLK21-CLK24 is the same as the frequency of the clock signals CLKA-CLKD. That is, the frequency F2 of the clock signals CLK21-CLK24 is equal to the frequency F1 of the first clock signal CLK 1. The clock signals CLK21-CLK24 are sequentially 90 degrees out of phase. For example, the phases of the clock signals CLK21-CLK24 are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively.

The mixer 240 includes 4 mixing units. Each mixing unit receives the radio frequency signal RF output by the low noise amplifier 230 and one of the clock signals CLK21-CLK 24. The mixing unit is used for modulating the radio frequency signal RF signal. The differential I signal includes signals Ip and In, which are In opposite phases. The differential Q signal includes signals Qp and Qn, which are in opposite phases. Four mixing units are used to generate the signals Ip and In, and Qp and Qn, respectively.

Fig. 10 is a schematic circuit diagram of the mixer 240. The mixer 240 shown in fig. 10 is a passive mixer, saving power consumption. As shown in fig. 10, the mixer 240 includes mixing units 241 to 244. The mixing unit 241 includes a capacitor 2401 and a transistor M11. The mixing unit 242 includes a capacitor 2402 and a transistor M12. The mixing unit 243 includes a capacitor 2403 and a transistor M13. Mixing unit 244 includes a capacitor 2404 and a transistor M14. The capacitor 2401, the capacitor 2402, the capacitor 2403, and the capacitor 2404 are used to filter the clock signals CLK21-CLK24, respectively. The mixing unit 241 generates a signal Ip according to the clock signal CLK21 and the radio frequency signal RF. The mixing unit 242 generates a signal Qp according to the clock signal CLK22 and the radio frequency signal RF. The mixing unit 243 generates a signal In according to the clock signal CLK23 and the radio frequency signal RF. The mixing unit 244 generates a signal Qn according to the clock signal CLK24 and the radio frequency signal RF.

Taking the mixing unit 241 generating the signal Ip as an example, one end of the capacitor 2401 receives the clock signal CLK21, and the other end is connected to the gate of the transistor M11. The gate of transistor M11 also receives a dc bias voltage VB. The source of the transistor M11 receives a radio frequency signal RF. The drain of the transistor M11 outputs a signal Ip. The transistor M11 is, for example, a PMOS transistor. The transistor M11 is turned on and off under the control of the clock signal CLK 21. Since the phases of the clock signal CLK21 and the clock signal CLK23 differ by 180 degrees, the signal Ip generated by the mixing unit 241 and the signal In generated by the mixing unit 243 differ by 180 degrees. Because the phases of the clock signal CLK22 and the clock signal CLK24 are 180 degrees different, the signal Qp generated by the mixing unit 242 and the signal Qn generated by the mixing unit 244 are 180 degrees different.

As shown in fig. 7, the sampling clock of the analog-to-digital converter 270 is the third clock signal CLK3. The third clock signal CLK3 is generated according to the first clock signal CLK 1. For example, the third clock signal CLK3 is the clock signal CLK12 output by the second divider 106 and the frequency of the third clock signal CLK3 is F1/M. Obtaining the sampling clock signal of analog-to-digital converter 270 from second divider 106 of phase-locked loop 100 reduces the need for additional dividers and clock generators.

In the radio frequency communication device provided by the present application, the frequency of the oscillation signal (the first clock signal CLK 1) output by the phase-locked loop 100 is set to the frequency of the local oscillation signal LO required by the radio frequency communication device. The voltage-controlled oscillator in the phase-locked loop 100 is a differential ring oscillator, which can provide a pair of clock signals with the same frequency and 90 degrees phase difference, and the pair of clock signals are converted into local oscillation signals LO (i.e., clock signals CLK21-CLK 24) required by the mixer 240 through the clock signal processing circuit 210, so that the circuit arrangement is simplified.

The radio frequency communication device provided by the application has the advantages that the influence of I/Q imbalance on the processing process of radio frequency signals is small through down conversion, the demand on a direct current elimination circuit is small, and the high integration level, the high performance and the low power consumption are easy to realize. The phase-locked loop 100 and the passive mixer cooperate to reduce the power consumption of the radio frequency communication device, and the sampling clock of the analog-to-digital converter is also from the signal after M frequency division in the phase-locked loop 100, so that the requirement of an additional frequency divider and a clock module is saved while the required sampling frequency is met, thereby greatly reducing the overall required power consumption of the radio frequency communication device.

It should be understood that the detailed description of the embodiments of the present application is merely intended to help those skilled in the art to better understand the embodiments of the present application, and is not intended to limit the scope of the embodiments of the present application, and that various modifications and variations can be made by those skilled in the art on the basis of the above embodiments, and all such modifications or variations fall within the scope of protection of the present application.

Claims

1. A phase locked loop, the phase locked loop comprising:

a voltage controlled oscillator for generating a first clock signal; and

a first loop and a second loop,

wherein the first loop comprises:

a first frequency divider having a first frequency division ratio, the first frequency divider for generating a first feedback signal from the first clock signal;

the first phase frequency discriminator is used for generating a first control signal according to the phase difference between a first input signal and the first feedback signal;

a first charge pump that generates a first current signal according to the first control signal; and

a first filter connected to the first charge pump and the control terminal of the voltage controlled oscillator,

the second loop includes:

a second divider having a second division ratio, the second division ratio being less than the first division ratio, the second divider for generating a second feedback signal from the first clock signal;

the second phase frequency detector is used for generating a second control signal according to the phase difference between a second input signal and the second feedback signal;

a second charge pump that generates a second current signal according to the second control signal; and

A second filter connected to the second charge pump and the control terminal of the voltage controlled oscillator,

wherein the bandwidth of the first loop is smaller than the bandwidth of the second loop.

2. The phase locked loop of claim 1, wherein the order of the first filter is greater than the order of the second filter.

3. The phase locked loop of claim 1, wherein the first loop further comprises a third frequency divider and the second loop further comprises a frequency multiplier; the third frequency divider divides the frequency of the reference signal to obtain the first input signal; the frequency multiplier multiplies the reference signal to obtain the second input signal; the reference signal is provided by a crystal oscillator.

4. The phase locked loop of claim 1, wherein the voltage controlled oscillator is a differential ring oscillator; the differential ring oscillator comprises an n-level differential amplifier, wherein n is an even number greater than or equal to 4; the non-inverting input end of the (i+1) th differential amplifier is connected with the inverting output end of the i th differential amplifier, the inverting input end of the (i+1) th differential amplifier is connected with the non-inverting output end of the i th differential amplifier, i is more than or equal to 1 and less than or equal to n-1, the non-inverting output end of the n th differential amplifier is connected with the non-inverting input end of the 1 st differential amplifier, and the inverting output end of the n th differential amplifier is connected with the inverting input end of the 1 st differential amplifier; the first clock signal is an output signal of an in-phase output end or an anti-phase output end of a first-stage differential amplifier in the n-stage differential amplifier.

5. The phase locked loop of claim 1, wherein the first filter comprises: the voltage-controlled oscillator comprises a first node, a second node, a first capacitor, a second capacitor and a first resistor, wherein the first resistor is arranged between the first node and the second node, the first capacitor is arranged between the second node and the ground, the second capacitor is arranged between the first node and the ground, the output end of a first charge pump is connected with the first node, the second filter comprises the first capacitor, the output end of a second charge pump is connected with the second node, and the first node is connected with the control end of the voltage-controlled oscillator.

6. The phase locked loop of claim 1, wherein the number of capacitances of the first filter is greater than the number of capacitances of the second filter, the capacitances of the second filter being a subset of the capacitances of the first filter.

7. A phase locked loop as claimed in any one of claims 1 to 6, wherein the bandwidth of the first filter is smaller than the bandwidth of the second filter.

8. A phase locked loop, the phase locked loop comprising:

a voltage controlled oscillator for generating a first clock signal; and

A first loop and a second loop,

wherein the first loop comprises:

a first phase detector for generating a first control signal according to a phase difference between a first input signal and the first feedback signal; and

a first filter connected to the first phase detector and the control terminal of the voltage controlled oscillator,

the second loop includes:

a second phase detector for generating a second control signal according to a phase difference between a second input signal and the second feedback signal; and

a second filter connected to the second phase detector and the control end of the voltage controlled oscillator,

9. The phase locked loop of claim 8, wherein a bandwidth of the first filter is less than a bandwidth of the second filter;

The order of the first filter is larger than the order of the second filter;

the number of capacitances of the first filter is greater than the number of capacitances of the second filter, which is a subset of the capacitances of the first filter.

10. A phase locked loop as claimed in claim 8 or 9, wherein the first input signal and the second input signal are generated based on a reference signal, the first input signal being a divided signal of the reference signal and the second input signal being a multiplied signal of the reference signal; the reference signal is provided by a crystal oscillator.

11. A radio frequency communications device, comprising: mixer and phase locked loop according to any of the claims 1-10, wherein the mixer modulates a radio frequency signal based on a local oscillator signal, the local oscillator signal being generated from the first clock signal obtained from the phase locked loop.

12. The radio frequency communication device of claim 11, wherein the mixer is a down-conversion mixer, the local oscillator signal comprises four clock signals with a duty cycle of 25%, and the four clock signals with a duty cycle of 25% are 90 degrees out of phase; the local oscillation signal is generated according to a pair of first clock signals with the same frequency and 90-degree phase difference obtained from the phase-locked loop.

13. The radio frequency communication device according to claim 11 or 12, further comprising: the input end of the low-pass filter is connected with the output end of the mixer, the input end of the variable-gain amplifier is connected with the output end of the low-pass filter, the input end of the analog-to-digital converter is connected with the output end of the variable-gain amplifier, and the sampling clock of the analog-to-digital converter is generated according to the first clock signal.