CN116364725A

CN116364725A - Display panel

Info

Publication number: CN116364725A
Application number: CN202310372350.XA
Authority: CN
Inventors: 陈玠鸣; 林彬成; 简伯儒; 廖达文
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2022-11-18
Filing date: 2023-04-10
Publication date: 2023-06-30
Also published as: TWI826130B

Abstract

A display panel comprises a lower substrate, a light emitting diode chip and an upper substrate. The lower substrate comprises a dielectric layer, a first electrode pad and a second electrode pad. The first electrode pad is located on the dielectric layer. The second electrode pad is located on the dielectric layer and adjacent to the first electrode pad, and the first electrode pad and the second electrode pad are used for providing different potentials. The light emitting diode chip comprises a first electrode and a second electrode which are positioned at two opposite sides, and the first electrode is electrically connected with the first electrode pad. The upper substrate is arranged on the lower substrate and the light emitting diode chip, and the upper substrate comprises a carrier plate, an upper bank structure and a transparent conductive layer. The carrier plate has a surface facing the lower substrate. The upper bank structure is disposed on the surface. The transparent conductive layer covers the surface of the carrier plate and the upper bank structure, and is electrically connected with the second electrode and the second electrode pad.

Description

Display panel

Technical Field

Some embodiments of the present disclosure relate to a display panel.

Background

Led displays are one of the most common displays today. Generally, when manufacturing a light emitting diode display, a large number of transfer processes are required to transfer a large number of light emitting diode chips onto a specific carrier. And forming a transparent conductive layer on the LED chip and the carrier plate to electrically connect the electrodes of the LED chip with the electrodes on the carrier plate. When the electrode of the light emitting diode chip is not effectively connected with the electrode on the carrier plate, the light emitting diode chip is easy to fail.

Disclosure of Invention

Some embodiments of the present disclosure provide a display panel including a lower substrate, a light emitting diode chip, and an upper substrate. The lower substrate comprises a dielectric layer, a first electrode pad and a second electrode pad. The first electrode pad is located on the dielectric layer. The second electrode pad is located on the dielectric layer and adjacent to the first electrode pad, and the first electrode pad and the second electrode pad are used for providing different potentials. The light emitting diode chip comprises a first electrode and a second electrode which are positioned at two opposite sides, and the first electrode is electrically connected with the first electrode pad. The upper substrate is arranged on the lower substrate and the light emitting diode chip, and the upper substrate comprises a carrier plate, an upper bank structure and a transparent conductive layer. The carrier plate has a surface facing the lower substrate. The upper bank structure is disposed on the surface. The transparent conductive layer covers the surface of the carrier plate and the upper bank structure, and is electrically connected with the second electrode and the second electrode pad.

In some embodiments, the side of any of the upper bank structures forms an angle with the surface of the carrier plate, the angle being less than or equal to 50 degrees.

In some embodiments, the lower substrate further comprises a plurality of lower bank structures arranged on the dielectric layer, the lower bank structures being under the upper bank structures.

In some embodiments, the display panel further includes a conductive material, wherein a vertical projection of the conductive material on the lower substrate overlaps with a plurality of vertical projections of the upper bank structure on the lower substrate, and the conductive material is electrically connected to the transparent conductive layer and the second electrode pad.

In some embodiments, the conductive material is a metal or a conductive paste.

In some embodiments, the height of the conductive material is substantially equal to the height of the lower bank structure.

In some embodiments, the upper bank structure is a light absorbing material.

In some embodiments, the lower bank structure is a reflective material.

In some embodiments, the display panel further comprises a reflective layer between the upper bank structure and the transparent conductive layer.

In some embodiments, one of the upper bank structures includes an upper portion and a lower portion, the lower portion of one of the upper bank structures is adjacent to the lower bank structure, a vertical projection of the upper portion on the lower substrate overlaps a vertical projection of the lower portion on the lower substrate, and a vertical projection of the lower portion on the lower substrate overlaps a vertical projection of the second electrode pad on the lower substrate.

In some embodiments, one of the upper bank structures comprises an upper portion and a lower portion, the second bank structure of the upper bank structure being adjacent to the lower bank structure.

In summary, some embodiments of the present disclosure may be used to reduce the risk of wire breakage of the transparent conductive layer of the display panel. In particular, the slope of the transparent conductive layer may be reduced to reduce the risk of wire breakage of the transparent conductive layer. Therefore, the probability of failure of the light-emitting diode chip due to disconnection of the transparent conductive layer can be reduced.

Drawings

Fig. 1 illustrates a cross-sectional view of a display panel of some embodiments of the present disclosure.

Fig. 2 shows a cross-sectional view of the light emitting diode die of fig. 1.

Fig. 3A illustrates a bottom view of the upper substrate of fig. 1.

Fig. 3B shows a top view of the lower substrate of fig. 1.

Fig. 4 to 7 are cross-sectional views illustrating a process of manufacturing a display panel.

Fig. 8 illustrates a cross-sectional view of a display panel of other embodiments of the present disclosure.

Fig. 9 shows a cross-sectional view of the light emitting diode die of fig. 8.

Fig. 10A illustrates a bottom view of the upper substrate of fig. 8.

Fig. 10B shows a top view of the lower substrate of fig. 8.

Fig. 11 illustrates a cross-sectional view of a display panel of other embodiments of the present disclosure.

Fig. 12 illustrates a cross-sectional view of a display panel of other embodiments of the present disclosure.

Fig. 13 illustrates a cross-sectional view of a display panel of other embodiments of the present disclosure.

Reference numerals illustrate:

10: display panel

10A: display panel

10B: display panel

10C: display panel

100: lower substrate

100': lower substrate

110: dielectric layer

112: dielectric layer

120: first electrode pad

130: second electrode pad

140: substrate board

150: active device

160: lower bank structure

170: first through hole part

180: second through hole part

200: light emitting diode chip

200B: light emitting diode chip

200G: light emitting diode chip

200R: light emitting diode chip

210: first electrode

212: first layer

214: second layer

220: second electrode

222: first layer

224: second layer

230: epitaxial layer

232: n-type semiconductor layer

234: multiple quantum well layer

236: p-type semiconductor layer

240: insulating layer

300: upper base plate

310: carrier plate

310S: surface of the body

320: upper bank structure

320S: side surface

322: first bank structure

324: second bank structure

326: upper part

326S: side surface

328: lower part

328S: side surface

330: transparent conductive layer

340: reflective layer

400: conductive material

402: sealant

404: conductive ball

500: adhesive layer

a1: included angle

a2: included angle

a3: included angle

D1: first direction

H1: height of (1)

H2: height of (1)

H4: height of (1)

And H5: height of (1)

H6: height of (1)

H7: height of (1)

Detailed Description

The following description sets forth preferred embodiments of the present disclosure and the accompanying drawings are provided to illustrate the construction of the present disclosure and the technical effects to be achieved, so that those skilled in the art to which the present disclosure pertains will be able to further understand the present disclosure.

Some embodiments of the present disclosure may be used to reduce the risk of disconnection of a transparent conductive layer of a display panel. In particular, the slope of the transparent conductive layer may be reduced to reduce the risk of wire breakage of the transparent conductive layer. Therefore, the probability of failure of the light-emitting diode chip due to disconnection of the transparent conductive layer can be reduced.

Fig. 1 illustrates a cross-sectional view of a display panel 10 of some embodiments of the present disclosure. The display panel 10 includes a lower substrate 100, a light emitting diode chip 200, and an upper substrate 300. The lower substrate 100 includes a dielectric layer 110, a first electrode pad 120 and a second electrode pad 130. The upper substrate 300 is disposed on the lower substrate 100 and the light emitting diode chip 200, and the upper substrate 300 includes a carrier 310 and a transparent conductive layer 330.

The lower substrate 100 may be a panel including driving elements. The lower substrate 100 includes a plurality of dielectric layers 110 stacked from bottom to top, and the dielectric layers 110 may be formed on the substrate 140. In some embodiments, as shown in fig. 1, the lower substrate 100 may include active devices 150, such as thin film transistors (thin film transistor, TFTs). In other embodiments, the lower substrate 100 may also include other driving devices such as micro chips (microchips), or the active devices may not be located as shown in fig. 1, for example, the active devices may be located under the substrate 140 and drive the display panel 10 in a double-sided wiring manner. The first electrode pad 120 is located on the dielectric layer 110. The second electrode pad 130 is disposed on the dielectric layer 110 and adjacent to the first electrode pad 120, and the first electrode pad 120 and the second electrode pad 130 are used for providing different potentials. In some embodiments, the lower substrate 100 includes a dielectric layer 112 between the dielectric layers 110, and the dielectric layer 112 may be made of silicon nitride. The lower substrate 100 further includes a plurality of lower bank structures 160 arranged on the dielectric layer 110.

The light emitting diode chip 200 includes a first electrode 210 and a second electrode 220 disposed on opposite sides, the first electrode 210 is electrically connected to the first electrode pad 120, and the first electrode 210 and the second electrode 220 have an epitaxial layer 230. Specifically, the lower substrate 100 may further include a first via 170 and a second via 180. The first via 170 and the second via 180 are located in the dielectric layer 110. The first via 170 is electrically connected to the active device 150 and the first electrode 210 of the led chip 200. The second through hole 180 is electrically connected to the ground electrode (not shown) and the second electrode 220 of the light emitting diode chip 200A. It should be noted that although fig. 1 shows that the second vias 180 on different dielectric layers 110 are not interconnected, the second vias 180 on different dielectric layers 110 may still be interconnected in cross-section different from that shown in fig. 1.

The upper substrate 300 may be a substrate electrically connecting the second electrode 220 of the light emitting diode chip 200 with the second electrode pad 130 of the lower substrate 100. The upper substrate 300 includes a carrier 310, the carrier 310 having a surface 310S facing the lower substrate 100. A plurality of upper bank structures 320 are disposed on the surface 310S. The transparent conductive layer 330 covers the surface 310S of the carrier 310 and the upper bank structure 320, and the transparent conductive layer 330 is electrically connected to the second electrode 220 and electrically connected to the second electrode 220 through the conductive material 400. In other words, the transparent conductive layer 330 is electrically connected to the second electrode 220 and the second electrode pad 130.

The lower bank structure 160 of the lower substrate 100 is under the upper bank structure 320. In some embodiments, the vertical projection of the lower bank structure 160 to the lower substrate 100 overlaps the vertical projection of the upper bank structure 320 to the lower substrate 100. More specifically, the upper bank structure 320 includes a first bank structure 322 and a second bank structure 324. The vertical projection of the first bank structure 322 on the lower substrate 100 overlaps with the vertical projections of the lower bank structure 160 on the lower substrate 100, and the vertical projection of the second bank structure 324 on the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 on the lower substrate 100. The height H1 of the first bank structure 322 is the same as the height H2 of the second bank structure 324. The height H4 of the led chip 200 is equal to the distance between the transparent conductive layer 330 and the first electrode pad 120 on the carrier 310, so as to ensure that the led chip 200 can be electrically connected to the transparent conductive layer 330 and the first electrode pad 120 at the same time.

The display panel 10 further includes a conductive material 400, wherein a vertical projection of the conductive material 400 on the lower substrate 100 overlaps a vertical projection of the upper bank structure 320 on the lower substrate 100, and is electrically connected to the transparent conductive layer 330 and the second electrode pad 130. The height H5 of the conductive material 400 is equal to the distance between the transparent conductive layer 330 and the second electrode pad 130 on the upper bank structure 320, so as to ensure that the conductive material 400 can electrically connect the transparent conductive layer 330 and the second electrode pad 130 at the same time. In some embodiments, the conductive material 400 is a metal or a conductive paste. For example, in fig. 1, the conductive material 400 is a conductive paste, and the conductive material 400 is composed of a sealing paste 402 and conductive balls 404. The conductive balls 404 are uniformly dispersed in the encapsulant 402. The sealant 402 may be an acrylic-epoxy, photoinitiator, thermal hardener, couplant, filler, combinations thereof, or the like. The conductive balls 404 may be balls with sequentially coated nickel layers and gold layers on the surface, and may be used to electrically connect the second electrode pad 130 and the transparent conductive layer 330.

Since the height H4 of the light emitting diode chip 200 is substantially equal to the distance between the transparent conductive layer 330 on the carrier plate 310 and the first electrode pad 120, and the transparent conductive layer 330 is formed only on the surface of the upper bank structure 320, the slope of the transparent conductive layer 330 is formed to be small. The electrical connection between the upper bank structure 320 and the second electrode pad 130 is made by the conductive material 400, so that the transparent conductive layer 330 is less likely to break due to the steep gradient, and the led chip 200 is disabled. In some embodiments, the side 320S of any one of the upper bank structures 320 forms an angle a1 with the surface 310S of the carrier plate 310, the angle a1 being less than or equal to 50 degrees. When the included angle a1 is less than or equal to 50 degrees, the gradient of the transparent conductive layer 330 is small, and thus it is less likely to break. Conversely, when the included angle a1 is greater than 50 degrees, the probability of breaking the transparent conductive layer 330 is increased.

In some embodiments, the upper and

lower bank structures

320 and 160 may be made using a suitable material, and the shapes of the upper and

lower bank structures

320 and 160 are designed to enhance the visual experience of the display panel 10. In some embodiments, the upper and

lower bank structures

320 and 160 may be made of different materials. For example, the lower bank structure 160 may be made of a reflective material to reflect the light emitted from the led chip 200 upwards, so as to improve the upward light-emitting efficiency of the display panel 10. The upper bank structure 320 may be a light absorbing material to absorb ambient light incident from the outside of the display panel 10 to reduce interference of the display panel 10 by the ambient light. Further, the upper bank structure 320 may have an inverted trapezoid shape, and the lower bank structure 160 may have a regular trapezoid shape. For example, the width of the upper bank structure 320 gradually becomes smaller toward the lower substrate 100, and the width of the lower bank structure 160 gradually increases toward the lower substrate 100. Thus, the inclined sides of the regular trapezoid shape of the lower bank structure 160 help to reflect light emitted from the light emitting diode chip 200 sideways upward. The inverted trapezoid shape of the upper bank structure 320 has a large upper surface, and can also more effectively absorb ambient light incident from the outside of the display panel 10. In some embodiments, the upper bank structure 320 may be formed of a black organic material, and a shielding rate (optical density) is not less than 1.0, for example, the shielding rate may be 2.0. The lower bank structure 160 may be formed of a white organic material and has a reflectivity of not less than 50%. For example, the reflectivity may be greater than or equal to 70%. The upper and

lower bank structures

320 and 160 may also be made of a compressible material. In some embodiments, the compression ratio of the material of the upper and

lower bank structures

320 and 160 is between 80% and 90%. Therefore, before the upper substrate 300 and the lower substrate 100 are assembled together, the thickness of the upper bank structure 320 and the thickness of the lower bank structure 160 are larger in sum. After the upper substrate 300 and the lower substrate 100 are assembled together, the thickness of the upper bank structure 320 and the thickness of the lower bank structure 160 are compressed, so that the transparent conductive layer 330 of the upper substrate 300 can be surely in contact with the conductive material 400.

The display panel 10 further includes an adhesive layer 500. The adhesive layer 500 is between the upper substrate 300 and the lower substrate 100 for adhering the upper substrate 300 and the lower substrate 100 and providing a supporting force. In some embodiments, the adhesive layer 500 may be made of a sealant doped with a small amount of a support. The sealant of the adhesive layer 500 may be an acrylic-epoxy resin, a photoinitiator, a thermal hardener, a coupling agent, a filler, a combination thereof, or the like to bond the upper substrate 300 and the lower substrate 100. The support may be a fiber or a silicon ball or the like that provides a supporting force, and the size of the support may be selected according to a target height between the upper substrate 300 and the lower substrate 100.

Fig. 2 illustrates a cross-sectional view of the light emitting diode chip 200 of fig. 1. The light emitting diode chip 200 includes a first electrode 210, a second electrode 220, an epitaxial layer 230 and an insulating layer 240. The first electrode 210 includes a first layer 212 and a second layer 214, with the second layer 214 between the first layer 212 and the epitaxial layer 230. The first layer 212 and the second layer 214 of the first electrode 210 may be made of conductors. In some embodiments, the first layer 212 may be made of nickel, tin, gold, or a combination thereof. The second layer 214 may be made of aluminum. The second electrode 220 may be made of a transparent conductive layer, such as Indium Tin Oxide (ITO), so that when the led chip 200 emits light upward (i.e., toward the second electrode 220 of fig. 1 and 2), the light can still penetrate the second electrode 220. The epitaxial layer 230 is between the first electrode 210 and the second electrode 220. The width of the epitaxial layer 230 may be narrower as it is closer to the second electrode 220, i.e., the epitaxial layer 230 may be a positive trapezoid. The epitaxial layer 230 may include an N-type semiconductor layer 232, a Multiple-Quantum Well (MQW) layer 234, and a P-type semiconductor layer 236. In some embodiments, the N-type semiconductor layer 232 and the P-type semiconductor layer 236 may be N-type doped gallium nitride and P-type doped gallium nitride, respectively. An insulating layer 240 is on the sidewall of the epitaxial layer 230 and encapsulates a portion of the second electrode 220. In some embodiments, the insulating layer 240 may be an oxide layer.

Fig. 3A illustrates a bottom view of the upper substrate 300 of fig. 1. Fig. 3B illustrates a top view of the lower substrate 100 of fig. 1. In fig. 3A, the upper bank structures 320 of the upper substrate 300 are arranged on the surface 310S of the carrier 310 along the first direction D1. A plurality of upper bank structures 320, such as but not limited to 3, may be formed in one unit with one large space between the upper bank structures 320 per unit. The larger space is for accommodating the light emitting diode chip 200. The transparent conductive layer 330 covers the surface 310S of the carrier 310 and the upper bank structure 320.

In fig. 3B, the lower bank structures 160 of the lower substrate 100 are arranged on the dielectric layer 110 along the first direction D1, and the distance between each of the lower bank structures 160 is substantially the same. Each of the lower bank structures 160 may correspond to one of the upper bank structures 320. The light emitting diode chip 200 may be located between two adjacent lower bank structures 160, and the light emitting diode chip 200 may be accommodated in a space between the upper bank structures 320. In some embodiments, the led chip 200 may include led

chips

200R, 200B and 200G emitting different colors, and the led

chips

200R, 200B and 200G may also be arranged along the first direction D1 and each located between two adjacent lower bank structures 160. Conductive material 400 may also be located between two adjacent lower bank structures 160, with conductive material 400 corresponding to one of the upper bank structures 320. The adhesive layer 500 is located at the periphery of the lower substrate 100 and thus can be used to adhere the lower substrate 100 and the upper substrate 300.

Fig. 4 to 7 show cross-sectional views of a process of manufacturing the display panel 10. In fig. 4, a lower substrate 100' is provided.

In fig. 5, a lower bank structure 160 is formed on the lower substrate 100' to form the lower substrate 100, and the lower bank structure 160 does not cover the first electrode pad 120 and the second electrode pad 130. The details of the lower substrate 100 are as described in fig. 1, and thus are not described herein.

In fig. 6, the light emitting diode chip 200 is transferred on the first electrode pad 120 such that the first electrode pad 120 of the lower substrate 100 is connected to the first electrode 210 of the light emitting diode chip 200.

In fig. 7, a conductive material 400 is formed on the second electrode pad 130 of the lower substrate 100 and an adhesive layer 500 is formed on the periphery of the lower substrate 100, and then the upper substrate 300 is placed on the lower substrate 100, so that the second electrode pad 130 of the lower substrate 100 is connected to the second electrode 220 of the light emitting diode chip 200 through the conductive material 400 and the transparent conductive layer 330 to form the display panel 10. Since the transparent conductive layer 330 is formed on the upper substrate 300 in advance, when the upper substrate 300 is directly disposed on the lower substrate 100, the second electrode pad 130 and the second electrode 220 can be simultaneously connected without forming additional materials for electrical connection around the led chip 200, so as to avoid the led chip 200 from falling off due to the formation of the additional materials.

Fig. 8 illustrates a cross-sectional view of a display panel 10A of other embodiments of the present disclosure. The display panel 10A is similar to the display panel 10 of fig. 1, and the difference between the two is that the structure of the light emitting diode chip 200 of the display panel 10A is different from that of the light emitting diode chip 200 of the display panel 10, and the position of the transparent conductive layer 330 is different from that of the conductive material 400. Specifically, the first electrode 210 of the light emitting diode chip 200 of the display panel 10A of fig. 8 is electrically connected to the first electrode pad 120 through the transparent conductive layer 330, and the second electrode 220 of the light emitting diode chip 200 of the display panel 10A is directly contacted and electrically connected to the second electrode pad 130. The first electrode 210 of the light emitting diode chip 200 of the display panel 10 of fig. 1 is directly contacted with and electrically connected to the first electrode pad 120, and the second electrode 220 of the light emitting diode chip 200 of the display panel 10 is electrically connected to the second electrode pad 130 through the transparent conductive layer 330. In addition, the vertical projection of the second bank structure 324 of the upper bank structure 320 of the display panel 10A of fig. 8 on the lower substrate 100 overlaps with the vertical projection of the first electrode pad 120 on the lower substrate 100, and the vertical projection of the second bank structure 324 of the upper bank structure 320 of the display panel 10 of fig. 1 on the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 on the lower substrate 100. In some embodiments, at least one upper bank structure 320 and lower bank structure 160 are in direct contact.

Fig. 9 illustrates a cross-sectional view of the light emitting diode chip 200 of fig. 8. The light emitting diode chip 200 includes a first electrode 210, a second electrode 220, an epitaxial layer 230 and an insulating layer 240. The first electrode 210 may be made of a transparent conductive layer, such as Indium Tin Oxide (ITO), so that when the led chip 200 emits light upward (i.e., toward the first electrode 210 in fig. 8 and 9), the light can still penetrate the first electrode 210. The second electrode 220 includes a first layer 222 and a second layer 224, and the second layer 224 is between the first layer 222 and the epitaxial layer 230. The first layer 222 and the second layer 224 of the second electrode 220 may be made of conductors. In some embodiments, the first layer 222 may be made of nickel, tin, gold, or a combination thereof. The second layer 224 may be made of aluminum. The epitaxial layer 230 is between the first electrode 210 and the second electrode 220. The width of the epitaxial layer 230 may be wider as it is closer to the first electrode 210, i.e., the epitaxial layer 230 may be inverted trapezoid. The epitaxial layer 230 may include an N-type semiconductor layer 232, a Multiple-Quantum Well (MQW) layer 234, and a P-type semiconductor layer 236. In some embodiments, the N-type semiconductor layer 232 and the P-type semiconductor layer 236 may be N-type doped gallium nitride and P-type doped gallium nitride, respectively. An insulating layer 240 is on the sidewall of the epitaxial layer 230 and encapsulates a portion of the first electrode 210. In some embodiments, the insulating layer 240 may be an oxide layer.

Fig. 10A illustrates a bottom view of the upper substrate 300 of fig. 8. Fig. 10B illustrates a top view of the lower substrate 100 of fig. 8. In fig. 10A, the upper bank structures 320 of the upper substrate 300 are arranged on the surface 310S of the carrier 310 along the first direction D1. A plurality of upper bank structures 320, such as but not limited to 3, may be formed in one unit with one large space between the upper bank structures 320 per unit. The larger space is for accommodating the light emitting diode chip 200. The transparent conductive layer 330 covers the surface 310S of the carrier 310 and the upper bank structure 320. Unlike the upper substrate 300 of fig. 10A, the transparent conductive layer 330 of the upper substrate 300 of fig. 3A is responsible for connecting the second electrode 220 of the light emitting diode chip 200 to the second electrode pad 130 (i.e., the ground electrode), so that the transparent conductive layer 330 may cover the entire upper bank structure 320. On the other hand, the transparent conductive layer 330 of the upper substrate 300 of fig. 10A is responsible for connecting the first electrode 210 of the light emitting diode chip 200 to the first electrode pad 120 and the active device 150, so the upper substrate 300 includes a plurality of transparent conductive layers 330, and each transparent conductive layer 330 covers a portion of the upper bank structure 320 and the space for accommodating the light emitting diode chip 200. The transparent conductive layer 330 may also not cover part of the upper bank structure 320.

In fig. 10B, the lower bank structures 160 of the lower substrate 100 are arranged on the dielectric layer 110 along the first direction D1, and the distance between each of the lower bank structures 160 is substantially the same. Each of the lower bank structures 160 may correspond to one of the upper bank structures 320. The light emitting diode chip 200 may be located between two adjacent lower bank structures 160, and the light emitting diode chip 200 may be accommodated in a space between the upper bank structures 320 and contact the transparent conductive layer 330. In some embodiments, the led chip 200 may include led

chips

200R, 200B and 200G emitting different colors, and the led

chips

Fig. 11 shows a cross-sectional view of a display panel 10B of other embodiments of the present disclosure. The display panel 10B is similar to the display panel 10 of fig. 1, with the difference that the conductive material 400 of the display panel 10B of fig. 11 is metal, and the conductive material 400 of the display panel 10 of fig. 1 is conductive paste.

Fig. 12 shows a cross-sectional view of a display panel 10C of other embodiments of the present disclosure. The display panel 10C is similar to the display panel 10 of fig. 1, with the difference that one of the upper bank structures 320 of the display panel 10B of fig. 11 includes an upper portion 326 and a lower portion 328, the lower portion 328 of the upper bank structure 320 being adjacent to the lower bank structure 160. The vertical projection of the upper portion 326 on the lower substrate 100 overlaps with the vertical projection of the lower portion 328 on the lower substrate 100, and the vertical projection of the lower portion 328 on the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 on the lower substrate 100. The side 326S of the upper portion 326 of the upper bank structure 320 is not interconnected with the side 328S of the lower portion 328 of the upper bank structure 320, and the transparent conductive layer 330 covers the upper portion 326 and the lower portion 328 of the upper bank structure 320. The side 326S of the upper portion 326 of the upper bank structure 320 forms an angle a2 with the surface 310S of the carrier plate 310, and the side 328S of the lower portion 328 of the upper bank structure 320 forms an angle a3 with the surface 310S of the carrier plate 310, the angles a2 and a3 being less than or equal to 50 degrees. In some embodiments, the height H7 of the lower surface of the lower portion 328 relative to the lower substrate 100 is smaller than the height H6 of the lower surface of the upper portion 326 relative to the lower substrate 100, so that the lower portion 328 can be closer to the second electrode pad 130, such that the electrical connection between the transparent conductive layer 330 and the second electrode pad 130 can be completed without disposing the conductive material 400.

Fig. 13 illustrates a cross-sectional view of a display panel 10D of other embodiments of the present disclosure. The display panel 10D is similar to the display panel 10 of fig. 1, with the difference that the display panel 10D further comprises a reflective layer 340 between the upper bank structure 320 and the transparent conductive layer 330. The reflective layer 340 can be used to reflect the light emitted from the led chip 200 upwards, so as to further improve the upward light-emitting efficiency of the display panel 10. In some embodiments, the light reflecting layer 340 may be made of metal.

In summary, some embodiments of the present disclosure may reduce the risk of disconnection of the transparent conductive layer in the display panel. For example, the display panel may include an upper substrate and a lower substrate. The transparent conductive layer may be formed only on the upper bank structure of the upper substrate and electrically connected to the lower substrate through an additional conductive material. Therefore, the included angle between the side wall of the upper bank structure of the upper substrate and the surface of the carrier plate of the upper substrate can be designed to be smaller, so that the risk of broken lines of the transparent conductive layer is reduced. Therefore, the LED chip in the display panel is not easy to fail due to the disconnection of the transparent conductive layer.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather, it should be apparent to one skilled in the art that various changes and modifications can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A display panel, comprising:

a lower substrate comprising:

a dielectric layer;

a first electrode pad on the dielectric layer; and

a second electrode pad on the dielectric layer, adjacent to the first electrode pad, wherein the first electrode pad and the second electrode pad are used for providing different potentials;

the LED chip comprises a first electrode and a second electrode which are positioned at two opposite sides, and the first electrode is electrically connected with the first electrode pad; and

an upper substrate on the lower substrate and the light emitting diode chip, the upper substrate comprising:

a carrier plate having a surface facing the lower substrate;

a plurality of upper bank structures disposed on the surface; and

and the transparent conductive layer covers the surface of the carrier plate and the upper bank structures and is electrically connected with the second electrode and the second electrode pad.

2. The display panel of claim 1, wherein a side of any of the upper bank structures forms an angle with the surface of the carrier plate, the angle being less than or equal to 50 degrees.

3. The display panel of claim 1, further comprising a conductive material overlapping a vertical projection of the conductive material on the lower substrate and a plurality of vertical projections of the upper bank structures on the lower substrate and electrically connecting the transparent conductive layer and the second electrode pad.

4. The display panel of claim 3, wherein the conductive material is metal or conductive paste.

5. The display panel of claim 3, wherein the lower substrate further comprises a plurality of lower bank structures arranged on the dielectric layer, the lower bank structures underlying the upper bank structures.

6. The display panel of claim 5, wherein a height of the conductive material is substantially equal to a plurality of heights of the lower bank structures.

7. The display panel of claim 5, wherein the lower bank structures are reflective materials.

8. The display panel of claim 5, wherein one of the upper bank structures comprises an upper portion and a lower portion, the lower portion of one of the upper bank structures is adjacent to the lower bank structures, a vertical projection of the upper portion on the lower substrate overlaps a vertical projection of the lower portion on the lower substrate, and the vertical projection of the lower portion on the lower substrate overlaps a vertical projection of the second electrode pad on the lower substrate.

9. The display panel of claim 1, wherein the upper bank structures are light absorbing materials.

10. The display panel of claim 1, further comprising a reflective layer between the upper bank structures and the transparent conductive layer.