CN116364560A - Semiconductor packaging structure and preparation method thereof - Google Patents

Semiconductor packaging structure and preparation method thereof Download PDF

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Publication number
CN116364560A
CN116364560A CN202310540373.7A CN202310540373A CN116364560A CN 116364560 A CN116364560 A CN 116364560A CN 202310540373 A CN202310540373 A CN 202310540373A CN 116364560 A CN116364560 A CN 116364560A
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China
Prior art keywords
chip
dummy
substrate
pad
welding area
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CN202310540373.7A
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Chinese (zh)
Inventor
陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202310540373.7A priority Critical patent/CN116364560A/en
Publication of CN116364560A publication Critical patent/CN116364560A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, wherein the semiconductor packaging structure comprises the following components: the packaging substrate is defined with a first chip welding area and a second chip welding area, the first chip welding area is adjacent to the second chip welding area and has a first gap, and the packaging substrate is also provided with at least one dummy pad which spans the first gap and covers part of the surfaces of the first chip welding area and the second chip welding area; the first chip is provided with a first dummy bump, the second chip is provided with a second dummy bump, and the first dummy bump and the second dummy bump are connected with the dummy pad in a bonding way; and the filling material layer is filled in gaps among the packaging substrate, the first chip and the second chip. The semiconductor packaging structure and the preparation method thereof can solve the problem that the existing packaging structure has cracks of the bottom filling material caused by stress concentration.

Description

Semiconductor packaging structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method thereof.
Background
The current advanced packaging technology has more and more densely packed leads and solder joints per unit area, and the 2.5D and fan-out packages have larger sizes, so that the reliability of the package body faces serious challenges, because CTE (coefficient of thermal expansion) mismatch among materials can generate Warpage (warp) in the thermal cycle process.
Because the integral package structure cannot directly release the stress generated by warpage, as shown in fig. 1, the stress is concentrated between the first core 21 and the second chip 22, which may cause the problems of cracking of the filling material layer 130 (render the inside of the package body corroded by water vapor), delamination, and failure of electromagnetic shielding Effect (EMI), and the cracks may also extend downward to damage the package substrate 40 bonded to the chip (with the structure of through holes, re-wiring layers, etc.), thereby affecting the electrical connection effect.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor package and a method for manufacturing the same, which are used for solving the problem that the underfill cracks due to stress concentration in the conventional package.
To achieve the above and other related objects, the present invention provides a semiconductor package structure comprising:
the packaging substrate comprises a first surface and a second surface opposite to the first surface, wherein the first surface is defined with a first chip welding area and a second chip welding area, the first chip welding area is adjacent to the second chip welding area and has a first gap, the first surface is also provided with at least one dummy bonding pad, and the dummy bonding pad spans the first gap and covers part of the surfaces of the first chip welding area and the second chip welding area;
the semiconductor device comprises a first chip and a second chip, wherein at least one first dummy bump is arranged at a first position of an active surface of the first chip, and at least one second dummy bump is arranged at a second position of the active surface of the second chip; the first position is a position corresponding to the dummy pad in the first chip active surface at the first chip bonding region covering part, the second position is a position corresponding to the dummy pad in the second chip active surface at the second chip bonding region covering part, and the first dummy bump and the second dummy bump are connected with the dummy pad in a bonding manner;
and the filling material layer is filled in gaps among the packaging substrate, the first chip and the second chip.
Optionally, the semiconductor package structure further includes a third chip; the first surface is also defined with a third chip welding area;
the third chip welding area is adjacent to the second chip welding area and has a second gap;
at least one of the dummy pads also spans a second of the second gaps and covers a portion of a surface of the second die bonding region and the third die bonding region;
at least one third dummy bump is disposed at a third position of the active surface of the third chip, where the third position is a position of the active surface of the third chip corresponding to a portion of the dummy pad covered by the third chip bonding region, and the second dummy bump and the third dummy bump are bonded with the dummy pad.
Optionally, the first chip bonding region, the second chip bonding region and the third chip bonding region are adjacent to each other;
one of the dummy pads covers part of the surfaces of the first chip bonding region, the second chip bonding region and the third chip bonding region at the same time;
the first dummy bump, the second dummy bump, and the third dummy bump are bonded to the dummy pad.
Optionally, the semiconductor package structure further includes:
and the plastic sealing layer is formed on the first surface and coats each chip.
Optionally, the package substrate includes an interposer, the interposer is formed with a through hole, and the dummy pad is insulated from the through hole.
Optionally, the package substrate includes an interposer, where a through hole and a rewiring layer are formed on the interposer, and the dummy pad is insulated from the through hole.
The invention also provides a preparation method of the semiconductor packaging structure, which comprises the following steps:
providing an intermediate structure, wherein the intermediate structure comprises a first temporary carrier plate and a packaging substrate positioned on the upper surface of the first temporary carrier plate, the packaging substrate comprises a first surface and a second surface opposite to the first surface, the first surface is defined with a first chip welding area and a second chip welding area, the first chip welding area is adjacent to the second chip welding area and has a first gap, the first surface is also provided with at least one dummy bonding pad, and the dummy bonding pad spans the first gap and covers part of the surfaces of the first chip welding area and part of the surfaces of the second chip welding area;
providing a first chip and a second chip, wherein at least one first dummy bump is arranged at a first position of an active surface of the first chip, and at least one second dummy bump is arranged at a second position of the active surface of the second chip; the first position is a position of the first chip active surface corresponding to the covering part of the dummy pad in the first chip welding area, and the second position is a position of the second chip active surface corresponding to the covering part of the dummy pad in the second chip welding area;
bonding the first chip to the package substrate in the first chip bonding region, bonding the second chip to the package substrate in the second chip bonding region, and bonding the dummy bump to the dummy pad;
filling a filling material layer into gaps between the first chip and the second chip which are connected with the packaging substrate in a bonding way.
Optionally, after filling the filling material layer, the preparation method further includes:
forming a plastic sealing layer on the first surface, wherein the plastic sealing layer wraps the first chip and the second chip;
and removing the first temporary carrier plate.
Optionally, the preparation method of the intermediate structure comprises the following steps:
providing a substrate, wherein a blind hole is formed in the substrate, and a metal column is filled in the blind hole;
forming a bonding pad and the dummy pad on the upper surface of the substrate, wherein the bonding pad is connected with the metal column, and the dummy pad is electrically isolated from the bonding pad;
providing a second temporary carrier plate, and fixing the upper surface of the substrate on the second temporary carrier plate;
thinning the lower surface of the substrate until the metal posts are exposed;
forming a conductive bump on the lower surface of the substrate, wherein the conductive bump is connected with the metal column;
providing the first temporary carrier plate, and fixing the lower surface of the substrate on the first temporary carrier plate;
and removing the second temporary carrier plate.
Optionally, after the lower surface of the substrate is thinned and before the conductive bump is formed on the lower surface of the substrate, the method for preparing the intermediate structure further includes a step of forming a redistribution layer on the lower surface of the substrate, where the redistribution layer is connected to the conductive bump.
As described above, according to the semiconductor package structure and the method for manufacturing the same, the dummy bumps are respectively arranged in two adjacent chips, the dummy pads are correspondingly arranged on the package substrate, the dummy bumps are insulated from circuits in the chips, the dummy pads are insulated from circuits in the package substrate, and after the chips are bonded and connected with the package substrate, the dummy pads are also bonded and connected with the dummy bumps respectively, so that a structure reinforcing bridge crossing the lower parts of the two chips is formed, the two adjacent chips are connected by the structure reinforcing bridge, and the problems of crack generation of welding spots caused by shrinkage and expansion of an underfill layer, layering, electromagnetic shielding failure, circuit interruption and the like of the package structure can be effectively prevented.
Drawings
Fig. 1 is a schematic view showing a semiconductor package structure in which a filling material layer between adjacent chips is cracked due to warpage.
Fig. 2 is a schematic diagram showing a semiconductor package structure in which a connection portion between a micro bump of a chip and a bonding pad is broken due to expansion of a filling material layer.
Fig. 3 is a schematic view showing prevention of cracking of the filler material layer after bonding of the dummy bump to the dummy pad.
Fig. 4 is a schematic view showing prevention of breakage of the flip-chip bonding pads after bonding of the dummy bumps to the dummy pads. .
Fig. 5 is a flowchart of a method for manufacturing a semiconductor package according to the present invention.
Fig. 6 is a top view of a semiconductor package according to the present invention.
Fig. 7 shows a schematic structural diagram of the intermediate structure according to the present invention.
Fig. 8 is a schematic structural diagram of a semiconductor package according to the present invention.
Fig. 9 is a schematic view showing a partial structure of the semiconductor package structure of fig. 8.
Fig. 10 shows a flow chart of a method for preparing an intermediate structure according to the invention.
Fig. 11 is a schematic view showing the structure of a substrate with blind holes according to the present invention.
Fig. 12 is a schematic diagram of a structure of the dummy pad according to the present invention after formation.
Fig. 13 is a schematic structural view of the second temporary carrier according to the present invention.
Fig. 14 is a schematic view of the structure of the thinned substrate according to the present invention.
Fig. 15 is a schematic view of a structure after forming conductive bumps according to the present invention.
Fig. 16 is a schematic structural view of the first temporary carrier according to the present invention.
Fig. 17 is a schematic structural diagram of the present invention after the second temporary carrier plate is removed.
Fig. 18 is a schematic structural diagram of the chip bonded to the package substrate according to the present invention.
Fig. 19 is a schematic view showing a structure after forming the filling material layer according to the present invention.
Fig. 20 shows a schematic structural diagram of the intermediate structure according to the present invention.
Fig. 21 is a schematic structural view of a semiconductor package according to the present invention.
Description of the component reference numerals
10. Semiconductor packaging structure
100. Substrate and method for manufacturing the same
101. Blind hole
102. Soldering pad
103. Dummy pad
104. Conductive bump
110. Second temporary carrier plate
120. First temporary carrier plate
130. Filling material layer
140. Plastic seal layer
121-128 first chip bonding region to eighth chip bonding region
21-24 first chip-fourth chip
210. Microbump
211. First dummy bump
221. Second dummy bump
30. Intermediate structure
40. Packaging substrate
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 21. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The present embodiment provides a semiconductor package structure 10, as shown in fig. 9, the semiconductor package structure 10 includes: the package substrate 40, the first chip 21, the second chip 22 and the filling material layer 130. It should be noted that, as shown in fig. 6 and 8, N chips (N is greater than or equal to 2) may be packaged on the package substrate 40, and not only two chips are packaged, but the package substrate 40 is correspondingly divided into N chip bonding areas that are bonded to the chips, and these chip bonding areas are adjacent to each other but not in contact, and as an example, the package substrate 40 in fig. 6 includes the first chip bonding area 121 to the eighth chip bonding area 128, and 4 chip bonding areas are shown in fig. 7; two adjacent chips within the dashed-line frame in fig. 8 are defined as a first chip 210 and a second chip 220, and the structure in fig. 9 is shown as a schematic partial structure of the semiconductor package 10 having the first chip 210 and the second chip 220, and the semiconductor package 10 according to this embodiment will be described below based on fig. 9.
As shown in fig. 9, a surface of the package substrate 40 to which the chip is bonded is defined as a first surface, and the opposite surface is defined as a second surface; the package substrate 40 defines two adjacent areas that are not in contact with each other, namely a first chip bonding area 121 (an area where the first chip 21 is bonded to the package substrate 40) and a second chip bonding area 122 (an area where the second chip 22 is bonded to the package substrate 40); a plurality of bonding pads 102 are distributed on the first surface, one side of the bonding pads 102 is connected with a connection line of the package substrate 40, and the other side is connected with a micro bump 210 on the active surface of the chip (the surface of the chip with the micro bump 210 is defined as the active surface), so that the bonding pads 102 and the micro bump 210 serve as a channel for electrically connecting the chip with the package substrate 40; the first surface is also provided with a dummy pad 103, and the dummy pad 103 is disposed across the first and second chip bonding regions 121 and 122 and is insulated from the connection line in the package substrate 40.
As shown in fig. 9, the first chip 21 has a microbump 210 disposed on the active surface thereof, and a first dummy bump 211 disposed on the side adjacent to the second chip 22; the second chip 22 has a microbump 210 disposed on an active surface thereof, and a second dummy bump 221 disposed on a side of the second chip adjacent to the first chip 21, wherein the first dummy bump 211 and the second dummy bump 221 are insulated from the connection circuit inside the chip.
As shown in fig. 9, the filling material layer 130 is filled between the chip and the package substrate 40, so that the stress can be redistributed, and the package stress damage can be reduced.
In this embodiment, since the dummy pad 103 spans the first chip bonding region 121 and the second chip bonding region 122 and connects the two non-contact regions, the structure of the dummy pad 103 functions as a stiffener for the package substrate 40, and the dummy pad 103 reinforces the structural strength of the package substrate 40, so that the package substrate 40 can be effectively prevented from being broken due to bending stress.
Since the two sides of the dummy pad 103 are respectively bonded to the first dummy bump 211 and the second dummy bump 221, as shown in fig. 3, by the connection between the first dummy bump 211 and the first chip 21 and the connection between the second dummy bump 221 and the second chip 22, the reinforcing structure formed by the dummy pad 103 and the first dummy bump 211 and the second dummy bump 221 can provide a pair of tensile forces (M1 and M1') for the package substrate 40 by the chip structure via the dummy bumps when the package substrate 40 generates bending stress, thereby further preventing the package substrate 40 from breaking due to bending stress, and the reinforcing column formed by the dummy pad 103 and the first dummy bump 211 can effectively prevent the filler material layer 130 from cracking due to bending stress.
Since the filling material layer 130 can redistribute stress, it should be noted that, as shown in fig. 2, the filling material layer 130 shrinks when heated and expands when cooled, and the filling material layer filled between the chips brings great stress to the chips in a direction perpendicular to the surface of the package substrate 40, so that cracks appear in flip-chip bonding points of the chips at edge positions; as shown in fig. 4, the reinforcing columns formed by the dummy pads 103 and the first dummy bumps 211 can generate a pulling force (M2 and M2') for pulling the chip and the package substrate 40 together when the filler material layer 130 expands, prevent the solder joints from breaking, and can be supported between the chip and the package substrate 40 when the filler material layer 130 contracts.
In some embodiments, the package substrate 40 employs an interposer, which may be a glass interposer or a silicon interposer, and is provided with a plurality of through holes and metal wire layers, and may also be provided with a redistribution layer; the via hole, the metal line layer, and the rewiring layer collectively serve as a connection line of the package substrate 40 and are insulated from the dummy pad 103.
In some embodiments, as illustrated in fig. 6, a plurality of dummy pads 103 are disposed in an area adjacent to two chips, and a plurality of first dummy bumps 211 may be disposed on the first chip 21 and a plurality of second dummy bumps 221 may be disposed on the second chip 22, wherein one dummy pad 103 may be connected to only one first dummy bump 211 (second dummy bump 221) or may be connected to two or more first dummy bumps 211 (second dummy bumps 221).
In some embodiments, as shown in fig. 6, the dummy pads are not necessarily provided between all adjacent chips (e.g., between the second chip bonding region 122 and the sixth chip bonding region 126 shown in fig. 6) due to design effects such as circuit capacitance, electromagnetic shielding, etc. within the package.
In some embodiments, as shown in fig. 6, when there are 3 chips adjacent to each other, the dummy pads 10 located at the middle of the 3 chips cross three chip bonding regions (such as the first chip bonding region 121, the second chip bonding region 122, and the fifth chip bonding region 125 shown in fig. 6) and are connected to the dummy bumps in the three chip bonding regions.
In some embodiments, as shown in fig. 6, when 4 chips are adjacent, the dummy pads located at the middle positions of the 4 chips cross the four chip bonding regions (the seventh chip bonding region 127, the fourth chip bonding region 124, the sixth chip bonding region 126, the eighth chip bonding region 128, respectively) and are connected with the dummy bumps in the four chip bonding regions.
In some embodiments, as shown in fig. 21, the semiconductor package structure 10 further includes a plastic layer 140 made of materials including, but not limited to, polyimide, silicone, and epoxy, wherein the plastic layer 140 is formed on the first surface, and an upper surface of the plastic layer is at least flush with an upper surface of one of the chips.
In some embodiments, the dummy pads and dummy bumps are made of a material including at least one of the following metallic materials: such as aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), gold (Au), tin (Sn), and silver (Ag).
Example two
The present embodiment provides a method for manufacturing a semiconductor package 10 according to embodiment one, as shown in fig. 5, the method for manufacturing a semiconductor package 10 includes: step S1) to step S4). Specifically, the method further comprises the steps S5) to S6).
Step S1): as shown in fig. 7, an intermediate structure 30 is provided, the intermediate structure 30 includes a first temporary carrier 120 and a package substrate 40 disposed on an upper surface of the first temporary carrier, the package substrate 40 includes a first surface and a second surface opposite to the first surface, the first surface defines a first chip bonding region 121 and a second chip bonding region 122, a first gap exists between two regions adjacent to the first chip bonding region 121 and the second chip bonding region 122, at least one dummy pad 103 is further disposed on the first surface, and the dummy pad 103 spans across the first gap and covers a portion of the first chip bonding region 121 and a portion of the second chip bonding region 122.
In this embodiment, the first temporary carrier 120 may be a glass carrier, a ceramic carrier, or the like, and an adhesive material layer is disposed between the first temporary carrier 120 and the package substrate 40 to fix the package substrate on the first temporary carrier 120.
Specifically, when the package substrate 40 adopts an Interposer, the method for preparing the intermediate structure 30 is shown in fig. 10, and includes steps S11) to S17).
Step S11), as shown in fig. 11, a substrate 100 is provided, wherein a blind hole 101 is formed in the substrate 100, and a metal pillar is filled in the blind hole 101.
In this embodiment, the substrate 100 is, for example, a silicon wafer, but not limited thereto, and may be a germanium wafer, a germanium-silicon wafer, an SOI wafer, or the like; the blind hole 101 may be formed by a deep silicon etching process; it should be noted that, the blind hole 101 in this embodiment refers to a through hole structure formed by electroplating or electroless plating process after the copper pillar in the blind hole is formed; in addition, the sidewall of the blind via 101 should be further formed with a sidewall insulating layer, a barrier layer and a seed layer, which are not shown in the figure for simplicity of illustration, but only the copper pillar in the blind via 101 is shown.
Step S12), as shown in fig. 12, a bonding pad 102 and the dummy pad 103 are formed on the upper surface of the substrate 100, wherein the dummy pad 103 is electrically isolated from the bonding pad 102.
In this embodiment, the bonding pad 102 is electrically connected to the blind via 101, and the dummy pad 103 is electrically insulated from the blind via 101; when the bonding pad 102 is formed, a metal transition layer is formed on the upper surface of the substrate 100 by adopting a sputtering process, then a photoresist layer with an opening pattern is formed on the upper surface of the metal transition layer, then the bonding pad is formed by adopting a chemical plating or electroplating mode for growth, and finally the photoresist layer and the metal transition layer which is not covered by the bonding pad are removed by adopting an etching mode.
Step S13), as shown in fig. 13, a second temporary carrier plate 110 is provided, and the upper surface of the substrate 100 is fixed on the second temporary carrier plate 110, so as to prevent the substrate 100 from being broken and warped in the subsequent process.
Step S14), as shown in fig. 14, the lower surface of the substrate 100 is thinned until the metal posts are exposed.
In this embodiment, the lower surface of the substrate 100 is thinned by a thinning process until the copper pillars of the blind holes are exposed, wherein during thinning, rough grinding processing may be performed first, and then fine grinding processing may be performed, so as to obtain a surface with good flatness.
Step S15), as shown in fig. 15, a conductive bump 104 is formed on the lower surface of the substrate 100, so as to obtain the package substrate, where the conductive bump 104 is connected to the metal pillar.
In this embodiment, the conductive bump 104 is electrically connected with the blind hole 101; it should be noted that, in some embodiments, a redistribution layer (not shown) is further formed on the lower surface of the substrate 100 for interlayer interconnection, and at this time, the conductive bump 104 is formed on the redistribution layer and connected to the blind via 101 through the redistribution layer.
Step S16), as shown in fig. 16, the first temporary carrier 120 is provided, and the lower surface of the substrate 100 is fixed on the first temporary carrier 120, so as to prevent the substrate 100 from being broken or warped in the subsequent process.
Step S17), as shown in fig. 17, the second temporary carrier plate 110 is removed, so as to obtain the intermediate structure 30.
In this embodiment, firstly, the adhesion of the adhesive material layer between the second temporary carrier 110 and the upper surface of the substrate 100 may be reduced by heating and/or illumination, the second temporary carrier 110 is removed, and then, the adhesive material layer may be peeled off by a treatment method such as tearing, illumination, etc.; of course, the second temporary carrier plate 110 and the substrate 100 may be peeled off from each other directly by a laser peeling process, and the bonding material layer may be gasified directly by the laser peeling process, so that the processing precision is high and the remaining impurities are small.
Step S2), providing a first chip 21 and a second chip 22, wherein at least one first dummy bump 211 is disposed at a first position of an active surface of the first chip 21, and at least one second dummy bump 221 is disposed at a second position of the active surface of the second chip 22; the first position is a position of the first chip active surface corresponding to the dummy pad in the first chip bonding region covering portion, and the second position is a position of the second chip active surface corresponding to the dummy pad in the second chip bonding region covering portion.
In this embodiment, the first chip 21 and the second chip 22 are both provided with micro bumps 210, the micro bumps 210 are connected with the connection lines inside the chip, and dummy bumps (first dummy bumps 211 and second dummy bumps 221 respectively) are preset, and the dummy bumps are insulated from the connection lines inside the chip.
Step S3), as shown in fig. 18, the first chip 21 is bonded to the package substrate 40 in the first chip bonding region 121, the second chip 22 is bonded to the package substrate 40 in the second chip bonding region 122, and the first dummy bump and the second dummy bump are bonded to the dummy pad.
In this embodiment, as shown in fig. 18, the micro bump 210 is bonded to the bonding pad 102 in the chip bonding region, the dummy bumps (211 and 221) are bonded to the dummy pad 103, and after bonding the dummy pads and the dummy bumps that are disposed across the adjacent chip bonding region, the interposer can be effectively prevented from cracking, the subsequently formed filling material layer can be prevented from cracking, and the connection between the micro bump 210 and the bonding pad 102 can be prevented from breaking.
Step S4), as shown in fig. 19, a filling material layer 130 is filled in the gap between the first chip 21 and the second chip 22 and the package substrate 40.
In the present embodiment, the filling method of the filling material layer 130 includes, but is not limited to, capillary underfill, and the material of the filling material layer 130 includes, but is not limited to, epoxy. The filling is arranged between the chip and the package substrate 40, so that the stress can be redistributed, and the effect of reducing package stress damage is achieved.
Step S5), as shown in fig. 20, a plastic layer 140 is formed on the first surface, and the plastic layer 140 encapsulates the first chip 21 and the second chip 22.
In this embodiment, the method of forming the plastic layer 140 includes, but is not limited to, compression molding, liquid sealing, vacuum lamination and spin coating, and the materials include, but are not limited to, polyimide, silicone and epoxy. After forming the molding layer 140, the molding layer 140 is thinned by, for example, a grinding process (backside grinding) and CMP (chemical mechanical polishing) until the upper surface of one of the chips is exposed, according to design requirements.
Step S6), as shown in fig. 21, the first temporary carrier plate 120 is removed.
In this embodiment, the semiconductor package structure 10 is prepared by removing the first temporary carrier 120 in the same manner as in step S17).
In summary, according to the semiconductor package structure and the method for manufacturing the same, the dummy bumps are respectively disposed in two adjacent chips, the dummy pads are correspondingly disposed on the package substrate, the dummy bumps are insulated from the circuits in the chips, the dummy pads are insulated from the circuits in the package substrate, and after the chips are bonded and connected with the package substrate, the dummy pads are also bonded and connected with the dummy bumps respectively, so as to form a structure reinforcing bridge crossing under the two chips, and the structure reinforcing bridge connects the two adjacent chips, so that the bottom filling layer can be effectively prevented from cracking due to shrinkage and expansion, and the problems of layering, electromagnetic shielding failure, circuit interruption and the like of the package structure can be further prevented.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor package structure, the semiconductor package structure comprising:
the packaging substrate comprises a first surface and a second surface opposite to the first surface, wherein the first surface is defined with a first chip welding area and a second chip welding area, the first chip welding area is adjacent to the second chip welding area and has a first gap, the first surface is also provided with at least one dummy bonding pad, and the dummy bonding pad spans the first gap and covers part of the surfaces of the first chip welding area and the second chip welding area;
the semiconductor device comprises a first chip and a second chip, wherein at least one first dummy bump is arranged at a first position of an active surface of the first chip, and at least one second dummy bump is arranged at a second position of the active surface of the second chip; the first position is a position corresponding to the dummy pad in the first chip active surface at the first chip bonding region covering part, the second position is a position corresponding to the dummy pad in the second chip active surface at the second chip bonding region covering part, and the first dummy bump and the second dummy bump are connected with the dummy pad in a bonding manner;
and the filling material layer is filled in gaps among the packaging substrate, the first chip and the second chip.
2. The semiconductor package according to claim 1, wherein the semiconductor package further comprises a third chip; the first surface is also defined with a third chip welding area;
the third chip welding area is adjacent to the second chip welding area and has a second gap;
at least one of the dummy pads also spans the second gap and covers a portion of a surface of the second die bonding region and the third die bonding region;
at least one third dummy bump is disposed at a third position of the third chip active surface, where the third position is a position of the third chip active surface corresponding to a covering portion of the dummy pad in the third chip bonding area, and the second dummy bump and the third dummy bump are bonded and connected with the dummy pad.
3. The semiconductor package according to claim 2, wherein the first, second and third die bonding regions are adjacent to each other;
one of the dummy pads covers part of the surfaces of the first chip bonding region, the second chip bonding region and the third chip bonding region at the same time;
the first dummy bump, the second dummy bump, and the third dummy bump are bonded to the dummy pad.
4. The semiconductor package according to any one of claims 1 to 3, further comprising:
and the plastic sealing layer is formed on the first surface and coats each chip.
5. The semiconductor package according to claim 1, wherein the package substrate includes an interposer formed with a via, the dummy pad being insulated from the via.
6. The semiconductor package according to claim 1, wherein the package substrate includes an interposer formed with a via and a redistribution layer, the dummy pad being insulated from the via and the redistribution layer.
7. A method of manufacturing a semiconductor package, the method comprising:
providing an intermediate structure, wherein the intermediate structure comprises a first temporary carrier plate and a packaging substrate positioned on the upper surface of the first temporary carrier plate, the packaging substrate comprises a first surface and a second surface opposite to the first surface, the first surface is defined with a first chip welding area and a second chip welding area, the first chip welding area is adjacent to the second chip welding area and has a first gap, the first surface is also provided with at least one dummy bonding pad, and the dummy bonding pad spans the first gap and covers part of the surfaces of the first chip welding area and part of the surfaces of the second chip welding area;
providing a first chip and a second chip, wherein at least one first dummy bump is arranged at a first position of an active surface of the first chip, and at least one second dummy bump is arranged at a second position of the active surface of the second chip; the first position is a position of the first chip active surface corresponding to the covering part of the dummy pad in the first chip welding area, and the second position is a position of the second chip active surface corresponding to the covering part of the dummy pad in the second chip welding area;
bonding the first chip to the package substrate in the first chip bonding region, bonding the second chip to the package substrate in the second chip bonding region, and bonding the first dummy bump and the second dummy bump to the dummy pad;
filling a filling material layer into gaps between the first chip and the second chip which are connected with the packaging substrate in a bonding way.
8. The method of manufacturing a semiconductor package according to claim 7, wherein after filling the filling material layer, the method further comprises:
forming a plastic sealing layer on the first surface, wherein the plastic sealing layer wraps the first chip and the second chip;
and removing the first temporary carrier plate.
9. The method of manufacturing a semiconductor package according to claim 7, wherein the method of manufacturing an intermediate structure comprises:
providing a substrate, wherein a blind hole is formed in the substrate, and a metal column is filled in the blind hole;
forming a bonding pad and the dummy pad on the upper surface of the substrate, wherein the bonding pad is connected with the metal column, and the dummy pad is electrically isolated from the bonding pad;
providing a second temporary carrier plate, and fixing the upper surface of the substrate on the second temporary carrier plate;
thinning the lower surface of the substrate until the metal posts are exposed;
forming a conductive bump on the lower surface of the substrate, wherein the conductive bump is connected with the metal column;
providing the first temporary carrier plate, and fixing the lower surface of the substrate on the first temporary carrier plate;
and removing the second temporary carrier plate.
10. The method of claim 9, wherein the method of fabricating the intermediate structure further comprises the step of forming a redistribution layer on the lower surface of the substrate after the lower surface of the substrate is thinned and before the conductive bump is formed on the lower surface of the substrate, wherein the redistribution layer is connected to the conductive bump.
CN202310540373.7A 2023-05-12 2023-05-12 Semiconductor packaging structure and preparation method thereof Pending CN116364560A (en)

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Application Number Priority Date Filing Date Title
CN202310540373.7A CN116364560A (en) 2023-05-12 2023-05-12 Semiconductor packaging structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310540373.7A CN116364560A (en) 2023-05-12 2023-05-12 Semiconductor packaging structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116364560A true CN116364560A (en) 2023-06-30

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