CN116364149A - Semiconductor structure and memory - Google Patents
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- CN116364149A CN116364149A CN202310354331.4A CN202310354331A CN116364149A CN 116364149 A CN116364149 A CN 116364149A CN 202310354331 A CN202310354331 A CN 202310354331A CN 116364149 A CN116364149 A CN 116364149A
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- 239000003990 capacitor Substances 0.000 claims description 8
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the disclosure provides a semiconductor structure and a memory, wherein the semiconductor structure comprises N memory array sheets and N-1 sense amplifier modules; for the 1 st and N th memory array chips, a first part of memory cells thereof are electrically connected to sense amplifier modules adjacent thereto; the second part of the memory cells are electrically connected to the first part of the memory cells; on the other hand, the 1 st and nth memory array tiles each include a plurality of twin sub-cells including two memory cells storing the same data, the twin sub-cells simultaneously performing reading and writing of data through sense amplifiers corresponding thereto. Thus, the chip area can be reduced and the integration level can be improved by adopting the embodiment of the disclosure.
Description
Cross Reference to Related Applications
The present disclosure claims priority from the chinese patent office, application number 202211336945.1, application name "a semiconductor structure and memory," filed on day 28, 10, 2022, the entire contents of which are incorporated herein by reference.
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor structure and a memory.
Background
With the development of semiconductor technology, the integration level of the memory is required to be higher and the performance standard is higher. Therefore, further optimization of the structure of the memory is required to improve the integration level.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a semiconductor structure and a memory, which can avoid the waste of memory cells and improve the integration level.
The technical scheme of the invention is realized as follows:
embodiments of the present disclosure provide a semiconductor structure including: n memory array chips and N-1 sense amplifier modules; the N storage array sheets are sequentially arranged along a first direction; 1 sense amplifier module is arranged between every 2 adjacent memory array chips; each of the memory array tiles includes: a plurality of memory cells, a plurality of first bit lines, and a plurality of second bit lines; wherein, for the 2 nd to N-1 st memory array chips, a first part of the memory cells in the memory array chips are electrically connected to a first side adjacent sense amplifier module through the corresponding first bit lines, and a second part of the memory cells in the memory array chips are electrically connected to a second side adjacent sense amplifier module through the corresponding second bit lines; for the 1 st and the N th memory array chips, a first part of the memory cells in the memory array chips are electrically connected to adjacent sense amplifier modules through the corresponding first bit lines; a second portion of the memory cells in the memory array die are electrically connected to the corresponding first bit lines through the corresponding second bit lines to connect to adjacent ones of the sense amplifier modules.
In the above scheme, among the N memory array slices, the 1 st memory array slice and the N memory array slice occupy the same area, and the 2 nd to N-1 memory array slices occupy the same area; the area occupied by any one of the 1 st memory array chip and the N-th memory array chip is half the area occupied by any one of the 2 nd to N-1 st memory array chips.
In the above scheme, the lengths of the N storage array slices along the second direction are equal; the second direction intersects the first direction; the length of any one of the 1 st memory array chip and the nth memory array chip along the first direction is half of the length of any one of the 2 nd to N-1 st memory array chips along the first direction.
In the above scheme, the first bit line and the second bit line are sequentially arranged in a crossing manner along the second direction; for the 1 st and the N th memory array chips, 1 first bit line is correspondingly connected with 1 second bit line adjacent to the 1 first bit line, and the sum of the lengths of the 1 first bit line and the 1 second bit line with a connection relationship is a first value; for the 2 nd to N-1 th memory array chips, the length of each first bit line is the first value, and the length of each second bit line is the first value.
In the above aspect, the semiconductor structure further includes: a plurality of first contact structures; the first contact structure extends along a second direction; for the 1 st memory array chip and the N th memory array chip, 1 first bit line and 1 second bit line are connected with each other through the first contact structure, and the sum of the delays of the 1 first bit line, the 1 second bit line and the 1 first contact structure with a connection relationship is a second value; for the 2 nd to N-1 th memory array chips, the delay of the first bit line is the second value, and the delay of the second bit line is the second value.
In the above aspect, the semiconductor structure further includes: a plurality of second wires and a plurality of second contact structures; the second wire extends along a second direction; for the 1 st and the N-th memory array chips, 1 first bit line is connected to 1 second wire through 1 second contact structure, and 1 second bit line is connected to the same second wire through another second contact structure, so as to realize the interconnection of 1 first bit line and 1 second bit line.
In the above scheme, for the 1 st memory array chip and the nth memory array chip, the sum of the delays of the 1 first bit line, the 2 second contact structures, the 1 second conductive line and the 1 second bit line having a connection relationship is a third value; for the 2 nd to N-1 th memory array chips, the delay of the first bit line is the third value, and the delay of the second bit line is the third value.
In the above solution, each of the sense amplifier modules includes: a plurality of sense amplifiers; each of the memory cells is correspondingly electrically connected to the sense amplifier in the sense amplifier module; for the 2 nd to N-2 nd sense amplifier modules, the first end and the second end of the sense amplifier are respectively and electrically connected with the storage units with the same quantity; for the 1 st and N-1 st sense amplifier modules, the number of the memory cells electrically connected to the first terminal of the sense amplifier is 2 times the number of the memory cells electrically connected to the second terminal of the sense amplifier.
Embodiments of the present disclosure also provide another semiconductor structure, the semiconductor structure including: n storage array sheets and N-1 sense amplifier modules, wherein the N storage array sheets are sequentially arranged along a first direction, 1 sense amplifier module is arranged between every 2 adjacent storage array sheets, and each sense amplifier module comprises a plurality of sense amplifiers; each of the 2 nd to N-1 th memory array tiles includes a plurality of memory cells that perform reading and writing of data through sense amplifiers corresponding thereto; the 1 st and nth memory array tiles each include a plurality of twin sub-cells including two of the memory cells storing the same data, the twin sub-cells simultaneously performing reading and writing of data through sense amplifiers corresponding thereto.
In the above scheme, in each memory array sheet, a plurality of memory cells are arranged in an array, a row direction of the array is a first direction, a column direction of the array is a second direction, and the second direction intersects with the first direction; for the 1 st and the N th memory array chip, the two memory cells of the double sub-cells are located in the same column, and the two memory cells of the double sub-cells are located in two adjacent rows.
In the above scheme, each memory array slice further includes a plurality of word lines and a plurality of bit lines, the memory cell includes a switching tube and a capacitor, a gate of the switching tube is connected to a word line, a first end of the switching tube is connected to the capacitor, and a second end of the switching tube is connected to a bit line; in the 1 st and nth memory array chips, the two memory cells included in the dual sub-cell are coupled to the same word line.
In the above scheme, the plurality of bit lines in the memory array slice include a plurality of first bit lines and a plurality of second bit lines, and the second end of the switch tube is connected with one of the first bit lines or the second bit lines; in the memory array chip, the first bit lines and the second bit lines are alternately arranged along the second direction; for the 2 nd to N-2 nd sense amplifier modules, a first end of 1 sense amplifier is connected with 1 first bit line of the adjacent memory array slice, and a second end of 1 sense amplifier is connected with 1 second bit line of the other adjacent memory array slice; for the 1 st sense amplifier module, a first end of the 1 st sense amplifier is connected with 1 first bit line and 1 second bit line of the 1 st memory array chip, and a second end of the sense amplifier is connected with 1 second bit line of the 2 nd memory array chip; for the N-1 sense amplifier module, a first end of the sense amplifier is connected with 1 first bit line of the N-1 memory array chip, and a second end of the sense amplifier is connected with 1 first bit line and 1 second bit line of the N memory array chip.
The embodiment of the disclosure also provides a memory, which comprises the semiconductor structure in the scheme.
In the above scheme, the memory is a DRAM.
Therefore, the embodiment of the disclosure provides a semiconductor structure and a memory, which can reduce the number of memory cells of a memory array slice at the edge to half the number of memory cells of other memory array slices under the condition that the sense amplifier module can work normally, so that the area of the memory array slice at the edge is reduced to half the area of other memory array slices, thereby reducing the area of a chip and improving the integration level.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram III of a semiconductor structure according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure;
fig. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;
Fig. 7 is a schematic structural diagram seven of a semiconductor structure according to an embodiment of the disclosure;
fig. 8 is a schematic structural diagram eight of a semiconductor structure according to an embodiment of the disclosure;
fig. 9 is a schematic structural diagram nine of a semiconductor structure provided in an embodiment of the disclosure;
fig. 10 is a schematic structural diagram of a memory according to an embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
In the related art, in order to ensure that two bit lines connected to the sense amplifier are symmetrical to each other, a complete memory Array chip (MAT) needs to be placed at each edge position of the Array region (Array). Therefore, part of memory cells in the memory array slice at the edge position can be in a non-use state, thereby causing the waste of the memory cells and being unfavorable for improving the chip integration level.
Fig. 1 is an alternative schematic view of a semiconductor structure 80 provided by an embodiment of the present disclosure, as shown in fig. 1, the semiconductor structure 80 includes: n memory array tiles 10 and N-1 sense amplifier modules 20. The N memory array chips 10 are sequentially arranged along the first direction X; each sense amplifier module 20 is disposed between every two adjacent memory array chips 10 (or, 1 sense amplifier module 20 is disposed between every 2 adjacent memory array chips 10); each memory array tile 10 includes: a plurality of memory cells; wherein, for the 2 nd to N-1 st memory array chip 10, its memory cells are electrically connected to the sense amplifier modules 20 adjacent thereto; for the 1 st memory array tile 10 and the nth memory array tile 10, a first portion of the memory cells thereof are electrically connected to the sense amplifier modules 20 adjacent thereto, and a second portion of the memory cells thereof are electrically connected to the sense amplifier modules 20 adjacent thereto by being electrically connected to the first portion of the memory cells thereof.
Note that, each memory array tile further includes a plurality of bit lines 30, and in order to more clearly show the contents of the drawings, the memory cells are omitted in fig. 1, and only the plurality of bit lines 30 (extending in the first direction X in fig. 1) in each memory array tile 10 are used to represent the connection relationship of the memory cells instead. That is, in each memory array tile 10, the memory cells are electrically connected to the corresponding sense amplifier modules 20 through the bit lines 30.
In the embodiments of the present disclosure, referring to fig. 1, since memory cells are arranged along bit lines 30 in a memory array chip 10, the longer the bit lines 30, the more memory cells are connected. The length of the bit line 30 is determined by the length of the memory array 10 along the first direction X.
With continued reference to fig. 1, for the 2 nd to N-1 st memory array die 10, its memory cells are electrically connected to their adjacent sense amp modules 20 by bit lines 30. Note that, in fig. 1, the 4 th to N-2 th memory array chips 10 are omitted; the structure and electrical connection relationship of the 4 th to N-2 th memory array chips 10 may be referred to as the structure and electrical connection relationship of the 3 rd memory array chip 10.
With continued reference to FIG. 1, a portion of the bit lines 30 in the 1 st memory array tile 10 are electrically connected to the 1 st sense amp module 20 (located between the 1 st and 2 nd memory array tiles 10). That is, for the 1 st memory array chip 10, the first portion of the memory cells thereof are electrically connected to the 1 st sense amplifier module 20 adjacent thereto. Another portion of the bit lines 30 in the 1 st memory array tile 10 is electrically connected to a portion of the bit lines 30 in the 1 st memory array tile 10 (which portion of the bit lines are electrically connected to the 1 st sense amp module 20 adjacent thereto) and is further electrically connected to the 1 st sense amp module 20 (located between the 1 st and 2 nd memory array tiles 10). That is, for the 1 st memory array chip 10, the second partial memory cells thereof are electrically connected to the 1 st sense amplifier module 20 adjacent thereto by being electrically connected to the first partial memory cells thereof.
Accordingly, a portion of the bit lines 30 in the nth memory array die 10 are electrically connected to the nth-1 sense amplifier module 20 (located between the nth and nth-1 memory array die 10). That is, for the nth memory array chip 10, a first portion of the memory cells thereof are electrically connected to the nth-1 sense amplifier module 20 adjacent thereto. Another portion of the bit lines 30 in the nth memory array tile 10 is electrically connected to a portion of the bit lines 30 in the nth memory array tile 10 (which portion of the bit lines are electrically connected to the 1 st sense amplifier module 20 adjacent thereto) and further electrically connected to the N-1 st sense amplifier module 20 (located between the nth and N-1 th memory array tiles 10). That is, for the nth memory array chip 10, the second portion of the memory cells thereof are electrically connected to the N-1 th sense amplifier module 20 adjacent thereto by being electrically connected to the first portion of the memory cells thereof.
That is, for the 1 st and nth memory array chips 10, the bit lines to which the second partial memory cells thereof are connected to the bit lines to which the first partial memory cells thereof are connected; thus, the first and second partial memory cells of the memory array chip (1 st and nth memory array chips 10) located at the edge are connected to the same sense amplifier module 20 adjacent thereto.
In the embodiments of the present disclosure, for the 2 nd to N-1 st memory array chips, the memory cells thereof are electrically connected to the sense amplifier modules adjacent thereto; for the 1 st and N th memory array chips, a first part of memory cells thereof are electrically connected to sense amplifier modules adjacent thereto; the second portion of the memory cells are electrically connected to the first portion of the memory cells. In this way, the first part of memory cells and the second part of memory cells of the memory array slice positioned at the edge are connected to the same sense amplification module adjacent to the first part of memory cells through bit lines, so that the waste of the memory cells is avoided. Meanwhile, the number of the storage units of the storage array slices positioned at the edge is reduced to half of the number of the storage units of other storage array slices, so that the area of the storage array slices positioned at the edge is reduced to half of the area of the other storage array slices, and the storage array slices are still in an optimal working state; therefore, the area of the chip can be reduced, and the integration level can be improved.
Fig. 2 shows a plurality of memory cells 100 included in any one of the 2 nd to N-1 st memory array tiles 10, as shown in fig. 2, a plurality of bit lines bl_0 to bl_i and a plurality of word lines wl_0 to wl_j are included in any one of the 2 nd to N-1 st memory array tile 10, and a plurality of memory cells 100 are also included in the memory array tile 10. Each memory cell 100 is located at the intersection of a bit line and a word line, and is electrically connected to the bit line and the word line, respectively. Specifically, the memory cell 100 includes a switching transistor and a capacitor, where a gate of the switching transistor is connected to a word line, a first end of the switching transistor is connected to the capacitor, and a second end of the switching transistor is connected to a bit line.
Referring to fig. 1 and 2, a plurality of memory cells 100 of any one of the 2 nd to N-1 st memory array chips 10 are electrically connected to two different sense amplifier modules through a plurality of bit lines in the memory array chip 10, respectively. If the plurality of bit lines 30 are divided into the first bit lines and the second bit lines, for example, bit lines marked with an odd number among the plurality of bit lines bl_0 to bl_i shown in fig. 2 are used as the first bit lines, and bit lines marked with an even number are used as the second bit lines. Then:
for the 2 nd to N-1 th memory array tiles 10, a first portion of memory cells in the memory array tile 10 are electrically connected to the first side adjacent sense amplifier module 20 through corresponding first bit lines, and a second portion of memory cells in the memory array tile 10 are electrically connected to the second side adjacent sense amplifier module 20 through corresponding second bit lines; for example, for the 2 nd memory array tile 10, a first portion of its memory cells 100 are electrically connected to the 1 st sense amp module via a first bit line, and a second portion of its memory cells are electrically connected to the 2 nd sense amp module 20 (between the 2 nd and 3 rd memory array tiles 10) via a second bit line.
Fig. 3 shows a plurality of memory cells 100 included in any one of the 1 st memory array tile 10 and the nth memory array tile 10, as shown in fig. 3, a plurality of bit lines bl_0 to bl_m and a plurality of word lines wl_0 to wl_n are included in any one of the 1 st memory array tile 10 and the nth memory array tile 10, and a plurality of memory cells 100 are also included in the memory array tile 10. Each memory cell 100 is located at the intersection of a bit line and a word line, and is electrically connected to the bit line and the word line, respectively.
Referring to fig. 1 and 3, a plurality of memory cells 100 of any one of the 1 st memory array chip 10 and the nth memory array chip 10 are electrically connected to a sense amplifier module adjacent thereto through a plurality of bit lines in the memory array chip 10. If the plurality of bit lines are divided into the first bit line and the second bit line, for example, the bit line with the odd number among the plurality of bit lines bl_0 to bl_m shown in fig. 3 is used as the first bit line, and the bit line with the even number is used as the second bit line. Then, for the 1 st and nth memory array chips 10, a first portion of the memory cells in the memory array chip 10 are electrically connected to adjacent sense amp modules 20 through corresponding first bit lines; a second portion of the memory cells in the memory array slice are electrically connected to corresponding first bit lines by corresponding second bit lines to connect to adjacent sense amp modules 20. For example, for the 1 st memory array tile 10, a first portion of the memory cells 100 thereof are electrically connected to the 1 st sense amp module 20 via a first bit line, and a second portion of the memory cells thereof are connected to the first bit line via a second bit line, and are in turn electrically connected to the 1 st sense amp module 20 (between the 1 st and 2 nd memory array tiles 10).
In the following description, when the first bit line or the second bit line is not specified, the "bit line" may refer to either one of the first bit line or the second bit line.
In some embodiments of the present disclosure, referring to fig. 1, the 1 st memory array tile 10 and the N-th memory array tile 10 occupy the same area, and the 2 nd to N-1 st memory array tile 10 occupy the same area.
In the embodiment of the present disclosure, referring to fig. 1, the lengths of the n memory array sheets 10 in the second direction Y may be set to be substantially equal; the second direction Y intersects the first direction X. Further, the lengths of the 1 st memory array chip 10 and the nth memory array chip 10 in the first direction X may be set to be equal so that the 1 st memory array chip 10 and the nth memory array chip 10 occupy the same area. Meanwhile, the lengths of the 2 nd to N-1 st memory array chips 10 in the first direction X may be set to be equal so that the 2 nd to N-1 st memory array chips 10 occupy the same area.
The area occupied by one memory array chip 10 is determined by the number of memory cells included in the memory array chip 10, that is, the larger the number of memory cells included in one memory array chip 10, the larger the area occupied by the memory array chip 10.
It should be understood that the 1 st memory array tile 10 and the nth memory array tile 10 occupy equal areas, where "equal areas" may be substantially equal areas; that is, the 1 st memory array chip 10 and the nth memory array chip 10 include a substantially equal number of memory cells. The reason for this being approximately equal is: it is also possible that a memory array tile may include a number of space cells (Dummy cells) and redundant cells (redundancy cells), which may depend on the actual design, so that the number of cells in the 1 st memory array tile 10 and the nth memory array tile 10 may not be exactly the same, and similarly, the following lengths equal and a length ratio of 1:2 may be referred to as being approximately.
The 2 nd to N-1 st memory array tiles 10 occupy equal (or substantially equal) areas, meaning that the 2 nd to N-1 st memory array tiles 10 contain substantially equal numbers of memory cells.
In some embodiments of the present disclosure, referring to fig. 1, the area occupied by any one of the 1 st memory array tile 10 and the N-th memory array tile 10 is half the area occupied by any one of the 2 nd to N-1 st memory array tiles 10.
In the embodiment of the present disclosure, referring to fig. 1, n memory array sheets 10 have equal lengths along the second direction Y; the second direction Y intersects the first direction X, and fig. 1 illustrates the second direction Y perpendicular to the first direction X as an example, but this does not constitute a related limitation. Further, the length of any one of the 1 st memory array chip 10 and the N-th memory array chip 10 in the first direction X is half the length of any one of the 2 nd to N-1 st memory array chips 10 in the first direction X.
Further, since the area occupied by one memory array chip 10 is determined by the number of memory cells included in the memory array chip 10, the number of memory cells included in any one of the 1 st memory array chip 10 and the N-th memory array chip 10 is approximately half the number of memory cells included in any one of the 2 nd to N-1 st memory array chips 10.
Fig. 4 is a partial schematic view of a semiconductor structure, semiconductor structure 80 comprising: a plurality of memory array dice 10 and a plurality of sense amplifier modules 20.
In some embodiments, referring to fig. 4, the first bit line 31 and the second bit line 32 are sequentially disposed to cross in the second direction Y. That is, the first partial memory cells and the second partial memory cells are disposed at intervals from each other in the second direction Y. In other embodiments, the first bit line 31 and the second bit line 32 may have other arrangements, which are not limited herein.
It should be noted that fig. 4 only shows an alternative arrangement of the first bit line 31 and the second bit line 32, so as to illustrate the bit line connection relationship between the memory array chips 10. Fig. 4 shows only the 1 st, 2 nd, 3 rd, N-1 st and N-1 st memory array die 10 and the 1 st, 2 nd, N-2 nd and N-1 st sense amplifier modules 20 connected thereto. The remainder of semiconductor structure 80 may be understood with reference to fig. 4, for example, the 3 rd to N-1 th memory array dice 10 may be referenced to the 2 nd memory array dice 10.
In some embodiments of the present disclosure, referring to fig. 4, semiconductor structure 80 further comprises: a plurality of first wires. In each memory array tile 10, the bit lines 30 include: a first bit line 31 and a second bit line 32. For the 2 nd to N-1 th memory array chips, a first portion of the memory cells thereof are electrically connected to the sense amplifier module 20 on a first side thereof through the first bit lines 31 and the first conductive lines, and a second portion of the memory cells thereof are electrically connected to the sense amplifier module 20 on a second side thereof through the second bit lines 32 and the first conductive lines; for the 1 st and nth memory array chips, a first portion of memory cells thereof is electrically connected to a sense amplifier module adjacent thereto through a first bit line 31 and a first conductive line, and a second portion of memory cells thereof is electrically connected to a first portion of memory cells thereof through a second bit line 32.
In fig. 4, the first conductive line is omitted, and the first conductive line is replaced by a bit line connected to the sense amplifier module; the connection manner of the first conductive line and the bit line can refer to fig. 5 and 6.
With continued reference to fig. 4, a first bit line 31 in the 1 st memory array die 10 is electrically connected to the 1 st sense amp module 20 adjacent thereto (between the 1 st and 2 nd memory array die 10). That is, for the 1 st memory array chip 10, a first portion of the memory cells thereof are electrically connected to the 1 st sense amplifier module 20 adjacent thereto through the first bit line 31 and the first conductive line. The second bit line 32 in the 1 st memory array tile 10 is electrically connected to the first bit line 31 in the 1 st memory array tile 10 and further electrically connected to the 1 st sense amp module 20. That is, for the 1 st memory array chip 10, the second portion of the memory cells thereof are electrically connected to the first portion of the memory cells thereof through the second bit lines 32.
Accordingly, the first bit line 31 in the nth memory array chip 10 is electrically connected to the nth-1 sense amplifier module 20 (located between the nth-1 and nth memory array chips 10) adjacent thereto. That is, for the nth memory array chip 10, a first portion of the memory cells thereof are electrically connected to the N-1 th sense amplifier module 20 adjacent thereto through the first bit line 31 and the first conductive line. The second bit line 32 in the nth memory array tile 10 is electrically connected to the first bit line 31 in the nth memory array tile 10 and further electrically connected to the nth-1 sense amplifier module 20 (located between the nth and nth-1 memory array tiles 10). That is, for the nth memory array chip 10, the second portion of its memory cells are electrically connected to the first portion of its memory cells by the second bit lines 32.
With continued reference to FIG. 4, a first bit line 31 in the 2 nd memory array die 10 is electrically connected to the 1 st sense amp module 20 adjacent thereto (between the 1 st and 2 nd memory array die 10); the second bit line 32 in the 2 nd memory array die 10 is electrically connected to the 2 nd sense amp module 20 adjacent thereto (between the 2 nd and 3 rd memory array die 10). That is, for the 2 nd memory array chip, a first portion of memory cells thereof is electrically connected to the sense amplifier module 20 on a first side thereof through the first bit line 31 and the first conductive line, and a second portion of memory cells thereof is electrically connected to the sense amplifier module 20 on a second side thereof through the second bit line 32 and the first conductive line.
Fig. 5 is a partial schematic view of a semiconductor structure including a plurality of memory array dice 10 and a plurality of sense amplifier modules 20, as shown in fig. 5. Fig. 5 shows only the 1 st, 2 nd, and 3 rd memory array chips 10, and the 1 st and 2 nd sense amplifier modules 20 connected thereto. The remainder of semiconductor structure 80 may be understood with reference to fig. 5, for example, the 4 th to N-1 th memory array dice 10 may be referred to the 2 nd memory array dice 10 or the 3 rd memory array dice 10; the nth memory array tile 10 may refer to the 1 st memory array tile 10.
In some embodiments of the present disclosure, referring to fig. 5, a plurality of first contact structures 41 and a plurality of third contact structures 43 are also included in the semiconductor structure. For the 1 st memory array chip 10 and for the nth memory array chip 10, a plurality of first bit lines 31 and a plurality of second bit lines 32 are included in each memory array chip 10, and the first bit lines 31 and the second bit lines 32 are electrically connected to each other through first contact structures 41. The first conductive line 51 is electrically connected to the sense amplifier module 20 through the third contact structure 43.
For the 1 st memory array chip 10, the second part of the memory cells thereof are electrically connected to the first bit line 31 in the 1 st memory array chip 10 and finally electrically connected to the 1 st sense amplifier module 20 (located between the 1 st and 2 nd memory array chips 10) through the second bit line 32 and the first contact structure 41; meanwhile, for the 1 st memory array chip 10, a first portion of the memory cells thereof are electrically connected to the 1 st sense amplifier module 20 (located between the 1 st and 2 nd memory array chips 10) through the first bit line 31 and the first conductive line 51. That is, the first and second partial memory cells of the 1 st memory array chip 10 are electrically connected to the sense amplifier module 20 adjacent to the 1 st memory array chip 10 through the first and second bit lines 31 and 32 connected to each other.
For the 2 nd memory array chip 10, a first portion of its memory cells are electrically connected to the 1 st sense amp module 20 through the first bit line 31 and the first conductive line 51. That is, the first portion of the memory cells of the 2 nd memory array die 10 are electrically connected to the 1 st sense amplifier module 20. For the 2 nd memory array die 10, a second portion of its memory cells are electrically connected to the 2 nd sense amp module 20 (located between the 2 nd and 3 rd memory array die 10) via the second bit lines 32 and the first conductive lines 51. That is, the second portion of the memory cells of the 2 nd memory array die 10 are electrically connected to the 2 nd sense amplifier module 20.
For the 3 rd memory array chip 10, a first portion of its memory cells are electrically connected to the 2 nd sense amp module 20 through the first bit line 31 and the first conductive line 51. For the 3 rd memory array chip 10, a second portion of the memory cells thereof are electrically connected to the 3 rd sense amp module 20 (located between the 3 rd and 4 th memory array chips 10) via the second bit lines 32 and the first conductive lines 51.
Fig. 6 is a left side view of the partial structure of fig. 5, and as shown in fig. 6, the first bit line 31 is electrically connected to the second bit line 32 through the first contact structure 41. Here, the top view of the first contact structure 41 may be any shape as long as it is ensured that the projection of the first contact structure 41 on the plane where the first bit line/second bit line is located intersects both the first bit line 31 and the second bit line 32.
In the embodiment of the present disclosure, for the 1 st and nth memory array chips 10,1 first bit line 31 is correspondingly connected to 1 second bit line 32 adjacent thereto, and the sum of lengths of 1 first bit line 31 and 1 second bit line 32 having a connection relationship is a first value (within an error-allowable range); for the 2 nd to N-1 st memory array chips 10, the length of each first bit line 31 is a first value, and the length of each second bit line 32 is a first value (within the tolerance range).
That is, the sum of the lengths of the first bit line 31 of each 1 st memory array tile 10 and the second bit line 32 of each 1 st memory array tile 10 is equal to the length of the bit line 30 of each 2 nd memory array tile 10; the sum of the lengths of the first bit line 31 of each nth memory array tile 10 and the second bit line 32 of each nth memory array tile 10 is equal to the length of the bit line 30 of each N-1 th memory array tile 10. Similarly, the length equality here may be a substantial length equality.
That is, (1) for the 2 nd to N-2 nd Sense amplifier modules 20, one end is connected to one memory cell through the first bit line 31 and the other end is connected to the other memory cell through the second bit line 32 when they perform Sense amplification (Sense), since the lengths of the first bit line 31 and the second bit line 32 in the 2 nd to N-1 st memory array chips 10 are substantially equal, 2 different memory cells are connected through the bit lines of the same length when the Sense amplifier modules 20 perform Sense amplification, respectively; (2) When the 1 st sense amplifier module 20 performs sense amplification, the 1 st sense amplifier module is connected to 1 st memory cell in the 1 st memory array chip 10 (actually, the 1 st sense amplifier module is also connected to another memory cell in the 1 st memory array chip 10 through the first bit line 31) after being connected in series through the 1 first bit line 31 and the 1 second bit line 32, and the 1 st sense amplifier module is connected to 1 st memory cell in the 2 nd memory array chip 10 through the first bit line 31 (or the second bit line 32); since the total length of the 1 st memory array chip 10 (the first bit line 31+the second bit line 32) =the total length of the first bit line 31 in the 2 nd memory array chip 10=the total length of the second bit line 32 in the 2 nd memory array chip 10, the sense amplifier module 20 can also realize that 2 different memory cells are connected via the bit lines with the same length when performing sense amplification, so as to ensure correct timing. The N-1 th sense amp module 20 can be similarly understood.
In the embodiment of the present disclosure, with continued reference to fig. 5, when the first bit line 31 of the 2 nd memory array chip 10 is electrically connected to the 1 st sense amplification module 20 through the first conductive line 51, the sum of the delays of the first bit line 31 of each 1 st memory array chip 10, each first contact structure 41, and the second bit line 32 of each 1 st memory array chip 10 is equal to the delay of the bit line of each 2 nd memory array chip 10; the sum of the delays of the first bit line 31 of each nth memory array tile 10, each first contact structure 41 and the second bit line 32 of each nth memory array tile 10 is approximately equal to the delay of the bit line of each N-1 th memory array tile 10. In this way, the delays of the circuits connected to the two ends of the sense amplifier module 20 can be approximately equal, so that the consistency of the time sequence of the signals transmitted by the two ends of the sense amplifier module 20 is ensured.
The sum of the lengths of the first bit line 31 of each 1 st memory array tile 10 and the second bit line 32 of each 1 st memory array tile 10 is approximately equal to the length of the bit line of each 2 nd memory array tile 10. Since the delay of the bit line is proportional to the resistance of the bit line and the length of the bit line, when the sum of the lengths of the first bit line 31 and the second bit line 32 of the 1 st memory array chip 10 is approximately equal to the length of the bit line of the 2 nd memory array chip 10, a compensation element may be added to the bit line of the 2 nd memory array chip 10 to balance the delay caused by the first contact structure 41. Thus, the sum of the delay times of the first bit line 31 of each 1 st memory array tile 10, each first contact structure 41, and the second bit line 32 of each 1 st memory array tile 10 is approximately equal to the delay time of the bit line of each 2 nd memory array tile 10. And, the sum of the resistances of the first bit line 31 of each 1 st memory array tile 10, each first contact structure 41, and the second bit line 32 of each 1 st memory array tile 10 is approximately equal to the resistance of the bit line of each 2 nd memory array tile 10. The nth and nth-1 memory array tiles 10 may be understood with reference to the 1 st and 2 nd memory array tiles 10.
That is, for the 1 st memory array chip 10 and the nth memory array chip 10, the 1 first bit line 31 and the 1 second bit line 32 are connected to each other by the first contact structure 41, and the sum of the delays of the 1 first bit line 31, the 1 second bit line 32, and the 1 first contact structure 41 having a connection relationship is the second value; for the 2 nd to N-1 st memory array chips 10, the delay of the first bit line 31 is a second value, and the delay of the second bit line 32 is a second value.
It is understood that the embodiment of the present disclosure shorts adjacent bit lines in the memory array chip 10 (i.e., the 1 st memory array chip 10 and the nth memory array chip 10) located at the edge position by two by the first contact structure 41. Thus, the waste of the memory cells is avoided, and the area of the memory array sheet 10 positioned at the edge is reduced, so that the area of the chip can be reduced, and the integration level is improved.
Fig. 7 is a partial schematic view of a semiconductor structure 80. As shown in fig. 7, the semiconductor structure 80 includes a plurality of memory array dice 10 and a plurality of sense amplifier modules 20. Fig. 7 shows only the 1 st, 2 nd, and 3 rd memory array chips 10, and the 1 st and 2 nd sense amplifier modules 20 connected thereto. The remainder of semiconductor structure 80 may be understood with reference to fig. 7, for example, the 4 th to N-1 th memory array dice 10 may be referred to the 2 nd memory array dice 10 or the 3 rd memory array dice 10; the nth memory array tile 10 may refer to the 1 st memory array tile 10.
It should be noted that the main difference between fig. 7 and fig. 5 is the connection manner of the first bit line 31 and the second bit line 32, so that other contents in fig. 7 are not repeated.
It should be noted that fig. 7 illustrates an alternative arrangement of the first bit line and the second bit line, and thus, in connection with fig. 7, the bit line of the 2 nd memory array chip in the embodiment of the disclosure may be the first bit line 31 of the 2 nd memory array chip; the bit line of the N-1 th memory array tile may be the second bit line 32 of the 2 nd memory array tile.
In other embodiments of the present disclosure, the semiconductor structure further includes: a plurality of second wires 52 and a plurality of second contact structures 42; the second wire 52 extends in a second direction; for the 1 st and nth memory array chips 10, the first bit line 31 and the second bit line 32 thereof are electrically connected to the second conductive line 52 through the second contact structure 42, respectively, so that the first bit line 31 and the second bit line 32 thereof are connected to each other.
Fig. 8 is a left side view of the partial structure of fig. 7, and as shown in fig. 8, the first bit line 31 and the second bit line 32 are electrically connected to the second conductive line 52 through the corresponding second contact structures 42, respectively, and further the first bit line 31 and the second bit line 32 are connected to each other. Similarly, the top view of the second contact structure 42 may be of various shapes.
In the embodiment of the disclosure, the sum of the delay of the first bit line 31 of each 1 st memory array tile 10, the second bit line 32 of each 1 st memory array tile 10, each second conductive line, and each second contact structure is approximately equal to the delay of the bit line of each 2 nd memory array tile 10; the sum of the delay of the first bit line 31 of each nth memory array tile 10, the second bit line 32 of each nth memory array tile 10, each second conductive line, and each second contact structure is approximately equal to the delay of the bit line of each N-1 th memory array tile 10.
That is, for the 1 st memory array chip 10 and the nth memory array chip 10, the sum of the delays (within the error-allowable range) of the 1 st first bit line 31, the 2 second contact structures, the 1 second conductive line, and the 1 second bit line 32 having the connection relationship is a third value; for the 2 nd to N-1 st memory array chips 10, the delay of the first bit line 31 is a third value, and the delay of the second bit line 32 (within the error tolerance range) is a third value.
In the disclosed embodiment, with continued reference to fig. 7, the sum of the delays of the first bit line 31 of each 1 st memory array tile 10, each two second contact structures 42, each second conductive line 52, and the second bit line 32 of each 1 st memory array tile 10 is equal to the delay of the bit line of each 2 nd memory array tile 10; the sum of the delays of the first bit line 31 of each nth memory array tile 10, each two second contact structures 42, each second conductive line 52, and the second bit line 32 of each nth memory array tile 10 is equal to the delay of the bit line of each N-1 th memory array tile 10. In this way, the delays of the circuits connected to the two ends of the sense amplifier module 20 can be equal, so that the consistency of the time sequence of the signals transmitted by the two ends of the sense amplifier module 20 is ensured.
The sum of the lengths of the first bit line 31 of each 1 st memory array tile 10 and the second bit line 32 of each 1 st memory array tile 10 is approximately equal to the length of the first bit line 31 of each 2 nd memory array tile 10. Since the delay of the bit line is proportional to the resistance of the bit line and the length of the bit line 30, in the case that the sum of the lengths of the first bit line 31 and the second bit line 32 of the 1 st memory array chip 10 is approximately equal to the length of the first bit line 31 of the 2 nd memory array chip 10, a compensation element needs to be added to the first bit line 31 of the 2 nd memory array chip 10 to balance the delay caused by the second contact structure 42 and the second conductive line 52. Thus, the sum of the delays of the first bit line 31 of each 1 st memory array tile 10, each two second contact structures 42, each second conductive line 52, and the second bit line 32 of each 1 st memory array tile 10 is approximately equal to the delay of the bit line of each 2 nd memory array tile 10. And the sum of the resistances of the first bit line 31 of each 1 st memory array die 10, each two second contact structures 42, each second conductive line 52, and the second bit line 32 of each 1 st memory array die 10 is approximately equal to the resistance of the bit line of each 2 nd memory array die 10. The nth and nth-1 memory array tiles 10 may be understood with reference to the 1 st and 2 nd memory array tiles 10.
In some embodiments of the present disclosure, as shown in fig. 9, a plurality of sense amplifiers 200 are included in each sense amplifier module 20. For the 2 nd to N-2 nd sense amplifier modules, the first and second ends of the sense amplifier 200 are electrically connected to an equal number of memory cells, respectively; for the 1 st and N-1 st sense amp modules, the number of memory cells to which the first terminal of sense amplifier 200 is electrically connected is 2 times the number of memory cells to which the second terminal of sense amplifier 200 is electrically connected.
Note that fig. 9 does not show the memory cells included in the memory array chip 10. Since the memory cells are arranged along the bit lines 30 in the memory array tile 10, the number of memory cells can be characterized by the length of the bit lines 30, with longer bit lines 30 connecting more memory cells.
In the disclosed embodiment, referring to fig. 4 and 9, for the sense amplifier 200 in the 1 st sense amplifier module 20 (located between the 1 st and 2 nd memory array chips 10), a first end thereof is electrically connected to the first bit line 31 and the second bit line 32 in the 1 st memory array chip 10, and a second end thereof is electrically connected to the first bit line 31 in the 2 nd memory array chip 10; the length of the bit line 30 to which the first end is connected is substantially equal to the length of the bit line 30 to which the second end is connected. That is, for the sense amplifier 200 in the 1 st sense amplifier module 20, a first terminal thereof is electrically connected to the memory cells in the 1 st memory array chip 10, and a second terminal thereof is electrically connected to the memory cells in the 2 nd memory array chip 10; the number of memory cells to which the first end is connected is approximately equal to 2 times the number of memory cells to which the second end is connected. The (N-1) th sense amp module 20 (located between the (N) th and (N-1) th memory array die 10) can be understood with reference to the (1) th sense amp module 20.
In the embodiment of the present disclosure, referring to fig. 9, for the other sense amplifying modules 20 except for the 1 st and the nth, the first and second ends of the sense amplifier 200 are electrically connected to the bit lines 30 in the memory array chips 10 at both sides thereof, respectively, and the lengths of the bit lines 30 in the memory array chips 10 at both sides thereof are equal. For example, for the sense amplifier 200 in the 2 nd sense amplifier module 20 (located between the 2 nd and 3 rd memory array dice 10), its first end is electrically connected to the bit line 30 in the 2 nd memory array dice 10 and its second end is electrically connected to the bit line 30 in the 3 rd memory array dice 10; the length of the bit line 30 to which the first end is connected is equal to the length of the bit line 30 to which the second end is connected. That is, for the sense amplifier 200 in the other sense amplifier module 20, the number of memory cells connected to the first terminal thereof is equal to the number of memory cells connected to the second terminal thereof.
In the embodiment of the disclosure, referring to fig. 9, for each sense amplifier 200, the memory cell to which the first terminal is electrically connected stores first data, and the memory cell to which the second terminal is electrically connected stores second data, which may be the same or different. When the sense amplifier 200 amplifies, only the memory cell connected at one end is turned on, and the memory cell connected at the other end is actually turned off, but the bit line connected at the other end is charged to a preset potential (which may be expressed as logic 0.5), so that one end of the sense amplifier 200 receives a data signal (a data signal to be written or a data signal to be read), and the other end is at the preset potential, thereby performing sensing and amplification, thereby completing the writing or reading process.
In another embodiment of the present disclosure, another semiconductor structure is provided. The semiconductor structure includes: n storage array sheets and N-1 sense amplifier modules, wherein the N storage array sheets are sequentially arranged along a first direction, 1 sense amplifier module is arranged between every 2 adjacent storage array sheets, and each sense amplifier module comprises a plurality of sense amplifiers;
each of the 2 nd to N-1 th memory array chips includes a plurality of memory cells that perform reading and writing of data through sense amplifiers corresponding thereto; each of the 1 st and nth memory array tiles includes a plurality of twin cells (twin cells) including two memory cells storing the same data, the twin cells simultaneously performing reading and writing of data through sense amplifiers corresponding thereto.
It should be noted that the physical structure of the semiconductor structure can still be seen in fig. 1-9. As described above, for the 1 st and N th memory array chips, since a part of memory cells are directly electrically connected to adjacent sense amplifiers via a first bit line and another part of memory cells are electrically connected to the first bit line and thus to adjacent sense amplifiers via a second bit line, there are 2 memory cells connected to the same sense amplifier for a plurality of memory cells coupled to the same word line, and these 2 memory cells are commonly selected and perform the same operation.
In some embodiments, in each memory array slice, a plurality of memory cells are arranged in an array, a row direction of the array is a first direction, a column direction of the array is a second direction, and the second direction intersects the first direction;
for the 1 st and N th memory array chips, two memory cells of the double sub-cells are located in the same column, and in the case that the first bit line and the second bit line are sequentially arranged in a crossing manner, two memory cells of the double sub-cells are located in two adjacent rows.
It should be noted that if the arrangement of the first bit line and the second bit line is changed, the positions of the dual sub-cells will also be changed correspondingly.
In some embodiments, as described above, each memory array slice further includes a plurality of word lines and a plurality of bit lines, the memory cell includes a switch tube and a capacitor, the gate of the switch tube is connected to a word line, the first end of the switch tube is connected to the capacitor, and the second end of the switch tube is connected to a bit line (the first bit line or the second bit line); in the 1 st and nth memory array chips, two memory cells included in a dual sub-cell are coupled to the same word line.
Thus, a twin subcell can be considered to be connected not only to the same word line, but also to the same end of the same sense amplifier; thus, the dual sub-units are simultaneously turned on and the same operation is performed.
In some embodiments, the plurality of bit lines in the memory array slice includes a plurality of first bit lines and a plurality of second bit lines, and the second end of the switching tube is connected to one of the first bit lines or the second bit lines; in the memory array chip, first bit lines and second bit lines are alternately arranged along a second direction, and a second end of a switching tube is connected to the first bit lines or the second bit lines, wherein the first bit lines and the second bit lines are alternately arranged along the first direction; for the 2 nd to N-2 nd sense amplifier modules, the first end of the 1 sense amplifier is connected with 1 first bit line of the adjacent memory array chip, and the second end of the 1 sense amplifier is connected with 1 second bit line of the other adjacent memory array chip; for the 1 st sense amplifier module, a first end of the 1 st sense amplifier is connected with 1 first bit line and 1 second bit line of the 1 st memory array chip, and a second end of the sense amplifier is connected with 1 second bit line of the 2 nd memory array chip; for the N-1 th sense amplifier module, a first end of the sense amplifier is connected with 1 first bit line of the N-1 th memory array chip, and a second end of the sense amplifier is connected with 1 first bit line and 1 second bit line of the N-1 th memory array chip.
It should be noted that, referring to fig. 3 and 9, adjacent first bit lines and second bit lines of the memory array chip 10 (1 st and N-th memory array chips) located at the edge are connected to each other, and are correspondingly connected to a plurality of sense amplifiers 200 of the 1 st or N-1 st sense amplifier module; thus, the adjacent two memory cells 100 connected to each word line of the memory array chip 10 located at the edge are connected to the first and second bit lines connected to each other, respectively, and thus connected to the same end of the same sense amplifier 200; thus, when reading or writing data, one word line of the memory array chip 10 located at the edge simultaneously turns on two memory cells 100 (i.e., dual sub-cells) connected to the same sense amplifier 200; thus, two memory cells 100 that are open at the same time (i.e., dual sub-cells) write and read the same data.
In brief, when reading or writing data, one word line of the memory array chip 10 located at the edge opens two memory cells 100, and the two memory cells 100 are denoted as dual cells (twin cells), which are connected to the same end of the sense amplifier 200. At least one of the twin subcells corresponds to the memory cell 100 connected to the other end of the sense amplifier 200 for equal bit line length, i.e., for equal delay. That is, the delays of the two memory cells 100 to which the first and second ends of each sense amplifier 200 (located at the 1 st or N-1 st sense amplifier module 20) are connected are equal.
That is, for the 1 st and N-1 st sense amp modules 20, the data of the two memory cells 100 connected to the first end of each sense amp 200 are the same, and the delay of one of the memory cells 100 is equal to the delay of the memory cell 100 connected to the second end of the sense amp 200; therefore, the first and second bit lines of the memory array chip 10 at the edge are connected to each other without affecting the read or write data.
Thus, the semiconductor structure is configured to input target data to the selected sense amplifier and turn on the selected word line to enable the selected double sub-unit to be written with the target data in the case of receiving the write data instruction for the 1 st and the nth memory array slices;
or, in case of receiving a read data command for the 1 st and nth memory array tiles, turning on the selected word line, acquiring an output signal of the selected sense amplifier to read out the data stored by the selected dual sub-cell.
Fig. 10 is a schematic structural diagram of a memory 90 according to an embodiment of the present disclosure, and as shown in fig. 10, the memory 90 includes a semiconductor structure 80.
In some embodiments of the present disclosure, as shown in fig. 10, memory 90 is a DRAM.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (14)
1. A semiconductor structure, the semiconductor structure comprising: n memory array chips and N-1 sense amplifier modules;
the N storage array sheets are sequentially arranged along a first direction; 1 sense amplifier module is arranged between every 2 adjacent memory array chips;
each of the memory array tiles includes: a plurality of memory cells, a plurality of first bit lines, and a plurality of second bit lines; wherein,,
for the 2 nd to N-1 st memory array chips, a first part of the memory cells in the memory array chips are electrically connected to a first side adjacent sense amplifier module through the corresponding first bit lines, and a second part of the memory cells in the memory array chips are electrically connected to a second side adjacent sense amplifier module through the corresponding second bit lines;
For the 1 st and the N th memory array chips, a first part of the memory cells in the memory array chips are electrically connected to adjacent sense amplifier modules through the corresponding first bit lines; a second portion of the memory cells in the memory array die are electrically connected to the corresponding first bit lines through the corresponding second bit lines to connect to adjacent ones of the sense amplifier modules.
2. The semiconductor structure of claim 1, wherein,
the area occupied by the 1 st storage array slice and the N storage array slice is equal in the N storage array slices, and the area occupied by the 2 nd to N-1 storage array slices is equal;
the area occupied by any one of the 1 st memory array chip and the N-th memory array chip is half the area occupied by any one of the 2 nd to N-1 st memory array chips.
3. The semiconductor structure of claim 2, wherein,
the lengths of the N storage array plates along the second direction are equal; the second direction intersects the first direction;
the length of any one of the 1 st memory array chip and the nth memory array chip along the first direction is half of the length of any one of the 2 nd to N-1 st memory array chips along the first direction.
4. The semiconductor structure of claim 3, wherein the first bit line and the second bit line are sequentially arranged crosswise along a second direction;
for the 1 st and the N th memory array chips, 1 first bit line is correspondingly connected with 1 second bit line adjacent to the 1 first bit line, and the sum of the lengths of the 1 first bit line and the 1 second bit line with a connection relationship is a first value;
for the 2 nd to N-1 th memory array chips, the length of each first bit line is the first value, and the length of each second bit line is the first value.
5. The semiconductor structure of claim 4, wherein the semiconductor structure further comprises: a plurality of first contact structures; the first contact structure extends along a second direction;
for the 1 st memory array chip and the N th memory array chip, 1 first bit line and 1 second bit line are connected with each other through the first contact structure, and the sum of the delays of the 1 first bit line, the 1 second bit line and the 1 first contact structure with a connection relationship is a second value;
for the 2 nd to N-1 th memory array chips, the delay of the first bit line is the second value, and the delay of the second bit line is the second value.
6. The semiconductor structure of claim 4, wherein the semiconductor structure further comprises: a plurality of second wires and a plurality of second contact structures; the second wire extends along a second direction;
for the 1 st and the N-th memory array chips, 1 first bit line is connected to 1 second wire through 1 second contact structure, and 1 second bit line is connected to the same second wire through another second contact structure, so as to realize the interconnection of 1 first bit line and 1 second bit line.
7. The semiconductor structure of claim 6, wherein,
for the 1 st memory array chip and the N th memory array chip, the sum of the delays of the 1 first bit line, the 2 second contact structures, the 1 second wire and the 1 second bit line with a connection relationship is a third value;
for the 2 nd to N-1 th memory array chips, the delay of the first bit line is the third value, and the delay of the second bit line is the third value.
8. The semiconductor structure of any one of claims 1-7, wherein each of the sense amplifier modules comprises: a plurality of sense amplifiers;
Each of the memory cells is correspondingly electrically connected to the sense amplifier in the sense amplifier module;
for the 2 nd to N-2 nd sense amplifier modules, the first end and the second end of the sense amplifier are respectively and electrically connected with the storage units with the same quantity;
for the 1 st and N-1 st sense amplifier modules, the number of the memory cells electrically connected to the first terminal of the sense amplifier is 2 times the number of the memory cells electrically connected to the second terminal of the sense amplifier.
9. A semiconductor structure, the semiconductor structure comprising: n storage array sheets and N-1 sense amplifier modules, wherein the N storage array sheets are sequentially arranged along a first direction, 1 sense amplifier module is arranged between every 2 adjacent storage array sheets, and each sense amplifier module comprises a plurality of sense amplifiers;
each of the 2 nd to N-1 th memory array tiles includes a plurality of memory cells that perform reading and writing of data through sense amplifiers corresponding thereto;
the 1 st and nth memory array tiles each include a plurality of twin sub-cells including two of the memory cells storing the same data, the twin sub-cells simultaneously performing reading and writing of data through sense amplifiers corresponding thereto.
10. The semiconductor structure of claim 9, wherein in each of the memory array tiles, a plurality of the memory cells are arranged in an array, a row direction of the array being a first direction, a column direction of the array being a second direction, the second direction intersecting the first direction;
for the 1 st and the N th memory array chip, the two memory cells of the double sub-cells are located in the same column, and the two memory cells of the double sub-cells are located in two adjacent rows.
11. The semiconductor structure of claim 9, wherein each of the memory array tiles further comprises a plurality of word lines and a plurality of bit lines, the memory cell comprises a switch tube and a capacitor, the gate of the switch tube is connected to a word line, the first end of the switch tube is connected to the capacitor, and the second end of the switch tube is connected to a bit line;
in the 1 st and nth memory array chips, the two memory cells included in the dual sub-cell are coupled to the same word line.
12. The semiconductor structure of claim 11, wherein,
the plurality of bit lines in the memory array slice comprise a plurality of first bit lines and a plurality of second bit lines, and the second end of the switch tube is connected with one of the first bit lines or the second bit lines; in the memory array chip, the first bit lines and the second bit lines are alternately arranged along the second direction;
For the 2 nd to N-2 nd sense amplifier modules, a first end of 1 sense amplifier is connected with 1 first bit line of the adjacent memory array slice, and a second end of 1 sense amplifier is connected with 1 second bit line of the other adjacent memory array slice;
for the 1 st sense amplifier module, a first end of the 1 st sense amplifier is connected with 1 first bit line and 1 second bit line of the 1 st memory array chip, and a second end of the sense amplifier is connected with 1 second bit line of the 2 nd memory array chip;
for the N-1 sense amplifier module, a first end of the sense amplifier is connected with 1 first bit line of the N-1 memory array chip, and a second end of the sense amplifier is connected with 1 first bit line and 1 second bit line of the N memory array chip.
13. A memory comprising the semiconductor structure of any of claims 1-12.
14. The memory of claim 13, wherein the memory is a DRAM.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116580729A (en) * | 2023-07-12 | 2023-08-11 | 长鑫存储技术有限公司 | Memory and repairing method thereof |
| WO2024088101A1 (en) * | 2022-10-28 | 2024-05-02 | 长鑫存储技术有限公司 | Semiconductor structure and memory |
| CN118155677A (en) * | 2024-03-13 | 2024-06-07 | 北京超弦存储器研究院 | Storage structure, memory and electronic equipment |
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| CN116364149A (en) * | 2022-10-28 | 2023-06-30 | 长鑫存储技术有限公司 | Semiconductor structure and memory |
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- 2023-03-31 CN CN202310354331.4A patent/CN116364149A/en not_active Withdrawn
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| US20060138466A1 (en) * | 2004-12-23 | 2006-06-29 | Jin Choi | Layout of semiconductor memory device and method of controlling capacitance of dummy cell |
| US20070081375A1 (en) * | 2005-10-11 | 2007-04-12 | Elpida Memory, Inc. | Semiconductor storage device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024088101A1 (en) * | 2022-10-28 | 2024-05-02 | 长鑫存储技术有限公司 | Semiconductor structure and memory |
| CN116580729A (en) * | 2023-07-12 | 2023-08-11 | 长鑫存储技术有限公司 | Memory and repairing method thereof |
| CN116580729B (en) * | 2023-07-12 | 2023-12-01 | 长鑫存储技术有限公司 | Memory and repairing method thereof |
| CN118155677A (en) * | 2024-03-13 | 2024-06-07 | 北京超弦存储器研究院 | Storage structure, memory and electronic equipment |
Also Published As
| Publication number | Publication date |
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| WO2024088101A1 (en) | 2024-05-02 |
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