CN116359719A - Integrated circuit intermittent fault on-line monitoring and intelligent early warning method - Google Patents
Integrated circuit intermittent fault on-line monitoring and intelligent early warning method Download PDFInfo
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 116
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000003466 welding Methods 0.000 claims abstract description 71
- 239000003990 capacitor Substances 0.000 claims abstract description 61
- 238000005070 sampling Methods 0.000 claims description 64
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 239000011889 copper foil Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
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- 239000003989 dielectric material Substances 0.000 claims description 4
- 230000036541 health Effects 0.000 abstract description 20
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- 229910000679 solder Inorganic materials 0.000 description 5
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- G01R31/317—Testing of digital circuits
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- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
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- Y04S10/52—Outage or fault management, e.g. fault detection or location
Abstract
The invention discloses an integrated circuit intermittent fault on-line monitoring and intelligent early warning method, which utilizes a monitoring capacitor formed by an FPGA chip to carry out health monitoring on any two welding spots to be detected at the same time, so that an external monitoring capacitor is not required to be welded on a PCB, and the monitoring cost ratio is improved; the provided monitoring module outputs the current moment value and the moment of the latest failure to the outside, and can be used for more complete monitoring of the health state of the welding spot and service life evaluation; the Fault threshold value can be set through the port fault_N signal, so that the flexibility of monitoring the health state of the welding spot is improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit health monitoring, and particularly relates to an integrated circuit intermittent fault on-line monitoring and intelligent early warning method.
Background
Field Programmable Gate Arrays (FPGAs) find wide application in electronic systems with their unique fine-grained parallelism. The electronic system can bear thermal stress and mechanical stress applied by external environment in the operation process, so that welding failure of electronic components is caused, and the FPGA is used as one of key components of the core of the electronic system, and the welding failure of the FPGA can possibly bring about disastrous accidents of the whole system. Therefore, the method has important significance in health monitoring of the FPGA welding spot state.
Studies have shown that: the resistance of the welding spot of the electronic component is increased when the health state is degraded under the action of thermal stress and mechanical stress. Therefore, the monitoring of the health state of the welding spots of the electronic components can be converted into the monitoring of the impedance of the welding spots of the electronic components, and the monitoring result can provide data support for the health monitoring and the service life estimation of the electronic components. The industry generally considers that the failure judgment standard of the solder joint of the FPGA package is as follows: (1) peak resistance duration greater than 300 Ω exceeds 200us; (2) 10 or more failures occur 10% of the time after the first failure time occurs.
The document "Ball Grid Array (BGA) Solder Joint Intermittency Detection:SJBIST" describes a SJ-BIST (Solder Joint Built-In self test) method proposed by American Sharp and Tuber company, the method is used for fault monitoring of FPGA welding spots, only a single capacitor is needed to detect two welding spots simultaneously, the SJ-BIST method can be used for detecting the change of the resistance of the FPGA welding spots within a few nanoseconds, but the method cannot obtain the resistance value of the detected welding spots, only the detected welding spot faults can be diagnosed, and the related study of service life prediction is difficult to be carried out by using fault data of the method. The patent number 2019102486286 'a high-precision FPGA welding spot fault real-time diagnosis method and diagnosis device' proposes a method for carrying out health monitoring on 2 FPGA welding spots by adopting a single capacitor and obtaining welding spot resistance values. The existing welding spot online monitoring method needs to be additionally provided with a monitoring capacitor no matter whether the accurate welding spot resistance value can be obtained or not, and the increase of the monitoring capacitor has the following effects: (1) the accuracy of the capacitor is influenced by the production process and the working environment, and the accuracy of monitoring the health state of the welding is influenced; (2) monitoring capacitance faults to cause error of monitoring results; (3) monitoring capacitance increases the cost of the electronic system. Therefore, the novel FPGA welding spot health state monitoring method without monitoring the capacitance has important engineering significance.
Disclosure of Invention
The invention aims to overcome the problems in the prior art and provide an on-line monitoring and intelligent early warning method for intermittent faults of an integrated circuit, which utilizes a monitoring capacitor formed by an FPGA chip to simultaneously carry out health monitoring on any two welding spots to be detected, thereby providing a more cost-effective and more accurate monitoring method for the health monitoring of the FPGA welding spots.
In order to achieve the technical purpose and the technical effect, the invention is realized by the following technical scheme:
an integrated circuit intermittent fault on-line monitoring and intelligent early warning method is characterized by comprising the following steps:
firstly, setting a monitoring capacitor on an FPGA chip to be detected, taking any two adjacent layers of copper foils on a PCB of the FPGA chip as capacitor plates, and forming a monitoring capacitor by taking a base material between the two layers of copper foils as a dielectric material;
step two, arbitrarily selecting two welding spots to be detected on the FPGA chip, namely a welding spot A and a welding spot B, and shorting pins of the welding spots A and B to be connected to a monitoring capacitor;
step three, a monitoring module is arranged, wherein the monitoring module is provided with a port A, a port B, a port Fault_N, a port Clk-S, a port Clk-C, a port CntA, a port CntB, a port FaultA_T, a port FaultB_T and a port current_T;
the port A and the port B are respectively used for connecting two welding spots A and B to be detected on the FPGA chip;
the port Fault_N is used for manually presetting the high-frequency sampling period number of the Fault threshold;
the port Clk-C is used for connecting a low-frequency clock control signal, controlling the states of the port A and the port B, and respectively controlling the port A and the port B to output a high-level or low-level state;
the port Clk-S is used for connecting a high-frequency clock sampling signal, sampling the signal of the port A or the port B, obtaining the state of the port A or the port B, and recording the corresponding sampling signal period number;
the port CntA is used for outputting the sampling signal cycle number when the port B is sampled, and the port CntB is used for outputting the sampling signal cycle number when the port A is sampled;
the port current_T is used for connecting a timer signal and recording the Current time value in real time;
the port FaultA_T is used for outputting the time when the current welding spot A fails, and the port FaultB_T is used for outputting the time when the current welding spot B fails;
step four, operating a monitoring module, wherein the monitoring module is powered on and initialized and then sequentially enters the following states:
state 1: the port A and the port B output low level at the same time, and discharge the monitoring capacitor;
state 2 is entered when the low frequency clock of port Clk-C goes down: the port A outputs high level, the monitoring capacitor is charged through the welding spot A, meanwhile, the signal of the port B is sampled through the high-frequency clock sampling signal of the port Clk-S, the sampling signal period number from the high level output of the port A to the high level input of the port B is recorded, and the sampling signal period number is output by the port CntA;
state 3 is entered when the low frequency clock signal of port Clk-C rises: the port A and the port B output low level at the same time, and the monitoring capacitor is discharged again;
when the low frequency clock control signal at port Clk-C falls on the edge again, state 4 is entered: the port B outputs a high level, the monitoring capacitor is charged through the welding spot B, meanwhile, the signal of the port A is sampled through the high-frequency clock sampling signal of the port Clk-S, the sampling signal period number from the start of outputting the high level by the port B to the stop of inputting the high level by the port A is recorded, and the sampling signal period number is output by the port CntB;
step five, in the running process of the monitoring module, recording the Current moment value in real time through the port current_T; when the output value of the port CntA is larger than a preset Fault threshold value in the port Fault_N, outputting the Current time value recorded by the port current_T to the port FaultA_T; and when the output value of the port CntB is larger than the preset Fault threshold value in the port Fault_N, outputting the Current time value recorded by the port current_T to the port Fault_T.
Further, the pins of the welding point A and the welding point B are in short circuit connection with one polar plate of the monitoring capacitor, and the other polar plate of the monitoring capacitor is grounded.
Further, the monitoring module is further provided with a port RST, the port RST is used for inputting a reset signal of the monitoring module, and the timer is reset to 0 moment when the monitoring module is electrified and initialized.
Further, the resistance value R of the solder joint to be detected by the FPGA chip may be expressed as:
wherein epsilon is the relative dielectric constant, S is the opposite area of the two electrode plates of the monitoring capacitor, d is the vertical distance between the two electrode plates of the monitoring capacitor, and V 1 To monitor the voltage value to which the capacitor can be charged finally, f is the frequency of the high-frequency clock sampling signal, V t The threshold voltage value of the sampling point from the low level state to the high level state is n, and the number of sampling signal cycles is n;
when the monitoring module operates, in the state 2, sampling signal periods of a high-frequency clock are obtained from the output of a high level of the port A to the input of a high level of the port B, and the sampling signal periods are taken as n, namely the output value of the port CntA, and the sampling signal periods are substituted into the output value to obtain the resistance value of a welding spot at the current moment A; in the state 4, the high-frequency clock sampling signal is used for obtaining the sampling signal period number from the output of the high level of the port B to the input of the high level of the port A as n, namely the output value of the port CntB, and the sampling signal period number is substituted into the output value to obtain the resistance value of the welding spot at the current moment B.
The beneficial effects of the invention are as follows:
according to the integrated circuit intermittent fault on-line monitoring and intelligent early warning method provided by the invention, the monitoring capacitor formed by the FPGA chip is utilized to perform health monitoring on any two welding spots to be detected at the same time, so that an external monitoring capacitor is not required to be welded on a PCB, and the monitoring cost ratio is improved; the provided monitoring module outputs the current moment value and the moment of the latest failure to the outside, and can be used for more complete monitoring of the health state of the welding spot and service life evaluation; the Fault threshold value can be set through the port fault_N signal, so that the flexibility of monitoring the health state of the welding spot is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a schematic diagram of a principle connection of the present invention;
fig. 2 is a schematic diagram of states of a monitoring module according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The on-line monitoring and intelligent early warning method for intermittent faults of the integrated circuit shown in fig. 1 utilizes a monitoring capacitor formed by an FPGA chip to simultaneously monitor health of any two welding spots to be detected, and comprises the following steps:
firstly, setting a monitoring capacitor on an FPGA chip to be detected, specifically, taking any two adjacent layers of copper foils 10 on a PCB of the FPGA chip as capacitor plates, and forming the monitoring capacitor by taking a base material 20 between the two layers of copper foils 10 as a dielectric material.
As can be seen from physical knowledge, a capacitor can be generated between two parallel electrode plates, as shown in fig. 1, two adjacent layers of copper foils of a PCB are used as capacitor electrode plates, and a substrate between the two layers of copper foils is used as a dielectric material to form a capacitor, wherein the capacitance is shown in formula (1):
wherein C is F The capacitance value between two parallel electrode plates is F, epsilon is relative dielectric constant, S is the opposite area of the two parallel electrode plates, d is the vertical distance between the two parallel electrode plates, pi is the circumference rate constant, and k is static electricity, wherein pi is equal to 3.14159A force constant, the value of which is: 8.987551 ×10 9 N·m 2 /C 2 。
Substituting a known constant into formula (1) and transforming it can result in formula (2):
wherein, the capacitance value unit obtained in the formula (2) is F, and then the formula (2) is further transformed to obtain the formula (3):
wherein, the capacitance value unit obtained in the formula (3) is pF.
And secondly, arbitrarily selecting two welding spots to be detected from the FPGA chip, namely a welding spot A and a welding spot B, shorting pins of the welding spots A and B to one polar plate of the monitoring capacitor, and grounding the other polar plate of the monitoring capacitor.
Step three, a monitoring module is arranged, and specifically, the monitoring module is provided with a port A, a port B, a port Fault_N, a port Clk-S, a port Clk-C, a port CntA, a port CntB, a port FaultA_T, a port FaultB_T, a port Current_T and a port RST.
The port A and the port B are respectively used for connecting two welding spots A and B to be detected on the FPGA chip.
The port fault_n is used for manually presetting the high-frequency sampling period number of the Fault threshold.
The port Clk-C is used for connecting a low-frequency clock control signal of 500KHz, controlling the states of the port A and the port B, respectively controlling the port A and the port B to output a high-level or low-level state, and the time for charging and discharging an external capacitor can be accurate to 1 mu s.
The port Clk-S is used for connecting a high-frequency clock sampling signal of 100MHz, sampling a signal of the port A or the port B, obtaining the state of the port A or the port B, and recording the corresponding sampling signal period number.
The port CntA is used for outputting the sampling signal cycle number when the port B is sampled, and the port CntB is used for outputting the sampling signal cycle number when the port a is sampled.
The port current_t is used for connecting a timer signal and recording the Current time value in real time.
Port faulta_t is used to output the time when the current last a-pad failed and port faultb_t is used to output the time when the current last B-pad failed.
The port RST is used for inputting a reset signal of the monitoring module.
Step four, operating the monitoring module, as shown in fig. 2, and after the monitoring module is powered on and initialized, sequentially entering the following states:
state 1: the port A and the port B output low level at the same time, the monitoring capacitor is discharged, and the port RST resets the timer to 0 moment;
state 2 is entered when the low frequency clock of port Clk-C goes down: the port A outputs high level, charges the monitoring capacitor through the welding spot A, samples the signal of the port B through the high-frequency clock sampling signal of the port Clk-S, records the sampling signal period number from the start of outputting the high level by the port A to the stop of inputting the high level by the port B, and outputs the sampling signal period number by the port CntA for calculating the resistance value of the welding spot of the current moment A;
state 3 is entered when the low frequency clock signal of port Clk-C rises: the port A and the port B output low level at the same time, and the monitoring capacitor is discharged again;
when the low frequency clock control signal at port Clk-C falls on the edge again, state 4 is entered: the port B outputs high level, the monitoring capacitor is charged through the welding spot B, meanwhile, the signal of the port A is sampled through the high-frequency clock sampling signal of the port Clk-S, the sampling signal period number from the start of outputting the high level of the port B to the stop of inputting the high level of the port A is recorded, and the sampling signal period number is output by the port CntB and is used for calculating the resistance value of the welding spot at the current moment B.
The capacitor charging time is related to the capacitance value and pad resistance of the capacitor according to the charging characteristics of the capacitor, and the capacitance value of the capacitor is fixed.
As is well known, the charge and discharge of a capacitor can be expressed as:
wherein V is 0 For the voltage value of the capacitor at the initial moment, V 1 The voltage value to which the capacitor can be charged finally is t is the charging time, V t Is the voltage value at the time of charging t.
After the above transformation, the resistance value of the FPGA solder joint can be expressed as:
in the present invention, the initial voltage V of the charging process is obtained by discharging the monitoring capacitor 0 0V; sampling by a high-frequency clock sampling signal with frequency f to obtain a critical voltage value of a sampling point from a low-level state to a high-level state, namely a voltage value V at a charging time t t The recorded sampling signal cycle number is n; the capacitance value C of the monitoring capacitor can be calculated by the formula (3) pF Substituting the resistance into the capacitance C in the formula (5), and then the resistance R of the FPGA welding spot can be expressed as:
for the FPGA pin with 3.3V level, when the time from the low level to the time when the high level is detected is t, V 0 Is 0V, V 1 Is 3.3V, V t Is 2V. Then it can be seen that transforming equation (6):
when the monitoring module operates, a high-frequency clock sampling signal CLK_S is used for obtaining a sampling signal period number from the output of a high level of a port A to the input of a high level of a port B as n, namely a monitoring module output signal CntA, and the sampling signal period number is substituted into a formula (6) to obtain the resistance value of a welding spot at the current moment A; in the state 4, the high-frequency clock sampling signal CLK_S is used for obtaining the sampling signal period number from the output of the high level of the port B to the input of the high level of the port A as n, namely the monitoring module output signal CntB, and the sampling signal period number is substituted into the formula (6) to obtain the resistance value of the welding spot at the current moment B.
Step five, in the running process of the monitoring module, recording the Current moment value in real time through the port current_T; when the output value of the port CntA is larger than a preset Fault threshold value in the port Fault_N, outputting the Current time value recorded by the port current_T to the port FaultA_T; when the output value of the port CntB is larger than a preset Fault threshold value in the port Fault_N, outputting the Current time value recorded by the port current_T to the port Fault_T;
wherein, faultA_T is the time when the current A welding spot fails, and FaultB_T is the time when the current B welding spot fails.
According to the integrated circuit intermittent fault on-line monitoring and intelligent early warning method provided by the invention, the monitoring capacitor formed by the FPGA chip is utilized to perform health monitoring on any two welding spots to be detected at the same time, so that an external monitoring capacitor is not required to be welded on a PCB, and the monitoring cost ratio is improved; the provided monitoring module outputs the current moment value and the moment of the latest failure to the outside, and can be used for more complete monitoring of the health state of the welding spot and service life evaluation; the Fault threshold value can be set through the port fault_N signal, so that the flexibility of monitoring the health state of the welding spot is improved.
In the description of the present specification, the descriptions of the terms "one embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims.
Claims (4)
1. An integrated circuit intermittent fault on-line monitoring and intelligent early warning method is characterized by comprising the following steps:
firstly, setting a monitoring capacitor on an FPGA chip to be detected, taking any two adjacent layers of copper foils (10) on a PCB of the FPGA chip as capacitor plates, and forming the monitoring capacitor by taking a base material (20) between the two layers of copper foils (10) as a dielectric material;
step two, arbitrarily selecting two welding spots to be detected on the FPGA chip, namely a welding spot A and a welding spot B, and shorting pins of the welding spots A and B to be connected to a monitoring capacitor;
step three, a monitoring module is arranged, wherein the monitoring module is provided with a port A, a port B, a port Fault_N, a port Clk-S, a port Clk-C, a port CntA, a port CntB, a port FaultA_T, a port FaultB_T and a port current_T;
the port A and the port B are respectively used for connecting two welding spots A and B to be detected on the FPGA chip;
the port Fault_N is used for manually presetting the high-frequency sampling period number of the Fault threshold;
the port Clk-C is used for connecting a low-frequency clock control signal, controlling the states of the port A and the port B, and respectively controlling the port A and the port B to output a high-level or low-level state;
the port Clk-S is used for connecting a high-frequency clock sampling signal, sampling the signal of the port A or the port B, obtaining the state of the port A or the port B, and recording the corresponding sampling signal period number;
the port CntA is used for outputting the sampling signal cycle number when the port B is sampled, and the port CntB is used for outputting the sampling signal cycle number when the port A is sampled;
the port current_T is used for connecting a timer signal and recording the Current time value in real time;
the port FaultA_T is used for outputting the time when the current welding spot A fails, and the port FaultB_T is used for outputting the time when the current welding spot B fails;
step four, operating a monitoring module, wherein the monitoring module is powered on and initialized and then sequentially enters the following states:
state 1: the port A and the port B output low level at the same time, and discharge the monitoring capacitor;
state 2 is entered when the low frequency clock of port Clk-C goes down: the port A outputs high level, the monitoring capacitor is charged through the welding spot A, meanwhile, the signal of the port B is sampled through the high-frequency clock sampling signal of the port Clk-S, the sampling signal period number from the high level output of the port A to the high level input of the port B is recorded, and the sampling signal period number is output by the port CntA;
state 3 is entered when the low frequency clock signal of port Clk-C rises: the port A and the port B output low level at the same time, and the monitoring capacitor is discharged again;
when the low frequency clock control signal at port Clk-C falls on the edge again, state 4 is entered: the port B outputs a high level, the monitoring capacitor is charged through the welding spot B, meanwhile, the signal of the port A is sampled through the high-frequency clock sampling signal of the port Clk-S, the sampling signal period number from the start of outputting the high level by the port B to the stop of inputting the high level by the port A is recorded, and the sampling signal period number is output by the port CntB;
step five, in the running process of the monitoring module, recording the Current moment value in real time through the port current_T; when the output value of the port CntA is larger than a preset Fault threshold value in the port Fault_N, outputting the Current time value recorded by the port current_T to the port FaultA_T; and when the output value of the port CntB is larger than the preset Fault threshold value in the port Fault_N, outputting the Current time value recorded by the port current_T to the port Fault_T.
2. The method for on-line monitoring and intelligent early warning of intermittent faults of an integrated circuit according to claim 1, wherein pins of a welding point A and a welding point B are in short circuit connection with one polar plate of a monitoring capacitor, and the other polar plate of the monitoring capacitor is grounded.
3. The method for on-line monitoring and intelligent early warning of intermittent faults of an integrated circuit according to claim 1, wherein the monitoring module is further provided with a port RST, the port RST is used for inputting a reset signal of the monitoring module, and a timer is reset to 0 moment when the monitoring module is powered on and initialized.
4. The method for on-line monitoring and intelligent early warning of intermittent faults of an integrated circuit according to claim 1, wherein the resistance value R of a welding spot to be detected by the FPGA chip can be expressed as follows:
wherein epsilon is the relative dielectric constant, S is the opposite area of the two electrode plates of the monitoring capacitor, d is the vertical distance between the two electrode plates of the monitoring capacitor, and V 1 To monitor the voltage value to which the capacitor can be charged finally, f is the frequency of the high-frequency clock sampling signal, V t The threshold voltage value of the sampling point from the low level state to the high level state is n, and the number of sampling signal cycles is n;
when the monitoring module operates, in the state 2, sampling signal periods of a high-frequency clock are obtained from the output of a high level of the port A to the input of a high level of the port B, and the sampling signal periods are taken as n, namely the output value of the port CntA, and the sampling signal periods are substituted into the output value to obtain the resistance value of a welding spot at the current moment A; in the state 4, the high-frequency clock sampling signal is used for obtaining the sampling signal period number from the output of the high level of the port B to the input of the high level of the port A as n, namely the output value of the port CntB, and the sampling signal period number is substituted into the output value to obtain the resistance value of the welding spot at the current moment B.
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