CN109932640B - High-precision FPGA welding spot fault real-time diagnosis method and diagnosis device - Google Patents
High-precision FPGA welding spot fault real-time diagnosis method and diagnosis device Download PDFInfo
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Abstract
The invention discloses a high-precision FPGA welding spot fault real-time diagnosis method and a high-precision FPGA welding spot fault real-time diagnosis device.A pin of two FPGA welding spots is connected with an external capacitor, the two pins are set to output a low level state firstly, the external capacitor is discharged, then a pin is set to output a high level state, the external capacitor is charged, a high-frequency clock is adopted to sample a signal of the other pin, the number of cycles sampled by the high-frequency clock is recorded to obtain the charging time of the capacitor, the resistance value of the corresponding FPGA welding spot is calculated, whether the FPGA welding spot is in fault or not is judged, and the service life of the FPGA welding spot is predicted; according to the invention, two welding spots are detected through a single capacitor, so that a more accurate welding spot resistance value can be obtained in real time, and the method can be used for predicting the service life of the welding spot of the FPGA.
Description
Technical Field
The invention belongs to the technical field of chip detection, relates to an FPGA welding spot fault detection technology, and particularly relates to a high-precision FPGA welding spot fault real-time diagnosis method and a high-precision FPGA welding spot fault real-time diagnosis device.
Background
The Field Programmable Gate Array (FPGA) has obvious parallelism and is widely applied to electronic systems. Solder joint failure due to thermal and mechanical stress is one of the most common failures in FPGAs, and it is noteworthy that this failure will cause the resistance of the FPGA solder joint to increase.
Therefore, monitoring of the resistance of the FPGA solder joints can be used to assess the health of the FPGA and provide data for fault and health management of the FPGA. Typically, when the resistance value of a pad of an FPGA exceeds 300 Ω and continues to exceed 200 μ s, it can be determined that the FPGA pad is faulty.
The american rution group company develops an SJ-BIST (Solder Joint build-In self test) method for diagnosing FPGA Solder Joint faults, only one single capacitor is needed to detect two Solder joints simultaneously, and the SJ-BIST method can detect changes In resistance of the FPGA Solder joints within a few nanoseconds, but cannot obtain the resistance of the detected Solder joints, and can only diagnose whether the detected Solder joints are faulty or not.
Although the conventional FPGA welding spot diagnosis method can detect the faults of the FPGA welding spots, the more accurate welding spot resistance value cannot be obtained, and the service life of the FPGA welding spots is predicted.
Disclosure of Invention
The invention aims to provide a high-precision FPGA welding spot fault real-time diagnosis method and a high-precision FPGA welding spot fault real-time diagnosis device.
The purpose of the invention can be realized by the following technical scheme:
a high-precision FPGA welding spot fault real-time diagnosis method specifically comprises the following steps:
step S1, firstly, establishing an FPGA welding spot fault diagnosis method model, wherein the FPGA welding spot fault diagnosis method model comprises two pins PinA and PinB of an FPGA welding spot, and the two pins PinA and PinB are both connected with an external capacitor;
step S2, setting the pin PinA and the pin PinB to output low level state, and discharging the external capacitor;
step S3, setting a pin PinA to output a high level state, and charging an external capacitor;
step S4, sampling a signal of a pin PinB by adopting a high-frequency clock, and acquiring the state of the pin PinB in real time;
step S5, when the pin PinB outputs a high level state, recording the sampling period number of the high-frequency clock, and calculating the resistance value of the FPGA welding spot corresponding to the pin PinA;
wherein, the resistance value R of the FPGA welding spot corresponding to the pin PinA is
Wherein, VthreshIs the critical voltage value, V, of pin PinB from low level state to high level state1The final voltage of the external capacitor in the charging process is obtained, C is the capacitance value of the external capacitor, n is the period number of the high-frequency clock, and f is the sampling frequency of the high-frequency clock;
and step S6, judging whether the FPGA welding spot has a fault or not according to the resistance value of the FPGA welding spot calculated in the step S5, and predicting the service life of the FPGA welding spot.
Further, the method also comprises the following steps:
step S7, setting the pin PinA and the pin PinB to output low level state again, and discharging the external capacitor;
and step S8, setting the pin PinB to output a high level state, charging the external capacitor, obtaining the resistance value of the FPGA welding spot corresponding to the pin PinB by referring to the methods in the steps 4 and 5, judging whether the FPGA welding spot is in fault, and predicting the service life of the FPGA welding spot.
A high-precision FPGA welding spot fault real-time diagnosis device comprises a state machine, wherein the state machine is provided with a port A, a port B, a port Clk-S, a port Clk-C, a port CntA and a port CntB;
the port A and the port B are respectively used for connecting two welding spots to be detected on the FPGA;
the port Clk-C is used for connecting a clock signal, controlling the states of the port A and the port B, controlling the port A or the port B to output a high level state and charging an external capacitor;
the port Clk-S is used for connecting a high-frequency clock sampling signal, sampling the signal of the port A or the port B, acquiring the state of the port A or the port B, and recording the corresponding sampling period number;
CntA is used to output a sampling signal period corresponding to port a, and CntB is used to output a sampling signal period corresponding to port B.
Further, the state machine is also provided with a port RST, and the port RST is used for inputting a reset signal of the system.
Further, the state machine includes four working states during working, which are an idle state, an AWBR working state, a waiting state, and an ARBW working state in sequence.
Further, when the state machine is in an idle state, the port A and the port B output a low level state to discharge the external capacitor; when the state machine enters an AWBR working state, a clock signal of a port Clk-C controls a port A to output a high level state, an external capacitor is charged through the port A, meanwhile, a high-frequency clock sampling signal of the port Clk-S samples a signal of a port B, and a sampling result is output by CntB; when the state machine enters a waiting state, the port A and the port B output a low level state again to discharge the external capacitor; when the state machine enters an ARBW working state, a port B is controlled to output a high level state through a clock signal of a port Clk-C, an external capacitor is charged through the port B, meanwhile, a signal of a port A is sampled through a high-frequency clock sampling signal of the port Clk-S, and a sampling result is output by CntA.
The invention has the beneficial effects that: according to the high-precision FPGA welding spot fault real-time diagnosis method and the diagnosis device, two welding spots are detected by using a single capacitor, and compared with the existing SJ-BIST method, the high-precision FPGA welding spot fault real-time diagnosis method and the high-precision FPGA welding spot fault real-time diagnosis device can obtain a more accurate welding spot resistance value in real time and are used for predicting the service life of the FPGA welding spot.
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The invention is described in further detail below with reference to the figures and specific embodiments.
FIG. 1 is a schematic diagram of a FPGA solder joint fault diagnosis method model in the invention.
FIG. 2 is a diagram of the hardware architecture of the state machine of the present invention.
Fig. 3 is a schematic diagram of the operating state of the state machine of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
The invention provides a high-precision FPGA welding spot fault real-time diagnosis method, which specifically comprises the following steps:
step S1, firstly, establishing an FPGA welding spot fault diagnosis method model, as shown in fig. 1, where the FPGA welding spot fault diagnosis method model includes two pins PinA and PinB of an FPGA welding spot, and the two pins PinA and PinB are both connected to an external capacitor.
In step S2, both pin PinA and pin PinB are set to output a low level state, and the external capacitor is discharged.
And step S3, setting the pin PinA to output a high level state, and charging the external capacitor.
And step S4, sampling the signal of the pin PinB by adopting a high-frequency clock, and acquiring the state of the pin PinB in real time, wherein the sampling frequency of the high-frequency clock is set to be 100MHz, so that the real-time property of the system is improved.
Step S5, when the pin PinB outputs a high level state, the charging time of the external capacitor can be obtained by recording the cycle number of the high frequency clock, and the resistance value of the FPGA solder point corresponding to the pin PinA is calculated.
The capacitor charging time is related to the capacitance value of the capacitor and the pad resistance according to the charging characteristics of the capacitor, and the capacitance value C of the capacitor is fixed.
As is well known, the charging and discharging of a capacitor can be expressed as
Wherein, V0And V1Respectively, the initial voltage and the final voltage of the charging process, t is the charging time, VtIs the value of the voltage at the charging time t.
After the above formula is transformed, the resistance value of the FPGA welding spot can be expressed as
In the invention, the external capacitor is discharged first, so that the initial electricity of the charging processPressure V0Is 0V; meanwhile, the signal of the pin is sampled by a high-frequency clock to obtain the critical voltage value V from a low level state to a high level statethreshI.e. the voltage value V at the charging time tt(ii) a Thirdly, obtaining the charging time t of the external capacitor through the periodicity n of the high-frequency clock and the sampling frequency f of the high-frequency clock, and further representing the resistance value R of the welding point of the FPGA as
In this step, R is the resistance value of the FPGA welding spot corresponding to the pin PinA, and V isthreshIs the critical voltage value, V, of pin PinB from low level state to high level state1The final voltage of the external capacitor in the charging process is C, the capacitance value of the external capacitor is n, the period number of the high-frequency clock is n, and the sampling frequency of the high-frequency clock is f.
And step S6, judging whether the FPGA welding spot has a fault or not according to the resistance value of the FPGA welding spot calculated in the step S5, and predicting the service life of the FPGA welding spot.
In step S7, the pin PinA and the pin PinB are set again to output a low level state, and the external capacitor is discharged.
And step S8, setting the pin PinB to output a high level state, charging an external capacitor, obtaining the resistance value of the FPGA welding point corresponding to the pin PinB by referring to the methods in the step 4 and the step 5, judging whether the FPGA welding point is in fault, and predicting the service life of the FPGA welding point.
As shown in FIG. 2, the high-precision FPGA welding spot fault real-time diagnosis device comprises a state machine, wherein the state machine is provided with a port A, a port B, a port Clk-S, a port Clk-C, a port CntA, a port CntB and a port RST.
The port A and the port B are respectively used for connecting two welding spots to be detected on the FPGA. The port Clk-C is used for connecting a clock signal of 500KHz, controlling the states of the port A and the port B, controlling the port A or the port B to output a high level state, and the time for charging the external capacitor can be accurate to 1 mus. The port Clk-S is used for connecting a high-frequency clock sampling signal of 100MHz, sampling the signal of the port A or the port B, acquiring the state of the port A or the port B, and recording the corresponding sampling period number. CntA is used to output a sampling signal period corresponding to port a, and CntB is used to output a sampling signal period corresponding to port B. In addition, the port RST is used for inputting a reset signal of the system.
As shown in fig. 3, the state machine includes four operating states, which are an idle state, an AWBR operating state, a waiting state, and an ARBW operating state. When the state machine is in an idle state, the port A and the port B output a low level state to discharge the external capacitor; when the state machine enters an AWBR working state, controlling a port A to output a high level state through a clock signal of a port Clk-C, charging an external capacitor through the port A, simultaneously sampling a signal of a port B through a high-frequency clock sampling signal of the port Clk-S, and outputting a sampling result by CntB; when the state machine enters a waiting state, the port A and the port B output a low level state again to discharge the external capacitor; when the state machine enters an ARBW working state, a clock signal of a port Clk-C controls a port B to output a high level state, an external capacitor is charged through the port B, meanwhile, a high-frequency clock sampling signal of the port Clk-S samples a signal of a port A, and a sampling result is output by CntA.
Compared with the existing SJ-BIST method, the device can obtain the resistance value of the corresponding FPGA welding point in the AWBR working state and the ARBW working state, and can predict the service life of the FPGA welding point.
According to the high-precision FPGA welding spot fault real-time diagnosis method and the diagnosis device, two welding spots are detected by using a single capacitor, and compared with the existing SJ-BIST method, the high-precision FPGA welding spot fault real-time diagnosis method and the high-precision FPGA welding spot fault real-time diagnosis device can obtain a more accurate welding spot resistance value in real time and are used for predicting the service life of the FPGA welding spot.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely exemplary and illustrative of the present invention and various modifications, additions and substitutions may be made by those skilled in the art to the specific embodiments described without departing from the scope of the invention as defined in the following claims.
Claims (1)
1. A high-precision FPGA welding spot fault real-time diagnosis method is characterized in that the high-precision FPGA welding spot fault real-time diagnosis method is realized based on a high-precision FPGA welding spot fault real-time diagnosis device, the high-precision FPGA welding spot fault real-time diagnosis device comprises a state machine, and the state machine is provided with a port A, a port B, a port Clk-S, a port Clk-C, a port CntA and a port CntB;
the port A and the port B are respectively used for connecting two welding spot pins PinA and Pin B to be detected on the FPGA;
the port Clk-C is used for connecting a clock signal, controlling the states of the port A and the port B, controlling the port A or the port B to output a high level state and charging an external capacitor;
the port Clk-S is used for connecting a high-frequency clock sampling signal, sampling the signal of the port A or the port B, acquiring the state of the port A or the port B, and recording the corresponding sampling period number;
the port CntA is used for outputting a sampling signal period corresponding to the port A, and the port CntB is used for outputting a sampling signal period corresponding to the port B;
the state machine is also provided with a port RST, and the port RST is used for inputting a reset signal of a system;
the state machine comprises four working states during working, namely an idle state, an AWBR working state, a waiting state and an ARBW working state in sequence;
when the state machine is in an idle state, the port A and the port B output a low level state to discharge an external capacitor; when the state machine enters an AWBR working state, a clock signal of a port Clk-C controls a port A to output a high level state, an external capacitor is charged through the port A, meanwhile, a high-frequency clock sampling signal of the port Clk-S is used, the sampling frequency of the high-frequency clock is set to be 100MHz, a signal of a port B is sampled, and a sampling result is output through a port CntB; when the state machine enters a waiting state, the port A and the port B output a low level state again to discharge the external capacitor; when the state machine enters an ARBW working state, controlling a port B to output a high level state through a clock signal of a port Clk-C, charging an external capacitor through the port B, simultaneously sampling a signal of a port A through a high-frequency clock sampling signal of the port Clk-S, and outputting a sampling result through a port CntA;
the high-precision FPGA welding spot fault real-time diagnosis method comprises the following steps:
step S1, firstly, establishing an FPGA welding spot fault diagnosis method model, wherein the FPGA welding spot fault diagnosis method model comprises two pins PinA and PinB of an FPGA welding spot, and the two pins PinA and PinB are both connected with an external capacitor;
step S2, setting the pin PinA and the pin PinB to output low level state, and discharging the external capacitor;
step S3, setting a pin PinA to output a high level state, and charging an external capacitor;
step S4, sampling a signal of a pin PinB by adopting a high-frequency clock, and acquiring the state of the pin PinB in real time;
step S5, when pin PinB outputs high level state, recording the number of cycles of high frequency clock sampling, calculating the resistance value of FPGA welding point corresponding to pin PinA,
wherein, the resistance value R of the FPGA welding spot corresponding to the pin PinA is
Wherein,VthreshIs the critical voltage value, V, of pin PinB from low level state to high level state1The final voltage of the external capacitor in the charging process is obtained, C is the capacitance value of the external capacitor, n is the period number of the high-frequency clock, and f is the sampling frequency of the high-frequency clock;
step S6, judging whether the FPGA welding spot is in failure or not according to the resistance value of the FPGA welding spot calculated in the step S5, and predicting the service life of the FPGA welding spot;
step S7, setting the pin PinA and the pin PinB to output low level state again, and discharging the external capacitor;
and step S8, setting the pin PinB to output a high level state, charging the external capacitor, obtaining the resistance value of the FPGA welding spot corresponding to the pin PinB by referring to the methods in the steps 4 and 5, judging whether the FPGA welding spot is in fault, and predicting the service life of the FPGA welding spot.
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