CN116359712A - Wafer test platform and detection method thereof - Google Patents
Wafer test platform and detection method thereof Download PDFInfo
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- CN116359712A CN116359712A CN202310483823.3A CN202310483823A CN116359712A CN 116359712 A CN116359712 A CN 116359712A CN 202310483823 A CN202310483823 A CN 202310483823A CN 116359712 A CN116359712 A CN 116359712A
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- 238000012360 testing method Methods 0.000 title claims abstract description 50
- 238000001514 detection method Methods 0.000 title claims abstract description 32
- 239000000523 sample Substances 0.000 claims abstract description 108
- 230000007246 mechanism Effects 0.000 claims abstract description 65
- 239000013307 optical fiber Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 27
- 238000012216 screening Methods 0.000 claims description 12
- 238000007689 inspection Methods 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 8
- 238000007781 pre-processing Methods 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 5
- 238000004364 calculation method Methods 0.000 claims description 4
- 238000003708 edge detection Methods 0.000 claims description 4
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- 238000012545 processing Methods 0.000 claims description 4
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2887—Features relating to contacting the IC under test, e.g. probe heads; chucks involving moving the probe head or the IC under test; docking stations
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2891—Features relating to contacting the IC under test, e.g. probe heads; chucks related to sensing or controlling of force, position, temperature
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
A wafer test platform and a detection method thereof, the wafer test platform comprises: a carrying tray; a camera mechanism for calibrating a position of the wafer; the chip angle adjusting mechanism is used for adjusting the horizontal direction angle of the wafer; the chip position adjusting mechanism is used for adjusting the horizontal position of the wafer; the probe assembly is provided with at least two probes; the probe assembly is used for simultaneously detecting a plurality of chips on the wafer and testing dark field IV curves of the chips after the chips on the wafer are powered on; and the optical fiber testing mechanism is used for enabling standard light beams emitted by the optical fibers to be incident on the photosensitive surface of the chip and electrifying the light field data of the chip. Through the wafer test platform, a plurality of chips on the wafer can be detected together, and the problem of low detection efficiency of the existing wafer is solved.
Description
Technical Field
The invention relates to the technical field of chip detection, in particular to a wafer test platform and a detection method thereof.
Background
When the photoelectric performance of the chips is detected, each chip on the wafer needs to be respectively electrified to perform an IV curve under the dark field of the chip. And after the test is finished, the optical fiber is moved to the position right above the chip to be tested, a standard light beam is adopted to be incident on the photosensitive surface of the chip, and the light field data of the chip is electrified. After the test is finished, the probe is adjusted to be electrified, so that dark field and light field data of the chip to be tested next are tested, and the test is repeated.
Because, the above process needs to be repeated multiple times during the wafer inspection process until all individual chips on the wafer are inspected. The conventional wafer test platform cannot realize the detection of a plurality of chips on a wafer together, so that the conventional wafer test platform has the problem of low detection efficiency. Those skilled in the art are highly required to improve the inspection efficiency of wafers.
Disclosure of Invention
The invention aims to provide a wafer test platform and a test method thereof, which are used for solving the problem that the conventional wafer test equipment cannot realize the simultaneous detection of a plurality of chips on a wafer, so that the conventional wafer test efficiency is low. To this end, the present invention provides a wafer test platform, comprising:
the bearing plate is used for bearing the wafer;
a camera mechanism for calibrating a position of the wafer, the camera mechanism comprising: a vertical camera disposed toward the wafer;
the chip angle adjusting mechanism is in transmission connection with the bearing disc and drives the bearing disc to rotate in the horizontal direction by an angle so as to adjust the horizontal direction angle of the wafer;
the chip position adjusting mechanism is in transmission connection with the bearing disc and drives the bearing disc to translate in the horizontal direction so as to adjust the horizontal position of the wafer;
the probe assembly is provided with at least two probes; the probe assembly is used for simultaneously detecting a plurality of chips on the wafer and testing dark field IV curves of the chips after the chips on the wafer are powered on;
and the optical fiber testing mechanism is used for enabling standard light beams emitted by the optical fibers to be incident on the photosensitive surface of the chip and electrifying the light field data of the chip.
Optionally, the probe assembly includes: a probe fixing seat and a probe arranged on the probe fixing seat;
the probe assembly is connected with the probe assembly driving structure through an elastic connecting piece.
Optionally, the elastic connecting piece is a spring sleeved on the telescopic rod; and two ends of the spring are respectively connected with the probe fixing seat and the probe assembly driving structure.
Optionally, the probe assembly driving structure includes:
a probe holder comprising: a fixed part and a moving part;
the probe fixing seat is fixedly arranged on the moving arm;
the first horizontal push rod is arranged on the fixed part and used for pushing the moving part to drive the probe fixing seat to move in the first horizontal direction;
the second horizontal push rod is arranged on the fixed part and used for pushing the moving part to drive the probe fixing seat to move in a second horizontal direction;
a height positioning component comprising: the vertical push rod is arranged on the fixed part and pushes the moving part to drive the probe fixing seat to move in the vertical direction;
the first horizontal push rod, the second horizontal push rod and the height positioning component are fixed in a limiting mode through limiting pins respectively.
Optionally, the carrying disc is arranged on the chip carrier; the chip position adjustment mechanism includes:
the X-axis driving mechanism drives the chip carrier to translate in the X-axis direction;
and the Y-axis driving mechanism drives the chip carrier to translate in the Y-axis direction.
A wafer inspection method comprising the steps of:
s1, detecting the position of a wafer: acquiring outline information of a wafer so as to judge whether array chips on the wafer incline or not;
s2, adjusting the wafer fillet degree: driving the bearing disc to rotate through a chip angle adjusting mechanism according to the wafer position detection information, and adjusting the angle of the wafer;
s3, detecting the wafer offset: acquiring the coordinate information of chips on the wafer, and comparing the coordinate information with system set coordinate information to determine the horizontal position offset of the wafer;
s4, adjusting the wafer offset: driving the carrying disc to translate through a chip position adjusting mechanism according to the wafer position detection information, and adjusting the position of the wafer;
s5, detecting a wafer: simultaneously detecting a plurality of chips on the wafer through a probe assembly with at least two probes, so as to test dark field IV curves of the chips; and, the standard light beam sent out by the optical fiber testing mechanism is incident on the photosensitive surface of the chip, and the optical field data of the chip is electrified.
Optionally, the step S1 specifically includes the following steps:
s101, moving the wafer to the center of a camera view of an image detection mechanism, and acquiring a clear image through the camera;
s102, performing image preprocessing, converting a clear image into a gray level image, and performing smoothing processing on the image through a Gaussian blur algorithm;
s103, carrying out Canny operator edge detection on the image after image preprocessing, and determining the contour type, the contour center point position and the contour size of each chip on the wafer; the contour size includes: a length value and a width value of the chip outline;
s104, performing chip inclination judgment.
Optionally, in step S104, specifically includes:
screening out a first core in the length direction of the waferSheet coordinates (x) 1 ，y 1 ) And the last chip coordinate (x n ，y n ) The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the two chip coordinate connecting lines of the wafer are parallel to the connecting lines of the preset coordinates, the wafer is not inclined in position, and step S3 is performed; or alternatively, the first and second heat exchangers may be,
screening out the first chip coordinate (x 1 ，y 1 ) And the last chip coordinate (x j ，y j ) The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the connecting line of the coordinates of the two chips of the wafer is not parallel to the connecting line of the preset coordinates, the array chip position on the wafer is inclined, and the inclination angle of the wafer on the carrier is calculated; the inclination Angle is Angle, and the calculation formula is as follows:
optionally, in step S1, further includes: step S105 provided after step S104; after step S105, if the wafer has no position inclination, step S3 is performed;
s105, verifying wafer fillet degree: and re-acquiring the outline information of the wafer so as to judge whether the array chips on the wafer are inclined.
Optionally, the wafer corner verification includes:
screening out the first chip coordinate (x 1 ，y 1 ) And the last chip coordinate (x j ，y j ) The method comprises the steps of carrying out a first treatment on the surface of the According to the coordinates of the two chips compared with the preset coordinates, if the coordinates (x 1 ，y 1 ) And chip coordinates (x) j ，y j ) The wafer is not inclined when the connecting line is parallel to a preset coordinate connecting line, otherwise, the wafer is inclined, and whether the wafer is inclined or not is judged;
if the wafer is not inclined, executing step S5;
if the wafer is tilted, the steps S101 to S104 are re-performed.
The technical scheme of the invention has the following advantages:
1. the wafer test platform provided by the invention comprises:
the bearing plate is used for bearing the wafer;
a camera mechanism for calibrating a position of the wafer, the camera mechanism comprising: a vertical camera disposed toward the wafer;
the chip angle adjusting mechanism is in transmission connection with the bearing disc and drives the bearing disc to rotate in the horizontal direction by an angle so as to adjust the horizontal direction angle of the wafer;
the chip position adjusting mechanism is in transmission connection with the bearing disc and drives the bearing disc to translate in the horizontal direction so as to adjust the horizontal position of the wafer;
the probe assembly is provided with at least two probes; the probe assembly is used for simultaneously detecting a plurality of chips on the wafer and testing dark field IV curves of the chips after the chips on the wafer are powered on;
and the optical fiber testing mechanism is used for enabling standard light beams emitted by the optical fibers to be incident on the photosensitive surface of the chip and electrifying the light field data of the chip.
In the invention, the plurality of chips on the wafer are detected simultaneously by the plurality of probes on the probe assembly, so that the dark field IV curve detection efficiency of the plurality of chips on the wafer can be effectively improved. Thereby improving the detection efficiency of the whole wafer test platform.
2. The invention provides a wafer test platform, the probe assembly includes: a probe fixing seat and a probe arranged on the probe fixing seat; the probe assembly is connected with the probe assembly driving structure through an elastic connecting piece. The elastic connecting piece is a spring sleeved on the telescopic rod; and two ends of the spring are respectively connected with the probe fixing seat and the probe assembly driving structure.
According to the invention, each probe on the probe assembly can have proper elasticity through the elastic connecting piece, so that the probe can be better contacted with the surface of the chip, and the detection accuracy is further improved.
3. The invention provides a wafer test platform, the probe assembly driving structure comprises:
a probe holder comprising: a fixed part and a moving part;
the probe fixing seat is fixedly arranged on the moving arm;
the first horizontal push rod is arranged on the fixed part and used for pushing the moving part to drive the probe fixing seat to move in the first horizontal direction;
the second horizontal push rod is arranged on the fixed part and used for pushing the moving part to drive the probe fixing seat to move in a second horizontal direction;
a height positioning component comprising: the vertical push rod is arranged on the fixed part and pushes the moving part to drive the probe fixing seat to move in the vertical direction;
the first horizontal push rod, the second horizontal push rod and the height positioning component are fixed in a limiting mode through limiting pins respectively.
According to the invention, the fixing part and the moving part are respectively arranged on the probe frame, and the moving arm is respectively driven to move in the horizontal direction and the vertical direction through the first horizontal push rod, the second horizontal push rod and the height positioning part, so that the moving position is limited and fixed through the limiting bolt. The above structure can simply and reliably change the position of the moving arm.
4. The wafer test platform provided by the invention is characterized in that the bearing disc is arranged on the chip carrier; the chip position adjustment mechanism includes: the X-axis driving mechanism drives the chip carrier to translate in the X-axis direction; and the Y-axis driving mechanism drives the chip carrier to translate in the Y-axis direction.
In the invention, the X-axis driving mechanism and the Y-axis driving mechanism can drive the chip carrier to move in the horizontal direction, so as to adjust the position of the chip carrier.
5. The wafer detection method provided by the invention comprises the following steps:
s1, detecting the position of a wafer: acquiring outline information of a wafer so as to judge whether array chips on the wafer incline or not;
s2, adjusting the wafer fillet degree: driving the bearing disc to rotate through a chip angle adjusting mechanism according to the wafer position detection information, and adjusting the angle of the wafer;
s3, detecting the wafer offset: acquiring the coordinate information of chips on the wafer, and comparing the coordinate information with system set coordinate information to determine the horizontal position offset of the wafer;
s4, adjusting the wafer offset: driving the carrying disc to translate through a chip position adjusting mechanism according to the wafer position detection information, and adjusting the position of the wafer;
s5, detecting a wafer: simultaneously detecting a plurality of chips on the wafer through a probe assembly with at least two probes, so as to test dark field IV curves of the chips; and, the standard light beam sent out by the optical fiber testing mechanism is incident on the photosensitive surface of the chip, and the optical field data of the chip is electrified.
In the prior art, when performance detection is performed on chips, each chip needs to be identified respectively, and chip detection efficiency is seriously affected. In order to solve the above problems, in the present invention, the wafer position detection is used to determine the chip profile information, so as to determine whether the array chips on the wafer are inclined. Wafer corner adjustment is achieved if tilted. And then, detecting the offset of the array chips on the wafer and finishing the offset adjustment of the array chips. The wafer rapid positioning adjustment method can realize the position correction of all chips only through one-time rotation and translation operation. After the optimal position of the array chip is determined, the dark field IV curve of the chip and the light field data of the chip are respectively tested through the probe assembly and the optical fiber testing mechanism. The probe assembly with a plurality of probes can effectively improve the detection efficiency of the wafer.
6. The wafer detection method provided by the invention specifically comprises the following steps in step S1:
s101, moving the wafer to the center of a camera view of an image detection mechanism, and acquiring a clear image through the camera;
s102, performing image preprocessing, converting a clear image into a gray level image, and performing smoothing processing on the image through a Gaussian blur algorithm;
s103, carrying out Canny operator edge detection on the image after image preprocessing, and determining the contour type, the contour center point position and the contour size of each chip on the wafer; the contour size includes: a length value and a width value of the chip outline;
s104, performing chip inclination judgment.
In the invention, the contour type, the contour center point position and the contour size of each chip on the wafer can be obtained by the method. Thereby providing data support for rotation and translation of the array chip positions on the wafer in the next step.
7. The wafer detection method provided by the invention specifically comprises the following steps in step S104:
screening out the first chip coordinate (x 1 ，y 1 ) And the last chip coordinate (x n ，y n ) The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the two chip coordinate connecting lines of the wafer are parallel to the connecting lines of the preset coordinates, the wafer is not inclined in position, and step S3 is performed; or alternatively, the first and second heat exchangers may be,
screening out the first chip coordinate (x 1 ，y 1 ) And the last chip coordinate (x j ，y j ) The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the connecting line of the coordinates of the two chips of the wafer is not parallel to the connecting line of the preset coordinates, the array chip position on the wafer is inclined, and the inclination angle of the wafer on the carrier is calculated; the inclination Angle is Angle, and the calculation formula is as follows:
in the present invention, the first chip coordinate (x 1 ，y 1 ) And the last chip coordinate (x n ，y n ) The method comprises the steps of carrying out a first treatment on the surface of the And comparing the measured coordinates of the two chips with standard preset coordinates, and if the straight line formed by connecting the two chips is parallel to the straight line formed by connecting the preset coordinates, the chips are not inclined, otherwise, the chips are inclined. Then, if the chip inclination is measured, the inclination angle of the array chip can be measured according to the inclination angle.
8. The wafer detection method provided by the invention further comprises the following steps in step S1: step S105 provided after step S104; after step S105, if the wafer has no position inclination, step S3 is performed; s105, verifying wafer fillet degree: and re-acquiring the outline information of the wafer so as to judge whether the array chips on the wafer are inclined.
Wafer corner verification includes: screening out the first chip coordinate (x 1 ，y 1 ) And the last chip coordinate (x j ，y j ) The method comprises the steps of carrying out a first treatment on the surface of the According to the coordinates of the two chips compared with the preset coordinates, if the coordinates (x 1 ，y 1 ) And chip coordinates (x) j ，y j ) The wafer is not inclined when the connecting line is parallel to a preset coordinate connecting line, otherwise, the wafer is inclined, and whether the wafer is inclined or not is judged; if the wafer is not inclined, executing step S5; if the wafer is tilted, the steps S101 to S104 are re-performed.
In the present invention, the first chip coordinate (x 1 ，y 1 ) And the last chip coordinate (x j ，y j ) Connecting the measured two coordinates to the array chip widthCompared with the connecting line of the preset coordinates in the degree direction, if the two are parallel, the chip has no position inclination, otherwise the chip is inclined. The method can effectively verify whether the wafer rotates in place or not and finish the work of correcting the inclination of the chip or not.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic perspective view of a wafer test platform according to the present invention;
FIG. 2 is a schematic perspective view of a driving structure of a probe assembly with a probe assembly according to the present invention;
FIG. 3 is a schematic perspective view of an optical fiber testing mechanism according to the present invention;
fig. 4 is a schematic perspective view of a fixing seat provided with a plurality of probes according to the present invention;
FIG. 5 is a schematic diagram of a connection structure between a probe holder and an elastic connector according to the present invention;
FIG. 6 is a schematic view of a tilted wafer position provided by the present invention;
fig. 7 is a flow chart of a wafer inspection method according to the present invention.
Reference numerals illustrate:
1-a carrying tray; 2-wafer; 3-vertical camera; 4-a chip angle adjusting mechanism; a 5-probe assembly; 6-probe; 7-an optical fiber testing mechanism; 8-a probe fixing seat; 9-elastic connection; 10-a probe assembly drive structure; 11-a fixing part; 12-a moving part; 13-a moving arm; 14-a first horizontal push rod; 15-a second horizontal push rod; 16-vertical push rod; 17-limiting pins; 18-a chip carrier; a 19-X axis driving mechanism; 20-Y axis driving mechanism.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
A wafer test platform is described, as shown in fig. 1, comprising:
a carrying tray 1 for carrying wafers 2; the bearing disc 1 is arranged on a chip carrier 18;
a camera mechanism for calibrating the position of the wafer 2, the camera mechanism comprising: a vertical camera 3 disposed toward the wafer 2;
the chip angle adjusting mechanism 4 is in transmission connection with the bearing disc 1 and drives the bearing disc 1 to rotate in the horizontal direction for adjusting the horizontal direction angle of the wafer 2;
the chip position adjusting mechanism is in transmission connection with the bearing disc 1 and drives the bearing disc 1 to translate in the horizontal direction so as to adjust the horizontal position of the wafer 2; the chip position adjustment mechanism shown in fig. 1 includes: the X-axis driving mechanism 19, wherein the X-axis driving mechanism 19 drives the chip carrier 18 to translate in the X-axis direction; the Y-axis driving mechanism 20, wherein the Y-axis driving mechanism 20 drives the chip carrier 18 to translate in the Y-axis direction;
the probe assembly 5 is provided with at least two probes 6; the probe assembly 5 is used for simultaneously detecting a plurality of chips on the wafer 2 and testing dark field IV curves of the chips after the chips on the wafer 2 are powered up. The probe assembly 5 as shown in fig. 4 and 5 includes: a probe holder 8, and a probe 6 provided on the probe holder 8; the probe assembly 5 is connected to a probe assembly driving structure 10 by means of an elastic connection 9. The elastic connecting piece 9 is a spring sleeved on the telescopic rod; both ends of the spring are respectively connected with the probe fixing seat 8 and the probe assembly driving structure 10;
the probe assembly driving structure 10 is used for driving the joint of the probe assembly 5 and the array chip on the wafer 2; the probe assembly driving structure 10 as shown in fig. 2 includes: a probe holder comprising: a fixed part 11 and a moving part 12; a moving arm 13, wherein the probe fixing seat 8 is fixedly arranged on the moving arm 13; a first horizontal pushing rod 14, disposed on the fixed portion 11, for pushing the moving portion 12 to drive the probe fixing seat 8 to move in a first horizontal direction; a second horizontal pushing rod 15, disposed on the fixed portion 11, for pushing the moving portion 12 to drive the probe fixing seat 8 to move in a second horizontal direction; a height positioning component comprising: a vertical push rod 16 provided on the fixing portion 11, the vertical push rod 16 pushing the moving portion 12 to drive the probe fixing seat 8 to move in a vertical direction; the first horizontal push rod 14, the second horizontal push rod 15 and the height positioning component are respectively fixed in a limiting way through a limiting bolt 17;
the optical fiber testing mechanism 7, as shown in fig. 3, the standard light beam emitted by the optical fiber testing mechanism 7 is incident on the photosensitive surface of the chip, and the optical field data of the chip is electrified.
The wafer inspection method shown in fig. 7 specifically includes the following steps:
s1, detecting the position of a wafer: acquiring outline information of the wafer 2 so as to judge whether the array chips on the wafer 2 are inclined or not;
s2, adjusting the wafer fillet degree: according to the position detection information of the wafer 2, the carrier plate 1 is driven to rotate through the chip angle adjusting mechanism 4, and the angle of the wafer 2 is adjusted;
s3, detecting the wafer offset: acquiring chip coordinate information on the wafer 2, and comparing the chip coordinate information with system set coordinate information to determine the horizontal position offset of the wafer 2;
s4, adjusting the wafer offset: driving the carrying disc 1 to translate through a chip position adjusting mechanism according to the position detection information of the wafer 2, and adjusting the position of the wafer 2;
s5, detecting a wafer: simultaneously detecting a plurality of chips on the wafer 2 through a probe assembly 5 with at least two probes 6, so as to test dark field IV curves of the chips; and, the standard light beam sent out by the optical fiber testing mechanism 7 is incident on the photosensitive surface of the chip, and the optical field data of the chip is electrified.
In this embodiment, the following steps are specifically included in step S1:
s101, moving the wafer 2 to the center of a camera view of an image detection mechanism, and acquiring a clear image through the camera;
s102, performing image preprocessing, converting a clear image into a gray level image, and performing smoothing processing on the image through a Gaussian blur algorithm;
s103, carrying out Canny operator edge detection on the image after image preprocessing, and determining the contour type, the contour center point positions x and y and the contour size of each chip on the wafer 2; the contour size includes: a length value and a width value of the chip outline;
s104, judging the inclination of the chip;
s105, verifying wafer fillet degree: and re-acquiring the outline information of the wafer 2 so as to judge whether the array chips on the wafer 2 are inclined. After step S105, if the wafer 2 is not tilted, step S3 is performed.
In this embodiment, as shown in fig. 6, in step S104, specifically, it includes:
screening out the first chip coordinate x in the length direction of the wafer 2 1 ，y 1 And the last chip coordinate x in the length direction of the wafer 2 n ，y n The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the two chip coordinate connecting lines of the wafer 2 are parallel to the connecting lines of the preset coordinates, the wafer 2 is not inclined in position, and step S3 is performed; or alternatively, the first and second heat exchangers may be,
screening out the first chip coordinate x in the length direction of the wafer 2 1 ，y 1 And the last chip coordinate x in the length direction of the wafer 2 j ，y j The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the connecting line of the coordinates of the two chips of the wafer 2 is not parallel to the connecting line of the preset coordinates, the array chip position on the wafer 2 is inclined, and the inclination angle of the wafer 2 on the carrier is calculated; the inclination Angle is Angle, and the calculation formula is as follows:
in this embodiment, as shown in fig. 6, the wafer corner verification includes:
screening out the first chip coordinate x in the length direction of the wafer 2 1 ，y 1 And the last chip coordinate x in the width direction of the wafer 2 j ，y j The method comprises the steps of carrying out a first treatment on the surface of the According to the coordinate of the two chips compared with the preset coordinate, if the coordinate x of the chips 1 ，y 1 And chip coordinate x j ，y j The wafer 2 is not inclined when the connecting line is parallel to a preset coordinate connecting line, otherwise, the wafer 2 is inclined, and whether the wafer 2 is inclined or not is judged;
if the wafer 2 is not inclined, executing step S5;
if the wafer 2 is tilted, the steps S101 to S104 are re-performed.
Of course, in the present embodiment, the connection manner of the probe assembly 5 and the probe assembly driving structure 10 is not specifically limited, and in other embodiments, the probe assembly 5 is directly connected to the probe assembly driving structure 10 without using an elastic mechanism.
Of course, in the present embodiment, the connection manner of the probe assembly 5 and the probe assembly driving structure 10 is not particularly limited, and in other embodiments, a rubber pad for elastically connecting the probe assembly 5 and the probe assembly driving structure 10 may be further disposed at a connection position of the two.
Of course, in the present embodiment, whether or not step S105 is provided after step S104 is not particularly limited, and in other embodiments, chip inclination determination is performed in step S104; if the two chip coordinate connecting lines of the wafer 2 are parallel to the connecting lines of the preset coordinates, the wafer 2 has no position inclination, and the step S3 is directly performed without going through the step S105.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (10)
1. A wafer test platform, comprising:
a carrying tray (1) for carrying a wafer (2);
camera mechanism for calibrating the position of the wafer (2), the camera mechanism comprising: a vertical camera (3) disposed toward the wafer (2);
the chip angle adjusting mechanism (4) is in transmission connection with the bearing disc (1) and drives the bearing disc (1) to rotate by an angle in the horizontal direction so as to adjust the horizontal direction angle of the wafer (2);
the chip position adjusting mechanism is in transmission connection with the bearing disc (1) and drives the bearing disc (1) to translate in the horizontal direction so as to adjust the horizontal position of the wafer (2);
the probe assembly (5), at least two probes (6) are arranged on the probe assembly (5); the probe assembly (5) is used for simultaneously detecting a plurality of chips on the wafer (2) and testing dark field IV curves of the chips after the chips on the wafer (2) are powered on;
and the optical fiber testing mechanism (7) is used for enabling standard light beams emitted by the optical fibers to be incident on the photosensitive surface of the chip and electrifying the light field data of the chip.
2. Wafer test platform according to claim 1, characterized in that the probe assembly (5) comprises: a probe fixing seat (8) and a probe (6) arranged on the probe fixing seat (8);
the probe assembly (5) is connected with a probe assembly driving structure (10) through an elastic connecting piece (9).
3. Wafer test platform according to claim 2, characterized in that the elastic connection (9) is a spring sleeved on a telescopic rod; and two ends of the spring are respectively connected with the probe fixing seat (8) and the probe assembly driving structure (10).
4. Wafer test platform according to claim 2, wherein the probe assembly drive structure (10) comprises:
a probe holder comprising: a fixed part (11) and a moving part (12);
a moving arm (13), wherein the probe fixing seat (8) is fixedly arranged on the moving arm (13);
a first horizontal push rod (14) arranged on the fixed part (11) and used for pushing the moving part (12) so as to drive the probe fixing seat (8) to move in a first horizontal direction;
the second horizontal push rod (15) is arranged on the fixed part (11) and is used for pushing the moving part (12) so as to drive the probe fixing seat (8) to move in the second horizontal direction;
a height positioning component comprising: a vertical push rod (16) arranged on the fixed part (11), wherein the vertical push rod (16) pushes the moving part (12) to drive the probe fixing seat (8) to move in the vertical direction;
the first horizontal push rod (14), the second horizontal push rod (15) and the height positioning component are respectively fixed in a limiting mode through a limiting bolt (17).
5. Wafer test platform according to claim 1, characterized in that the carrier tray (1) is arranged on a chip carrier (18); the chip position adjustment mechanism includes:
the X-axis driving mechanism (19), wherein the X-axis driving mechanism (19) drives the chip carrier (18) to translate in the X-axis direction;
and the Y-axis driving mechanism (20) drives the chip carrier (18) to translate in the Y-axis direction.
6. A wafer inspection method for using the wafer test platform of claim 1, comprising the steps of:
s1, detecting the position of a wafer: acquiring outline information of a wafer (2) so as to judge whether array chips on the wafer (2) incline or not;
s2, adjusting the wafer fillet degree: according to the position detection information of the wafer (2), the carrier disc (1) is driven to rotate through a chip angle adjusting mechanism (4), and the angle of the wafer (2) is adjusted;
s3, detecting the wafer offset: acquiring chip coordinate information on the wafer (2), and comparing the chip coordinate information with system set coordinate information to determine the horizontal position offset of the wafer (2);
s4, adjusting the wafer offset: driving the carrying disc (1) to translate through a chip position adjusting mechanism according to the position detection information of the wafer (2) to adjust the position of the wafer (2);
s5, detecting a wafer: simultaneously detecting a plurality of chips on the wafer (2) through a probe assembly (5) with at least two probes (6), so as to test dark field IV curves of the chips; and, the standard light beam sent out by the optical fiber testing mechanism (7) is incident on the photosensitive surface of the chip, and the optical field data of the chip is electrified.
7. The wafer inspection method according to claim 6, wherein in step S1, the method specifically comprises the steps of:
s101, moving the wafer (2) to the center of a camera view of an image detection mechanism, and acquiring a clear image through the camera;
s102, performing image preprocessing, converting a clear image into a gray level image, and performing smoothing processing on the image through a Gaussian blur algorithm;
s103, carrying out Canny operator edge detection on the image after image preprocessing, and determining the contour type, contour center point position (x, y) and contour size of each chip on the wafer (2); the contour size includes: a length value and a width value of the chip outline;
s104, performing chip inclination judgment.
8. The method according to claim 7, wherein in step S104, specifically:
screening out the first chip coordinate (x) in the length direction of the wafer (2) 1 ，y 1 ) And the last chip coordinate (x) in the length direction of the wafer (2) n ，y n ) The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the two chip coordinate connecting lines of the wafer (2) are parallel to the connecting lines of the preset coordinates, the wafer (2) is not inclined in position, and step S3 is performed; or alternatively, the first and second heat exchangers may be,
screening out the first chip coordinate (x) in the length direction of the wafer (2) 1 ，y 1 ) And the last chip coordinate (x) in the length direction of the wafer (2) j ，y j ) The method comprises the steps of carrying out a first treatment on the surface of the Comparing the coordinates of the two chips with preset coordinates to judge whether the chips incline or not; if the connecting line of the coordinates of the two chips of the wafer (2) is not parallel to the connecting line of the preset coordinates, the array chip position on the wafer (2) is inclined, and the inclination angle of the wafer (2) on the carrier is calculated; the inclination Angle is Angle, and the calculation formula is as follows:
9. the wafer inspection method according to claim 7, further comprising, in step S1: step S105 provided after step S104; step S3 is performed if the wafer (2) is not inclined after the step S105;
s105, verifying wafer fillet degree: and re-acquiring the outline information of the wafer (2) so as to judge whether the array chips on the wafer (2) are inclined.
10. The wafer inspection method of claim 9, wherein the wafer corner verification comprises:
screening out the first chip coordinate (x) in the length direction of the wafer (2) 1 ，y 1 ) And the last chip coordinate (x) in the width direction of the wafer (2) j ，y j ) The method comprises the steps of carrying out a first treatment on the surface of the According to the coordinates of the two chips compared with the preset coordinates, if the coordinates (x 1 ，y 1 ) And chip coordinates (x) j ，y j ) The wafer (2) is not inclined when the connecting line is parallel to a preset coordinate connecting line, otherwise, the wafer (2) is inclined, and whether the wafer (2) is inclined or not is judged;
if the wafer (2) is not inclined, executing step S5;
if the wafer (2) is tilted, the steps S101 to S104 are re-executed.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116883515A (en) * | 2023-09-06 | 2023-10-13 | 菲特（天津）检测技术有限公司 | Optical environment adjusting method and optical calibration device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116883515A (en) * | 2023-09-06 | 2023-10-13 | 菲特（天津）检测技术有限公司 | Optical environment adjusting method and optical calibration device |
| CN116883515B (en) * | 2023-09-06 | 2024-01-16 | 菲特（天津）检测技术有限公司 | Optical environment adjusting method and optical calibration device |
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