CN116346270A - Method and application for supporting time synchronization of Serdes overclock - Google Patents

Method and application for supporting time synchronization of Serdes overclock Download PDF

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Publication number
CN116346270A
CN116346270A CN202111602566.8A CN202111602566A CN116346270A CN 116346270 A CN116346270 A CN 116346270A CN 202111602566 A CN202111602566 A CN 202111602566A CN 116346270 A CN116346270 A CN 116346270A
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ptp
serdes
message
time
frame start
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贺伟
王东
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Nanjing Shengke Communication Co ltd
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Nanjing Shengke Communication Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

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Abstract

The invention discloses a method for supporting time synchronization of Serdes overclocking and application thereof, wherein the method comprises the following steps: inserting a PTP mark according to a preset period, and acquiring the interval between the PTP mark and a frame start delimiter of a PTP message; calculating the sending time of the frame start delimiter of the PTP message on a Serdes parallel interface; and performing cross-clock domain processing according to the sending time, and forwarding the processed sending time through a following message. According to the method, clock synchronization can be performed in a 2-step mode under Serdes over-frequency, a PTP (precision time protocol) zone bit is periodically inserted in a receiving and transmitting direction to serve as a time stamp reference point for aligning a time stamp of a PTP message SFD (small form factor) point, the time stamp reference point of the PTP zone bit and an interval between the time stamp reference point and a frame start delimiter of the PTP message are stored in a FIFO readable by a CPU (Central processing Unit), so that the CPU reads the information and calculates accurate compensation time according to different Serdes rates, and ultra-high precision clock synchronization is achieved.

Description

Method and application for supporting time synchronization of Serdes overclock
Technical Field
The present invention relates to the field of communications, and more particularly, to a method and application for supporting time synchronization of Serdes overclocking.
Background
Ethernet has been widely used and rapidly developed over a long period of time from 10m,100m,1000mbps to 10gbps,40gbps,100gbps, to today's 25gbps,50gbps,200gbps,400gbps. While network rates are rapidly evolving, 5G networks have also met with a golden period of evolution. The low delay is a very important application of the 5G network, such as vehicle networking, unmanned, intelligent manufacturing, unmanned aerial vehicle delivery and other businesses all need to have the characteristics of ultra-low delay, high reliability and the like.
To ensure low latency in a 5G network, clock synchronization is required between network devices. Precision Time Protocol (PTP, precision time protocol) is a time synchronization protocol for high precision time synchronization between devices. In the PTP protocol, there are two modes, 2-step and 1-step. The 1-step mode needs to put the message in the Sync message for sending at the sending time of the device; the 2-step does not need to send the message in the Sync message at the sending time of the device, but instead sends the message in the follow-up message, but needs to record the residence time of the Sync message in the device for the follow-up message to use.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a method and application for supporting time synchronization of Serdes overtime, which solve the problem that the time stamp of a frame start delimiter of a message cannot be calculated with high precision under Serdes overtime, and further the time synchronization cannot be realized.
To achieve the above object, an embodiment of the present invention provides a method for supporting time synchronization of Serdes overclocking.
In one or more embodiments of the invention, the method comprises: inserting a PTP mark according to a preset period, and acquiring the interval between the PTP mark and a frame start delimiter of a PTP message; calculating the sending time of the frame start delimiter of the PTP message on a Serdes parallel interface; and performing cross-clock domain processing on the sending time, and forwarding the processed sending time through a following message.
In one or more embodiments of the present invention, obtaining the interval between the PTP flag and the start of frame delimiter of the PTP packet includes: detecting whether a flag bit of a frame start delimiter of the PTP message is a first value; if so, recording a PTP mark count into a first-in first-out queue readable by a CPU, wherein the PTP mark count is the distance between a PTP mark and a frame start delimiter of the PTP message.
In one or more embodiments of the present invention, calculating a transmission time of a start of frame delimiter of the PTP packet on a Serdes parallel interface includes: acquiring the transmission time TS of the PTP mark on the Serdes parallel interface pm The method comprises the steps of carrying out a first treatment on the surface of the Calculating the compensation time TS between the frame start delimiter and the PTP mark of the PTP message according to the port rate speed and the PTP mark count com Wherein TS com =ptp flag count 1024/speed; calculating the transmission time TS of the frame start delimiter of the PTP message on the Serdes parallel interface sfd Wherein TS sfd ＝TS pm +TS com 。
In one or more embodiments of the present invention, the clock domain crossing processing is performed on the sending time, and the processed sending time is forwarded by following a message, including: writing the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface into an asynchronous first-in first-out buffer; when the depth of the buffer reaches a preset threshold, a CPU is informed of reading the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface, wherein a clock domain read by the CPU works in a main clock domain of a chip; and the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface is put into a following message, and the following message is forwarded.
In another aspect of the invention, an apparatus supporting time synchronization of Serdes overclocking is provided that includes an acquisition module, a calculation module, and a cross-clock module.
The acquisition module is used for inserting the PTP mark according to a preset period and acquiring the interval between the PTP mark and the frame start delimiter of the PTP message.
And the calculating module is used for calculating the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface.
And the clock crossing module is used for performing clock crossing processing according to the sending time and forwarding the processed sending time through following the message.
In one or more embodiments of the present invention, the acquiring module is further configured to: detecting whether a flag bit of a frame start delimiter of the PTP message is a first value; if so, recording a PTP mark count into a first-in first-out queue readable by a CPU, wherein the PTP mark count is the distance between a PTP mark and a frame start delimiter of the PTP message.
In one or more embodiments of the invention, the computing module is further to: acquiring the transmission time TS of the PTP mark on the Serdes parallel interface pm The method comprises the steps of carrying out a first treatment on the surface of the Calculating the compensation time TS between the frame start delimiter and the PTP mark of the PTP message according to the port rate speed and the PTP mark count com Wherein TS com =ptp flag count 1024/speed; calculating the transmission time TS of the frame start delimiter of the PTP message on the Serdes parallel interface sfd Wherein TS sfd ＝TS pm +TS com 。
In one or more embodiments of the invention, the cross-clock module is further configured to: writing the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface into an asynchronous first-in first-out buffer; when the depth of the buffer reaches a preset threshold, a CPU is informed of reading the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface, wherein a clock domain read by the CPU works in a main clock domain of a chip; and the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface is put into a following message, and the following message is forwarded.
In another aspect of the present invention, there is provided an electronic device including: at least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of supporting Serdes over-clocking time synchronization as described above.
In another aspect of the invention, a computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, implements the steps of a method of supporting Serdes overclocking as described.
Compared with the prior art, according to the method and the application for supporting the time synchronization of the Serdes overtime, the clock synchronization can be carried out by using a 2-step mode under the Serdes overtime, the same clock synchronization architecture is adopted for different Ethernet rates of 1G-800G, a PTP mark is periodically inserted in the receiving and transmitting direction as a time stamp reference point for aligning with the time stamp of the frame start delimiter of the PTP message, and the time stamp reference point of the PTP mark and the interval between the PTP mark and the frame start delimiter of the PTP message are stored in the FIFO readable by the CPU, so that the CPU can read the information and calculate accurate compensation time according to different Serdes rates, and the ultra-high precision time synchronization effect is achieved.
According to the method and the application for supporting the Serdes over-frequency time synchronization, the jitter of the sending and receiving directions is optimized to the greatest extent, the cross-clock domain processing of the data paths and the time stamp paths of the receiving and sending directions is reduced, errors caused by CDC are reduced, and the clock synchronization precision is improved. In addition, by the method of calculating the compensation time by the CPU, complex calculation of the compensation time by the chip can be reduced, new upgrade of the over-frequency requirement can be rapidly realized, the type of the over-frequency is not limited, and the flexibility of the chip application can be improved.
Drawings
FIG. 1 is a flow chart of a method of supporting time synchronization of Serdes overclock in accordance with an embodiment of the present invention;
FIG. 2 is a block diagram of a method for supporting time synchronization of Serdes overclock in accordance with an embodiment of the present invention;
FIG. 3 is a chart of PTP flag counts for a method of supporting time synchronization for Serdes overclocking in accordance with an embodiment of the present invention;
FIG. 4 is a block diagram of an apparatus supporting Serdes over-clocking time synchronization in accordance with an embodiment of the present invention;
FIG. 5 is a hardware block diagram of a computing device supporting time synchronization of Serdes overclocking in accordance with one embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The following describes in detail the technical solutions provided by the embodiments of the present invention with reference to the accompanying drawings.
Example 1
As shown in fig. 1 to 3, a method for supporting time synchronization of Serdes overclocking in an embodiment of the present invention is described, and includes the following steps.
In step S101, a PTP flag is inserted according to a preset period, and an interval between the PTP flag and a frame start delimiter of a PTP packet is acquired.
As shown in fig. 2, when transmitting a PTP message, the tuning sublayer (RS) sets the PTP message flag to a first value, and transmits a 7-byte preamble (10101010) and a 1-byte start of frame delimiter SFD (10101011) before transmitting the message. The function of the preamble is to inform the receiver that a data frame arrives, so that the data frame is kept synchronous with the input clock, and the frame start delimiter is responsible for informing the receiver that the next field is the address of the destination host. The SFD marks the beginning of a message transmission and can find the beginning of a message as long as the SFD can be found.
The data bit width used by the MII interface in the RS transmit direction is 128 bytes, while the preamble and SFD are aligned by 4 bytes for 10G or 25G rates and by 8 bytes for 40G and above, so the location of the SFD is 32 possible above the MII interface. In order to find the exact position of the frame start delimiter of the PTP message, a periodic PTP flag signal, denoted PTP flag, is generated in the RS transmission direction by means of a PTP flag counter. The count unit of the counter is 128 bytes, i.e. each 1-up of the counter indicates that 128 bytes are transmitted. When the SFD flag bit of the PTP message is the first value, the value of the PTP flag counter is recorded and is recorded as a PTP flag count, and the PTP flag count is the interval between the PTP flag and the start of frame delimiter of the PTP message, as shown in FIG. 3.
In step S102, the transmission time of the start of frame delimiter of the PTP message on the Serdes parallel interface is calculated.
Since there is no way to find the start of frame delimiter of the message on the Serdes parallel interface, to obtain a high precision time stamp, the time stamp of the start of frame delimiter sending time of the message must be sampled on the Serdes parallel interface.
Therefore, in this embodiment, the time stamp of the PTP flag sending point is acquired on the Serdes parallel interface, and the time stamp, the PTP flag, the distance of the frame start delimiter of the PTP packet, and the port work rate are stored together in a FIFO (first in first out queue) readable by the CPU. When the CPU detects that the data exists in the FIFO, the data in the FIFO is read out, and the time stamp compensation is carried out according to the read information, so that the accurate time stamp of the sending point of the frame start delimiter of the message on the Serdes parallel interface is obtained.
Specifically, the PTP flag is transferred to the parallel interface of Serdes through the physical coding sublayer, and when the PTP flag on the parallel interface of Serdes is the first value (in this embodiment, the first value is 1), a time stamp is sampled, that is, the transmission time TS of the PTP flag on the parallel interface of Serdes pm At the same time, the transmission time is stored in a FIFO readable by the CPU. The CPU reads information from FIFO including TS pm A transmission interval (i.e., PTP flag count) between a start of frame delimiter and a PTP flag of a PTP message, and a port working rate speed. The CPU calculates the compensation time TS between the frame start delimiter and the PTP mark of the PTP message through the port rate and the PTP mark count com Wherein TS com =ptp flag count 1024/speed. Thus, the transmission time TS of the start of frame delimiter of PTP message on Serdes parallel interface sfd Transmission time TS on Serdes parallel interface for PTP flag pm Compensation time TS between start of frame delimiter and PTP flag of +PTP message com 。
Taking a 100Gbps port as an example, the sending time of the start-of-frame delimiter of the PTP message on the Serdes parallel interface is calculated from the Serdes non-over-frequency and Serdes over-frequency to 110Gbps respectively.
When the Serdes is not over-frequency at the 100Gbps port, the distance between the frame start delimiter of the PTP message and the PTP mark is 8 x 128 bits of PTP mark count, namely 1024 bits of PTP mark count, and 100Gbps indicates that 1ns can send 100 bits of data, so that the time required for sending 1024 bits of PTP mark count is 10.24ns of PTP mark count, namely TS at the rate of 100Gbps com PTP flag count 10.24ns. Therefore, the transmission time stamp of the start of frame delimiter of the PTP message on the Serdes parallel interface is TS sfd ＝TS pm +TS com . TS of other Port Rate sfd And can be obtained by the same calculation method, and will not be described in detail herein.
At 100Gbps port, when Serdes overturns to 110Gbps, the distance between the frame start delimiter and the PTP flag of the PTP packet is still 1024 bits, and 110Gbps indicates that 1ns can transmit 110 bits of data, so that at 110Gbps rate, the time required for transmitting the 1024 bits of the PTP flag count is 9.30ns, i.e., TS com The =ptp flag count is 9.30ns.
If the compensation time between the frame start delimiter and the PTP flag of the PTP message is calculated by the chip, the compensation time calculation at the rate is correspondingly increased when Serdes increases an over-frequency rate. And the Serdes over-frequency type supported by the chip is fixed, and when a new over-frequency requirement exists, the chip cannot be updated on line. The invention calculates the compensation time between the frame start delimiter and the PTP mark of the PTP message by the CPU, thereby not only avoiding the complex calculation of the compensation time by the chip, but also rapidly realizing the upgrade of the new over-frequency requirement, having no limitation on the type of the over-frequency, and improving the flexibility of the chip application.
In step S103, the transmission time is subjected to the clock domain crossing processing, and the processed transmission time is forwarded by following the message.
Under a 1GHz clock, calculating to obtain the frame start of the PTP messageTransmission time TS of delimiter on Serdes parallel interface sfd And writing the transmission time into an asynchronous first-in first-out buffer, when the depth of the buffer reaches a preset threshold value, reading the transmission time of the frame start delimiter of the PTP message on the Serdes parallel interface by a CPU, operating a clock domain read by the CPU on a main clock domain of a chip, and transmitting the transmission time of the frame start delimiter of the read PTP message on the Serdes parallel interface by the CPU through a following message, thereby realizing time synchronization based on PTP 2-step. In this embodiment, the time stamp path is subjected to clock crossing processing only once, so that errors brought by clock crossing domains are reduced, and clock synchronization accuracy can be improved.
As shown in FIG. 4, an apparatus for supporting time synchronization of Serdes overclocking according to an embodiment of the present invention is described.
In an embodiment of the present invention, the apparatus supporting the time synchronization of the Serdes overclocking includes an acquisition module 401, a calculation module 402, and a cross-clock module 403.
The obtaining module 401 is configured to insert a PTP flag according to a preset period, and obtain an interval between the PTP flag and a frame start delimiter of a PTP packet.
The calculating module 402 is configured to calculate a transmission time of a start of frame delimiter of the PTP packet on the Serdes parallel interface.
The clock crossing module 403 is configured to perform clock domain crossing processing according to the sending time, and forward the sending time after processing by following the message.
The acquisition module 401 is further configured to: detecting whether a flag bit of a frame start delimiter of a PTP message is a first value; if so, recording PTP mark count into CPU readable first-in first-out queue, wherein PTP mark count is the distance between PTP mark and frame start delimiter of PTP message.
The computing module 402 is also configured to: acquisition of the time TS of transmission of PTP markers on Serdes parallel interfaces pm The method comprises the steps of carrying out a first treatment on the surface of the Calculating the compensation time TS between the frame start delimiter and the PTP mark of the PTP message according to the port rate speed and the PTP mark count com Wherein TS com =ptp flag count 1024/speed; calculating the start of frame delimiter of PTP message at Serdes andtransmission time TS on line interface sfd Wherein TS sfd ＝TS pm +TS com 。
The cross clock module 403 is also configured to: writing the sending time of a frame start delimiter of a PTP message on a Serdes parallel interface into an asynchronous first-in first-out buffer; when the depth of the buffer reaches a preset threshold, notifying a CPU to read the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface, wherein a clock domain read by the CPU works in a main clock domain of the chip; and the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface is put into the following message, and the following message is forwarded.
FIG. 5 illustrates a hardware block diagram of a computing device 50 for supporting time synchronization of Serdes overclocking according to an embodiment of the present description. As shown in fig. 5, computing device 50 may include at least one processor 501, memory 502 (e.g., non-volatile memory), memory 503, and communication interface 504, and at least one processor 501, memory 502, memory 503, and communication interface 504 are connected together via bus 505. The at least one processor 501 executes at least one computer-readable instruction stored or encoded in the memory 502.
It should be appreciated that the computer-executable instructions stored in memory 502, when executed, cause at least one processor 501 to perform the various operations and functions described above in connection with fig. 1-5 in various embodiments of the present description.
In embodiments of the present description, computing device 50 may include, but is not limited to: personal computers, server computers, workstations, desktop computers, laptop computers, notebook computers, mobile computing devices, smart phones, tablet computers, cellular phones, personal Digital Assistants (PDAs), handsets, messaging devices, wearable computing devices, consumer electronic devices, and the like.
According to one embodiment, a program product, such as a machine-readable medium, is provided. The machine-readable medium may have instructions (i.e., elements described above implemented in software) that, when executed by a machine, cause the machine to perform the various operations and functions described above in connection with fig. 1-5 in various embodiments of the specification. In particular, a system or apparatus provided with a readable storage medium having stored thereon software program code implementing the functions of any of the above embodiments may be provided, and a computer or processor of the system or apparatus may be caused to read out and execute instructions stored in the readable storage medium.
According to the method and the application for supporting the time synchronization of the Serdes overtime, which are disclosed by the embodiment of the invention, clock synchronization can be carried out by using a 2-step mode under the Serdes overtime, the same clock synchronization architecture is adopted for different Ethernet rates of 1G-800G, a PTP mark is periodically inserted in a receiving and transmitting direction as a time stamp reference point for aligning with the time stamp of the start-of-frame delimiter of the PTP message, the time stamp reference point of the PTP mark and the interval between the time stamp reference point and the start-of-frame delimiter of the PTP message are stored in a FIFO readable by a CPU, so that the CPU can read the information and calculate accurate compensation time according to different Serdes rates, and the ultra-high precision time synchronization effect is achieved.
According to the method and the application for supporting the Serdes over-frequency time synchronization, the jitter of the sending and receiving directions is optimized to the greatest extent, the cross-clock domain processing of the data paths and the time stamp paths of the receiving and sending directions is reduced, errors caused by CDC are reduced, and the clock synchronization precision is improved. In addition, by the method of calculating the compensation time by the CPU, complex calculation of the compensation time by the chip can be reduced, new upgrade of the over-frequency requirement can be rapidly realized, the type of the over-frequency is not limited, and the flexibility of the chip application can be improved.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A method for supporting time synchronization of Serdes overclock, the method comprising:
inserting a PTP mark according to a preset period, and acquiring the interval between the PTP mark and a frame start delimiter of a PTP message;
calculating the sending time of the frame start delimiter of the PTP message on a Serdes parallel interface; and
and carrying out cross-clock domain processing on the sending time, and forwarding the processed sending time through a following message.
2. The method for supporting time synchronization of Serdes overclocking according to claim 1, wherein obtaining the interval between the PTP flag and the start of frame delimiter of the PTP message comprises:
detecting whether a flag bit of a frame start delimiter of the PTP message is a first value; if so, the first and second data are not identical,
and recording a PTP mark count into a first-in first-out queue readable by a CPU, wherein the PTP mark count is the distance between the PTP mark and a frame start delimiter of the PTP message.
3. The method for supporting time synchronization of Serdes overclock according to claim 1, wherein calculating the transmission time of the start of frame delimiter of the PTP message on the Serdes parallel interface comprises:
acquiring the transmission time TS of the PTP mark on the Serdes parallel interface pm ；
Calculating the compensation time TS between the frame start delimiter and the PTP mark of the PTP message according to the port rate speed and the PTP mark count com Wherein TS com =ptp flag count 1024/speed; and
calculating the transmission time TS of the frame start delimiter of the PTP message on the Serdes parallel interface sfd Wherein TS sfd ＝TS pm +TS com 。
4. The method for supporting time synchronization of Serdes overclock according to claim 1, wherein performing cross-clock domain processing on the transmission time and forwarding the processed transmission time by following a message, comprises:
writing the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface into an asynchronous first-in first-out buffer;
when the depth of the buffer reaches a preset threshold, a CPU is informed of reading the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface, wherein a clock domain read by the CPU works in a main clock domain of a chip; and
and the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface is put into a following message, and the following message is forwarded.
5. An apparatus for supporting time synchronization of Serdes overclock, the apparatus comprising:
the acquisition module is used for inserting a PTP mark according to a preset period and acquiring the interval between the PTP mark and a frame start delimiter of a PTP message;
the calculation module is used for calculating the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface; and
and the clock crossing module is used for performing clock crossing processing according to the sending time and forwarding the processed sending time through following the message.
6. The apparatus for supporting time synchronization of Serdes overclocking of claim 5, wherein the acquisition module is further configured to:
detecting whether a flag bit of a frame start delimiter of the PTP message is a first value; if so, the first and second data are not identical,
and recording a PTP mark count into a first-in first-out queue readable by a CPU, wherein the PTP mark count is the distance between the PTP mark and a frame start delimiter of the PTP message.
7. The apparatus for supporting time synchronization of Serdes overclocking of claim 5, wherein the computing module is further configured to:
acquiring the transmission time TS of the PTP mark on the Serdes parallel interface pm ；
Calculating the compensation time TS between the frame start delimiter and the PTP mark of the PTP message according to the port rate speed and the PTP mark count com Wherein TS com =ptp flag count 1024/speed; and
calculating the transmission time TS of the frame start delimiter of the PTP message on the Serdes parallel interface sfd Wherein TS sfd ＝TS pm +TS com 。
8. The apparatus for supporting time synchronization of Serdes overclock of claim 5, wherein the cross-clock module is further configured to:
writing the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface into an asynchronous first-in first-out buffer;
when the depth of the buffer reaches a preset threshold, a CPU is informed of reading the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface, wherein a clock domain read by the CPU works in a main clock domain of a chip; and
and the sending time of the frame start delimiter of the PTP message on the Serdes parallel interface is put into a following message, and the following message is forwarded.
9. An electronic device, comprising:
at least one processor; and
a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the method of supporting Serdes over-clocking of any of claims 1 to 4.
10. A computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the steps of the method of supporting Serdes overclocking time synchronization according to any of claims 1 to 4.
CN202111602566.8A 2021-12-24 2021-12-24 Method and application for supporting time synchronization of Serdes overclock Pending CN116346270A (en)

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