CN116346243B - Underwater acoustic serial port communication circuit - Google Patents
Underwater acoustic serial port communication circuit Download PDFInfo
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- CN116346243B CN116346243B CN202211419876.0A CN202211419876A CN116346243B CN 116346243 B CN116346243 B CN 116346243B CN 202211419876 A CN202211419876 A CN 202211419876A CN 116346243 B CN116346243 B CN 116346243B
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- 239000003990 capacitor Substances 0.000 claims description 51
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B13/00—Transmission systems characterised by the medium used for transmission, not provided for in groups H04B3/00 - H04B11/00
- H04B13/02—Transmission systems in which the medium consists of the earth or a large mass of water thereon, e.g. earth telegraphy
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
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Abstract
The invention relates to a communication circuit, in particular to an underwater acoustic serial communication circuit. The frequency-selective circuit is characterized by comprising two FSK frequency-selective modules and a gate circuit, wherein the FSK frequency-selective modules are connected with the gate circuit in an adaptive manner, the FSK frequency-selective modules are used for selecting frequencies of input signals LO, when the frequency of the input signals LO is the set frequency of the FSK frequency-selective modules, the output signals FSKrx of the FSK frequency-selective modules are high level, namely logic 1, and when the frequency of the input signals LO is other set frequency, the output signals FSKrx of the FSK frequency-selective modules are low level, namely logic 0. The gate circuit is used for converting an output signal FSKrx of the FSK frequency discrimination module into a TTL level signal so as to carry out serial port communication. The reference signal of the FSK frequency discrimination module is controlled by a Notch bias potentiometer R15 so as to adjust the reference of the frequency discrimination module and realize delay triggering. The underwater acoustic serial communication circuit is low in price and long in standby time.
Description
Technical Field
The invention relates to a communication circuit, in particular to an underwater acoustic serial port communication circuit which is low in power consumption and can stand by for a long time.
Background
The acoustic releaser is mainly applied to recycling of deep sea monitoring instrument equipment, and after receiving a deck unit release instruction, the acoustic releaser drives a release mechanism to recycle the monitoring instrument equipment, belongs to switching value signals and does not have a data return function. However, although the underwater acoustic communication device can perform data communication, the cost is high, the standby power consumption is generally high, and the standby time is short, which is not suitable.
Disclosure of Invention
The invention aims to solve the technical problem of improving an underwater acoustic serial port communication circuit, which has low price and long standby time.
In order to solve the problems, the following technical scheme is provided:
the underwater acoustic serial port communication circuit is characterized by comprising two FSK frequency discrimination modules and a gate circuit, wherein the FSK frequency discrimination modules are connected with the gate circuit in an adaptive manner, the FSK frequency discrimination modules are used for selecting frequencies of input signals LO, when the frequency of the input signals LO is the set frequency of the FSK frequency discrimination modules, the output signals FSKrx of the FSK frequency discrimination modules are high levels, namely logic 1, and when the frequency of the input signals LO is other set frequencies, the output signals FSKrx of the FSK frequency discrimination modules are low levels, namely logic 0; the gate circuit is used for converting an output signal FSKrx of the FSK frequency discrimination module into a TTL level signal so as to carry out serial port communication. The reference signal of the FSK frequency discrimination module is controlled by a Notch bias potentiometer R15 so as to adjust the reference of the frequency discrimination module and realize delay triggering.
The FSK frequency discrimination module comprises a frequency selection filtering unit, a first enveloping unit, a second enveloping unit, a judging unit and a notch unit. The frequency-selecting filtering unit is connected with the first envelope unit in an adaptive manner, the notch unit is connected with the second envelope unit in an adaptive manner, and the first envelope unit and the second envelope unit are connected with the judging unit in an adaptive manner; the input signal LO enters a frequency-selecting filter circuit and a trap circuit respectively, the frequency-selecting filter circuit filters the input signal LO in a frequency-selecting way and then forms an envelope signal Zt through a first envelope unit, the trap circuit traps the input signal LO and then forms an envelope signal Zn through a second envelope unit, the envelope signal Zt and the envelope signal Zn enter a judging unit, the judging unit judges the envelope signal Zt and the envelope signal Zn and then generates an output signal FSKrx, and the output signal FSKrx is connected with the input end of an AND gate circuit.
The notch unit comprises a resistor R18 and a comparison amplifier U4A. One end of the resistor R18 is connected to the input signal LO, the other end of the resistor R18 is connected with one end of the capacitor C11, the other end of the capacitor C11 is connected with the inverting input end of the comparison amplifier U4A, the non-inverting input end of the comparison amplifier U4A is connected with the reference signal Notch bias, the output end of the comparison amplifier U4A is respectively connected with the control end of the second wrapping unit, one end of the resistor R12 and one end of the capacitor C8, the other end of the resistor R12 is respectively located at one fixed pin of the potentiometer R14 and the inverting input end of the comparison amplifier U4A, the other end of the capacitor C8 is respectively connected with the moving plate pin of the potentiometer R14 and the inverting input end of the comparison amplifier U4A, the other fixed pin of the potentiometer R14 is connected with one end of the capacitor C9, and the other end of the capacitor C9 is connected with the frequency selecting filter unit. The power source AVCC is connected with one end of a resistor R11, the other end of the resistor R11 is connected with one fixed pin of a potentiometer R15, the other fixed pin of the potentiometer R15 is connected with one end of a resistor R17, the other end of the resistor R17 is grounded, and two ends of the resistor R17 are connected with a capacitor C12 in parallel. The movable piece pin of the potentiometer R15 is connected with one end of the capacitor C13, and the other end of the capacitor C13 is grounded; the moving plate pin of the potentiometer R15 forms the reference signal Notch bias. The potentiometer R15 pin connected with the resistor R17 forms AVCC/2.
The frequency-selecting filtering unit comprises an operational amplifier U1A, an operational amplifier U2A and a resistor R1; one end of the resistor R1 is connected to the input signal LO, the other end of the resistor R1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is connected with the inverting input end of the operational amplifier U1A, the non-inverting input end of the operational amplifier U1A is connected with the AVCC/2, the output end of the operational amplifier U1A is connected with one end of the resistor R4, one end of the resistor R2 and one end of the capacitor C1 respectively, the other end of the resistor R4 is connected with the inverting input end of the operational amplifier U2A, the other end of the resistor R2 is connected with the inverting input end of the operational amplifier U1A, and the other end of the capacitor C1 is connected with one end of the capacitor C2 connected with the resistor R1. The non-inverting input end of the operational amplifier U2A is connected with the AVCC/2, the output end of the operational amplifier U2A is respectively connected with the control end of the first envelope unit, one fixed pin of the potentiometer R5, the moving plate pin of the potentiometer R5, one fixed pin of the potentiometer R3 and the moving plate pin of the potentiometer R3, the other fixed pin of the potentiometer R5 is connected with the inverting input end of the operational amplifier U2A, and the other fixed pin of the potentiometer R3 is connected with one end of the capacitor C2 connected with the resistor R1.
The judging unit is a comparison amplifier U1B, the output end of the comparison amplifier U1B generates the output signal FSKrx, the output end of the comparison amplifier U1B is connected with one end of a resistor R8, and the other end of the resistor R8 is connected with the non-inverting input end of the comparison amplifier U1B.
The second envelope unit comprises a triode Q2, the collector of the triode Q2 is connected with a power supply AVCC, the base of the triode Q2 is the control end of the second envelope unit, the emitter of the triode Q2 is connected with one end of a resistor R16, the other end of the resistor R16 generates an envelope signal Zn, the end of the resistor R16 is connected with one end of a resistor R13 and the inverting input end of a comparison amplifier U1B respectively, the other end of the resistor R13 is grounded, and a capacitor C10 is connected between the two ends of the resistor R13 in parallel.
The first envelope unit comprises a triode Q1, a collector electrode of the triode Q1 is connected with a power supply AVCC, a base electrode of the triode Q1 is a control end of the first envelope unit, an emitter electrode of the triode Q1 is connected with one end of a resistor R6, the other end of the resistor R6 is respectively connected with one end of a resistor R9 and one end of a resistor R7, the other end of the resistor R9 is grounded, a capacitor C7 is connected between two ends of the resistor R9 in parallel, an envelope signal Zt is generated at the other end of the resistor R7, and the end of the resistor R7 is connected with a non-inverting input end of a comparison amplifier U1B.
The output end of the comparison amplifier U1B is connected with one end of a resistor R10, and the other end of the resistor R10 is grounded through a light emitting diode D1.
The gate circuit is a NAND gate circuit.
By adopting the scheme, the method has the following advantages:
because the underwater acoustic serial port communication circuit adopts two FSK frequency discrimination modules to respectively generate logic 1 and logic 0 signals, and adopts a gate circuit to realize serial port communication by using the logic signal TTL level signals, the reference signal of the FSK frequency discrimination module is controlled by a Notch bias potentiometer R15 so as to adjust the reference of the frequency discrimination module and realize delay triggering. The underwater acoustic serial communication circuit is arranged in the deck unit, and the switching value signals can be converted into serial signals to be transmitted to the MCU, so that serial communication is realized, and compared with the underwater acoustic communication machine, the whole communication circuit has low cost. Moreover, the ocean background noise can be filtered out by setting the reference of the frequency discrimination module, so that false triggering operation caused by the ocean background noise is avoided, the power consumption of the whole circuit is greatly reduced, the standby time of the circuit is prolonged, and the circuit can be continuously standby underwater for years.
Drawings
FIG. 1 is a topology diagram of an underwater acoustic serial communications circuit of the present invention;
FIG. 2 is a schematic diagram of the structure of an FSK frequency discrimination module in an underwater acoustic serial communication circuit of the present invention;
FIG. 3 is a graph showing actual waveforms of the Q values of the notch units in the underwater acoustic serial communication circuit of the present invention;
fig. 4 is a schematic diagram of an FSK frequency discrimination module of the underwater acoustic serial communication circuit of the present invention in an operating state with an input signal and an output signal.
FIG. 5 is a waveform actual measurement diagram of the Q value of the frequency selective filter unit in the underwater acoustic serial communication circuit of the present invention;
FIG. 6 is a diagram of a data format of UART serial communication.
Detailed Description
The present invention is described in further detail below with reference to the accompanying drawings.
As shown in fig. 1 to 6, the underwater acoustic serial communication circuit of the present invention includes two FSK frequency discrimination modules and a gate circuit, which is a nand gate circuit. The FSK frequency discrimination module is connected with the AND gate circuit in an adaptive manner, the FSK frequency discrimination module is used for selecting the frequency of the input signal LO, when the frequency of the input signal LO is the set frequency of the FSK frequency discrimination module, the output signal FSKrx of the FSK frequency discrimination module is high level, namely logic 1, and when the frequency of the input signal LO is other set frequencies, the output signal FSKrx of the FSK frequency discrimination module is low level, namely logic 0. The gate circuit is used for converting an output signal FSKrx of the FSK frequency discrimination module into a TTL level signal so as to carry out serial port communication. The reference signal of the FSK frequency discrimination module is controlled by a Notch bias potentiometer R15 so as to adjust the reference of the frequency discrimination module and realize delay triggering. The FSK frequency discrimination module comprises a frequency selection filtering unit, a first enveloping unit, a second enveloping unit, a judging unit and a notch unit. The frequency-selecting filtering unit is connected with the first envelope unit in an adaptive manner, the notch unit is connected with the second envelope unit in an adaptive manner, and the first envelope unit and the second envelope unit are connected with the judging unit in an adaptive manner; the input signal LO enters a frequency-selecting filter circuit and a trap circuit respectively, the frequency-selecting filter circuit filters the input signal LO in a frequency-selecting way and then forms an envelope signal Zt through a first envelope unit, the trap circuit traps the input signal LO and then forms an envelope signal Zn through a second envelope unit, the envelope signal Zt and the envelope signal Zn enter a judging unit, the judging unit judges the envelope signal Zt and the envelope signal Zn and then generates an output signal FSKrx, and the output signal FSKrx is connected with the input end of an AND gate circuit. The two FSK frequency discrimination modules are adopted to convert the switching value signals into output signals FSKrx of logic 1 or logic 0, and the output signals FSKrx are converted into TTL level signals through the gate circuit, so that serial port signals can be formed to be communicated with the MCU. The ocean background noise can be filtered out by setting the reference of the frequency discrimination module, so that false triggering operation caused by the ocean background noise is avoided.
As shown in fig. 2, the notch unit includes a resistor R18 and a comparison amplifier U4A. One end of the resistor R18 is connected to the input signal LO, the other end of the resistor R18 is connected with one end of the capacitor C11, the other end of the capacitor C11 is connected with the inverting input end of the comparison amplifier U4A, the non-inverting input end of the comparison amplifier U4A is connected with the reference signal Notch bias, the output end of the comparison amplifier U4A is respectively connected with the control end of the second wrapping unit, one end of the resistor R12 and one end of the capacitor C8, the other end of the resistor R12 is respectively located at one fixed pin of the potentiometer R14 and the inverting input end of the comparison amplifier U4A, the other end of the capacitor C8 is respectively connected with the moving plate pin of the potentiometer R14 and the inverting input end of the comparison amplifier U4A, the other fixed pin of the potentiometer R14 is connected with one end of the capacitor C9, and the other end of the capacitor C9 is connected with the frequency selecting filter unit. The power source AVCC is connected with one end of a resistor R11, the other end of the resistor R11 is connected with one fixed pin of a potentiometer R15, the other fixed pin of the potentiometer R15 is connected with one end of a resistor R17, the other end of the resistor R17 is grounded, and two ends of the resistor R17 are connected with a capacitor C12 in parallel. The movable piece pin of the potentiometer R15 is connected with one end of the capacitor C13, and the other end of the capacitor C13 is grounded. The moving plate pin of the potentiometer R15 forms the reference signal Notch bias. The potentiometer R15 pin connected with the resistor R17 forms AVCC/2. By adjusting the value of R14, the Q value of the notch unit is adjusted to be below-40 dB, so that the requirement can be met, and the actual test waveform of the notch unit is shown in figure 3. The notch unit reference is adjusted by adjusting the value of R15, so that the purpose of delay triggering is achieved, namely, after the effective signals reach a certain number, the output can trigger the high level as shown in fig. 4, and only after the effective signals reach a certain number, the output high level can be triggered, so that the influence of false triggering caused by ocean background noise on the power consumption of the whole circuit is effectively eliminated, and the underwater standby time is prolonged.
As shown in fig. 2, the frequency-selective filtering unit includes an operational amplifier U1A, an operational amplifier U2A, and a resistor R1; one end of the resistor R1 is connected to the input signal LO, the other end of the resistor R1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is connected with the inverting input end of the operational amplifier U1A, the non-inverting input end of the operational amplifier U1A is connected with the AVCC/2, the output end of the operational amplifier U1A is connected with one end of the resistor R4, one end of the resistor R2 and one end of the capacitor C1 respectively, the other end of the resistor R4 is connected with the inverting input end of the operational amplifier U2A, the other end of the resistor R2 is connected with the inverting input end of the operational amplifier U1A, and the other end of the capacitor C1 is connected with one end of the capacitor C2 connected with the resistor R1. The non-inverting input end of the operational amplifier U2A is connected with the AVCC/2, the output end of the operational amplifier U2A is respectively connected with the control end of the first envelope unit, one fixed pin of the potentiometer R5, the moving plate pin of the potentiometer R5, one fixed pin of the potentiometer R3 and the moving plate pin of the potentiometer R3, the other fixed pin of the potentiometer R5 is connected with the inverting input end of the operational amplifier U2A, and the other fixed pin of the potentiometer R3 is connected with one end of the capacitor C2 connected with the resistor R1. The design principle of the frequency-selecting filtering unit is as follows: let R 1 ＝R 2 ＝R，C 1 ＝C 2 The frequency selection frequency is given by =c:
by setting proper resistance and capacitance, R is then regulated 3 The purpose of accurate frequency selection is achieved. Finally adjust R 5 The Q value of the frequency-selecting filtering unit is adjusted, and the expression is as follows:
R 5 and the value is adjusted to a proper value, so that the denominator is equal to 0, the Q value can reach infinity theoretically, and the test effect of the actual frequency-selecting filtering unit is shown in fig. 5.
The first envelope unit comprises a triode Q1, a collector electrode of the triode Q1 is connected with a power supply AVCC, a base electrode of the triode Q1 is a control end of the first envelope unit, an emitter electrode of the triode Q1 is connected with one end of a resistor R6, the other end of the resistor R6 is respectively connected with one end of a resistor R9 and one end of a resistor R7, the other end of the resistor R9 is grounded, a capacitor C7 is connected between two ends of the resistor R9 in parallel, an envelope signal Zt is generated at the other end of the resistor R7, and the end of the resistor R7 is connected with a non-inverting input end of a comparison amplifier U1B. The second envelope unit comprises a triode Q2, the collector of the triode Q2 is connected with a power supply AVCC, the base of the triode Q2 is the control end of the second envelope unit, the emitter of the triode Q2 is connected with one end of a resistor R16, the other end of the resistor R16 generates an envelope signal Zn, the end of the resistor R16 is connected with one end of a resistor R13 and the inverting input end of a comparison amplifier U1B respectively, the other end of the resistor R13 is grounded, and a capacitor C10 is connected between the two ends of the resistor R13 in parallel. The judging unit is a comparison amplifier U1B, the output end of the comparison amplifier U1B generates the output signal FSKrx, the output end of the comparison amplifier U1B is connected with one end of a resistor R8, and the other end of the resistor R8 is connected with the non-inverting input end of the comparison amplifier U1B. The comparison amplifier U1B compares and judges the envelope signal Zt and the envelope signal Zn, and can output high level after the frequency signal to be frequency-discriminated is input. The input signals of the rest frequencies, the circuit outputs low level.
As shown in fig. 2, the output end of the comparison amplifier U1B is connected to one end of the resistor R10, and the other end of the resistor R10 is grounded through the light emitting diode D1. When the output signal is at a high level, the light emitting diode D1 generates light, thereby playing a role in prompting.
UART serial communication is a communication mode for transmitting data according to bits, and a communication protocol can be layered into a protocol layer and a physical layer. The physical layer defines the characteristics of mechanical and electronic functions in the communication protocol, so as to ensure the propagation of the original data in a physical medium; the protocol layer mainly prescribes communication logic, unifies data packing and unpacking standards of both parties, and the data format is shown in fig. 6. When transmitting data, for example, 0x55 data, which is expressed as 0b01010101 in binary form, is a principle of low-order first transmission and high-order last transmission in UART communication, then the TXD is pulled down first for a period of time, a bit 0 is transmitted, then pulled down again for a period of time, a bit 0 is transmitted again, then pulled up for a period of time, and a bit 1 … … is transmitted until all 8-bit binary digits 0b01010101 are transmitted. Wherein the baud rate of the communication is agreed in advance according to the sending duration of each bit. Two instruction parameters are set for UART serial communication encoding, one being an in-band frequency (logic 1) and an out-of-band frequency (logic 0).
In use, the frequency of one FSK frequency discrimination module is set to transmit an in-band frequency (logic 1), the output signal FSKrx generated by the FSK frequency discrimination module is defined as FSKrx1, and the frequency of the other FSK frequency discrimination module is set to transmit an out-of-band frequency (logic 0), and the output signal FSKrx generated by the FSK frequency discrimination module is defined as FSKrx0. The input signal LO is demodulated into a TTL level signal through the underwater acoustic communication circuit, and then can be connected to the RXD pin of the UART serial port of the MCU to perform underwater acoustic data interaction, wherein the truth table is as follows:
| FSK1 | FSK0 | UART_RX | status of |
| 0 | 0 | 1 | Idle |
| 0 | 1 | 0 | Logic 0 |
| 1 | 0 | 1 | Logic 1 |
The underwater acoustic serial communication circuit converts the switching value signal into the serial signal and transmits the serial signal to the MCU, so that serial communication is realized, and compared with an underwater acoustic communication machine, the cost of the whole communication circuit is low. Moreover, the ocean background noise can be filtered out by setting the reference of the frequency discrimination module, so that false triggering operation caused by the ocean background noise is avoided, the power consumption of the whole circuit is greatly reduced, the standby time of the circuit is prolonged, and the circuit can be continuously standby underwater for years.
Claims (3)
1. The underwater acoustic serial port communication circuit is characterized by comprising two FSK frequency discrimination modules and a gate circuit, wherein the FSK frequency discrimination modules are connected with the gate circuit in an adaptive manner, the FSK frequency discrimination modules are used for selecting frequencies of input signals LO, when the frequency of the input signals LO is the set frequency of the FSK frequency discrimination modules, the output signals FSKrx of the FSK frequency discrimination modules are high levels, namely logic 1, and when the frequency of the input signals LO is other set frequencies, the output signals FSKrx of the FSK frequency discrimination modules are low levels, namely logic 0; the gate circuit is used for converting an output signal FSKrx of the FSK frequency discrimination module into a TTL level signal so as to carry out serial port communication; the reference signal of the FSK frequency discrimination module is controlled by a Notch bias potentiometer R15 so as to adjust the reference of the frequency discrimination module and realize delay triggering; setting the frequency of one FSK frequency discrimination module to enable the FSK frequency discrimination module to send in-band frequency, namely logic 1, and setting the frequency of the other FSK frequency discrimination module to enable the FSK frequency discrimination module to send out-of-band frequency, namely logic 0;
the FSK frequency discrimination module comprises a frequency selection filtering unit, a first enveloping unit, a second enveloping unit, a judging unit and a notch unit; the frequency-selecting filtering unit is connected with the first envelope unit in an adaptive manner, the notch unit is connected with the second envelope unit in an adaptive manner, and the first envelope unit and the second envelope unit are connected with the judging unit in an adaptive manner; the input signal LO enters a frequency-selecting filter circuit and a trap circuit respectively, the frequency-selecting filter circuit filters the input signal LO in a frequency-selecting way and then forms an envelope signal Zt through a first envelope unit, the trap circuit traps the input signal LO and then forms an envelope signal Zn through a second envelope unit, the envelope signal Zt and the envelope signal Zn enter a judging unit, the judging unit judges the envelope signal Zt and the envelope signal Zn and then generates an output signal FSKrx, and the output signal FSKrx is connected with the input end of the AND gate circuit;
the notch unit comprises a resistor R18 and a comparison amplifier U4A; one end of the resistor R18 is connected to the input signal LO, the other end of the resistor R18 is connected with one end of the capacitor C11, the other end of the capacitor C11 is connected with the inverting input end of the comparison amplifier U4A, the non-inverting input end of the comparison amplifier U4A is connected with the reference signal Notch bias, the output end of the comparison amplifier U4A is respectively connected with the control end of the second wrapping unit, one end of the resistor R12 and one end of the capacitor C8, the other end of the resistor R12 is respectively positioned at one fixed pin of the potentiometer R14 and the inverting input end of the comparison amplifier U4A, the other end of the capacitor C8 is respectively connected with the moving plate pin of the potentiometer R14 and the inverting input end of the comparison amplifier U4A, the other fixed pin of the potentiometer R14 is connected with one end of the capacitor C9, and the other end of the capacitor C9 is connected with the frequency selection filter unit; the power source AVCC is connected with one end of a resistor R11, the other end of the resistor R11 is connected with one fixed pin of a potentiometer R15, the other fixed pin of the potentiometer R15 is connected with one end of a resistor R17, the other end of the resistor R17 is grounded, and two ends of the resistor R17 are connected with a capacitor C12 in parallel; the movable piece pin of the potentiometer R15 is connected with one end of the capacitor C13, and the other end of the capacitor C13 is grounded; the movable piece pin of the potentiometer R15 forms the reference signal Notch bias; the fixed pin of the potentiometer R15 connected with the resistor R17 forms AVCC/2;
the frequency-selecting filtering unit comprises an operational amplifier U1A, an operational amplifier U2A and a resistor R1; one end of the resistor R1 is connected with the input signal LO, the other end of the resistor R1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is connected with the inverting input end of the operational amplifier U1A, the non-inverting input end of the operational amplifier U1A is connected with the AVCC/2, the output end of the operational amplifier U1A is respectively connected with one end of the resistor R4, one end of the resistor R2 and one end of the capacitor C1, the other end of the resistor R4 is connected with the inverting input end of the operational amplifier U2A, the other end of the resistor R2 is connected with the inverting input end of the operational amplifier U1A, and the other end of the capacitor C1 is connected with one end of the capacitor C2 connected with the resistor R1; the non-inverting input end of the operational amplifier U2A is connected with the AVCC/2, the output end of the operational amplifier U2A is respectively connected with the control end of the first envelope unit, one fixed pin of the potentiometer R5, the moving plate pin of the potentiometer R5, one fixed pin of the potentiometer R3 and the moving plate pin of the potentiometer R3, the other fixed pin of the potentiometer R5 is connected with the inverting input end of the operational amplifier U2A, and the other fixed pin of the potentiometer R3 is connected with one end of a capacitor C2 connected with a resistor R1;
the judging unit is a comparison amplifier U1B, the output end of the comparison amplifier U1B generates the output signal FSKrx, the output end of the comparison amplifier U1B is connected with one end of a resistor R8, and the other end of the resistor R8 is connected with the non-inverting input end of the comparison amplifier U1B;
the second envelope unit comprises a triode Q2, the collector of the triode Q2 is connected with a power supply AVCC, the base electrode of the triode Q2 is the control end of the second envelope unit, the emitter of the triode Q2 is connected with one end of a resistor R16, the other end of the resistor R16 generates an envelope signal Zn, one end of the resistor R16 generating the envelope signal Zn is respectively connected with one end of a resistor R13 and the inverting input end of a comparison amplifier U1B, the other end of the resistor R13 is grounded, and a capacitor C10 is connected between the two ends of the resistor R13 in parallel;
the first envelope unit comprises a triode Q1, a collector of the triode Q1 is connected with a power supply AVCC, a base electrode of the triode Q1 is a control end of the first envelope unit, an emitter of the triode Q1 is connected with one end of a resistor R6, the other end of the resistor R6 is respectively connected with one end of a resistor R9 and one end of a resistor R7, the other end of the resistor R9 is grounded, a capacitor C7 is connected between two ends of the resistor R9 in parallel, the other end of the resistor R7 generates an envelope signal Zt, and one end of the resistor R7 generating the envelope signal Zt is connected with a non-inverting input end of a comparison amplifier U1B.
2. The underwater acoustic serial communication circuit as claimed in claim 1, wherein the output terminal of the comparison amplifier U1B is connected to one end of a resistor R10, and the other end of the resistor R10 is grounded through a light emitting diode D1.
3. The underwater acoustic serial communications circuit of claim 1, wherein the gate circuit is a nand gate circuit.
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