CN116346142A

CN116346142A - Coding method and coder, decoding method and decoder, communication system

Info

Publication number: CN116346142A
Application number: CN202111607935.2A
Authority: CN
Inventors: 庄永昌
Original assignee: China Telecom Corp Ltd
Current assignee: China Telecom Corp Ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2023-06-27

Abstract

The present disclosure provides an encoding method and encoder, a decoding method and decoder, and a communication system. The coding method comprises the following steps: processing the initial bit sequence to generate m initial w transverse subsections with the length of n; sub-segment transformation is carried out on m initial w transverse sub-segments to generate m initial b transverse sub-segments with the length of n; combining bits in the m initial b horizontal subsections with the same position respectively to generate an initial b vertical subsection; generating a b longitudinal sub-segment check code by using s initial b longitudinal sub-segments, and forming q temporary b transverse sub-segments by using b longitudinal sub-segment check code bits and null bits; generating m b transverse subsections by utilizing h initial b transverse subsections and q temporary b transverse subsections; performing sub-segment transformation on the m b transverse sub-segments to generate m w transverse sub-segments; combining the m w transverse subsections into a bit sequence to be coded with the length of N; and coding the bit sequence to be coded with the length of N to obtain a coded bit sequence and transmitting the coded bit sequence.

Description

Coding method and coder, decoding method and decoder, communication system

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to an encoding method, an encoder, a decoding method, a decoder, and a communications system.

Background

In the SCL (Successive Cancellation List, list continuous deletion) decoding scheme of the polarization code, the polarization code is split into a plurality of transverse subsections with equal length, each subsection is independently subjected to SCL decoding assisted by a check code, and then the decoding results of each subsection (set as a bit space) are processed in a combined way to obtain the decoding result (set as v bit space) of the polarization code.

Disclosure of Invention

The inventor notes that a plurality of alternative paths can pass the verification in the SCL decoding result assisted by the transverse sub-segment verification code, and only one alternative path can be selected according to the magnitude of the occurrence probability, thereby influencing the decoding result.

Accordingly, the present disclosure proposes a coding and decoding scheme, which performs longitudinal sub-segment verification based on the transverse sub-segment verification result, so as to improve the performance of sub-segment SCL decoding.

According to a first aspect of embodiments of the present disclosure, there is provided an encoding method, including: processing an initial bit sequence with the length of N to generate m initial w transverse subsections with the length of N, wherein the initial bit sequence comprises source information bits, frozen bits and null bits; performing w- > b sub-segment transformation processing on m initial w transverse sub-segments to generate m initial b transverse sub-segments with the length of n, wherein among the m initial b transverse sub-segments, h initial b transverse sub-segments comprise mixed bits and null bits, q initial b transverse sub-segments comprise null bits, and m=h+q; combining the bits with the same positions in m initial b transverse subsections respectively to generate s initial b longitudinal subsections comprising mixed bits and null bits and r initial b longitudinal subsections comprising null bits, wherein n=s+r; generating s b longitudinal subsections with the length of m and comprising b longitudinal subsection check codes by using the s initial b longitudinal subsections, and forming q temporary b transverse subsections with the length of n by using b longitudinal subsection check code bits in the s b longitudinal subsections and null bits in the r longitudinal subsections; generating m b transverse subsections comprising b transverse subsection check codes by utilizing the h initial b transverse subsections and the q temporary b transverse subsections; b- > w sub-segment transformation is carried out on the m b transverse sub-segments so as to generate m w transverse sub-segments; merging the m w transverse subsections into a bit sequence to be coded with the length of N; and coding the bit sequence to be coded with the length of N to obtain a coded bit sequence and transmitting the coded bit sequence.

In some embodiments, N, m and n are each an integer power of 2; the code is a polarization code.

In some embodiments, in m initial b lateral subsections: the 1 st to the s bit in the 1 st to the h th initial w-direction subsections are composed of source information bits and freeze bits, and the s+1 to the s+r bits are composed of null bits; the h+1th to h+q th initial w transverse subsections consist of null bits.

In some embodiments, the w- > b sub-segment transform is processed as a multi-bit operation; the mixed bit in the initial b transverse sub-segment is obtained by calculating the source information bit, the frozen bit and the null bit in the initial w transverse sub-segment; the null bits in the initial b transversal sub-segment are calculated from at least one null bit in the initial w transversal sub-segment.

In some embodiments, in n initial b longitudinal subsections: the 1 st bit to the h bit in the 1 st initial b longitudinal subsection to the s th initial b longitudinal subsection are respectively generated by the source information bit, the frozen bit and the null bit through operation, and the h+1th bit to the h+q bit are generated by the null bit through operation; bits in the s+1th initial b-longitudinal sub-segment to the s+r th initial b-longitudinal sub-segment are generated by a null bit through operation.

In some embodiments, generating s b-longitudinal subsections of length m comprising b-longitudinal subsegment check codes using the s initial b-longitudinal subsegments comprises: and performing check code generation operation on the mixed bits in the s initial b longitudinal subsections to obtain s b longitudinal subsections with the length m, wherein the s b longitudinal subsections comprise b longitudinal subsection check codes.

In some embodiments, generating m b transversal subsections including b transversal subsections check codes using the h initial b transversal subsections and the q temporary b transversal subsections includes: performing check code generation operation on the mixed bits in the h initial b transverse subsections to generate h b transverse subsections with the length of n and containing b transverse subsections check codes; and performing check code generation operation on the mixed bits in the q temporary b transverse subsections and the b longitudinal subsection check code bits to generate q b transverse subsections with the length of n and containing the b transverse subsections check code.

In some embodiments, the b- > w sub-segment transforms and the w- > b sub-segment transforms are inverse to each other.

In some embodiments, generating m b transversal subsections including b transversal subsections check codes using the h initial b transversal subsections and the q temporary b transversal subsections includes: splicing m B transverse subsections comprising the h initial B transverse subsections and the q temporary B transverse subsections into k B transverse subsections, wherein each B transverse subsection comprises one or more B transverse subsections; and respectively performing check code generation operation on the mixed bits in the k B transverse subsections and the B longitudinal subsections so as to generate B transverse subsections check codes of the k B transverse subsections.

In some embodiments, the b-longitudinal sub-segment check code comprises a cyclic redundancy check code, a parity check code, or a combination of a cyclic redundancy check code and a parity check code.

In some embodiments, if k=1, there is only one B transversal sub-segment, which includes all m B transversal sub-segments, which includes one check code, and the check code bits are located in the check code bits of the m B transversal sub-segments; if k is more than 1 and less than m, at least one B transverse sub-segment comprises a plurality of B transverse sub-segments, each B transverse sub-segment comprises a check code, and check code bits in each B transverse sub-segment are positioned in check code bits in the corresponding B transverse sub-segment; if k=m, each B-transversal sub-segment serves as a B-transversal sub-segment, each B-transversal sub-segment includes a check code, and the check code bits in each B-transversal sub-segment are located in the check code bits in the corresponding B-transversal sub-segment.

According to a second aspect of embodiments of the present disclosure, there is provided an encoder comprising: a memory configured to store instructions; a processor coupled to the memory, the processor configured to perform the encoding method according to any of the embodiments described above based on instructions stored in the memory.

According to a third aspect of embodiments of the present disclosure, there is provided a decoding method, including: dividing a received bit sequence to be decoded with the length of N into m transverse subsections to be decoded with the length of N, wherein the bit sequence to be decoded with the length of N is a log likelihood ratio sequence; independently carrying out decoding processing on the m transverse subsections to be decoded to obtain a decoding result of m a transverse subsections with L alternative paths; respectively combining bits with the same position in the same alternative path in m a transverse subsections to generate s a longitudinal subsections, wherein the s a longitudinal subsections do not comprise a longitudinal subsections consisting of a transverse subsections check codes; respectively checking m a transverse subsections so as to reserve alternative paths passing the check; checking the s longitudinal subsections a to obtain m decoding results; and processing the m decoding results to obtain a decoding bit sequence.

In some embodiments, N, m and n are each an integer power of 2; the decoding process is an SCL decoding process.

In some embodiments, processing the m SCL decoding results to obtain a decoded bit sequence comprises: sub-segment transformation is carried out on m decoding results to obtain m v sub-segments; carrying out correction processing on the m v sub-segments to obtain m corrected v sub-segments; and merging the m corrected v sub-segments to obtain a decoding bit sequence.

In some embodiments, verifying the m a lateral subsections separately includes: parity checking is performed on each a transverse sub-segment; if the alternative paths passing through the parity check exist, deleting the alternative paths not passing through the parity check; wherein the bits at the same position on the multiple alternative paths passing the check in each a transverse subsection are divided into single value bits and split value bits, the single value bits are 0 or 1, and the split value bits have 0 and 1 at the same time.

In some embodiments, verifying the s a longitudinal subsections includes: respectively concatenating the values of m bits in the s a longitudinal subsections into a plurality of alternative paths according to single value bits or split value bits, wherein 0 and 1 of the split value bits respectively participate in path combination, and reserving Lv alternative paths with the maximum occurrence probability; respectively carrying out parity check on Lv alternative paths of each a longitudinal subsection in the s a longitudinal subsections, wherein if the bits at the same position in a plurality of alternative paths passing through the parity check are single-value bits, the corresponding single-value bits are the check result of the corresponding bits of the a transverse subsections, and deleting the alternative paths with inconsistent values of the corresponding bits in the alternative paths reserved in the a transverse subsections and the single-value bits; if only one alternative path is reserved currently, taking the alternative path as an SCL decoding result; if a plurality of alternative paths are reserved currently, the alternative path with the largest occurrence probability is taken as an SCL decoding result.

In some embodiments, verifying the m a lateral subsections separately includes: dividing m a transverse subsections Duan Pinjie into k A subsections, wherein each A subsection comprises one or more a transverse subsections, and k is a positive integer which is more than 1 and less than or equal to m; respectively checking k A subsections; if the alternative paths passing the verification exist, deleting the alternative paths not passing the verification; splitting the a sub-segment so as to take the obtained a sub-segment as a corresponding decoding result, wherein bits at the same position on a plurality of alternative paths passing verification in each a sub-segment are divided into single value bits and split value bits, wherein the single value is 0 or 1, and the split value simultaneously has 0 and 1.

In some embodiments, verifying the k a subsections separately includes: and respectively performing CRC check, parity check or CRC and parity combination check on the k A sub-segments.

In some embodiments, dividing the m a-transversal subsections Duan Pinjie into k a subsections includes: in the k-th group, the parameter i=1 is taken; combining the L alternative paths in the ith a-transversal subsection with the L alternative paths of the 1 st a-transversal subsection to obtain L ² Alternate paths; will L ² The L alternative paths with the highest occurrence probability among the alternative paths are used as L alternative paths of the (i+1) th a transverse subsection; updating the parameter i with i=i+1; if i is less than M, repeating the step of combining the L alternative paths in the ith a transverse subsection and the L alternative paths of the (i+1) th a transverse subsection; if i=m, the L alternative paths with the largest occurrence probability are taken as alternative paths of the k-th group a sub-segment.

In some embodiments, combining the L alternative paths in the i-th a-lateral subsection and the L alternative paths of the 1-th a-lateral subsection comprises: and combining the L alternative paths in the ith transverse subsection and the L alternative paths of the 1 st transverse subsection according to a serial splicing mode of splicing one by one, a parallel splicing mode of splicing all groups simultaneously after grouping or a serial and parallel mixed splicing mode.

In some embodiments, verifying the s a longitudinal subsections includes: respectively concatenating the values of m bits in the s a longitudinal subsections into a plurality of alternative paths according to single value bits or split value bits, wherein the two split values respectively participate in path combination, and reserving Lv alternative paths with the maximum occurrence probability; respectively carrying out parity check on Lv alternative paths of each a longitudinal subsection in the s a longitudinal subsections, wherein if the bits at the same position in the alternative paths passing through the parity check are all single-value bits, the corresponding single value is a check result of the corresponding bit of the a transverse subsection, and deleting the value of the corresponding bit in the alternative paths reserved in the a transverse subsection and the alternative paths with inconsistent single value; if only one alternative path is reserved currently, taking the alternative path as a decoding result; if a plurality of alternative paths are reserved currently, the alternative path with the largest occurrence probability is taken as a decoding result.

In some embodiments, performing correction processing on the m v subsections to obtain m corrected v subsections includes: and (3) carrying out operation on the h+1th to h+qh a transverse subsections and the v subsections to obtain m corrected v subsections.

According to a fourth aspect of embodiments of the present disclosure, there is provided a decoder, comprising: a memory configured to store instructions; a processor coupled to the memory, the processor configured to perform a decoding method according to any of the embodiments described above based on instructions stored in the memory.

According to a fifth aspect of embodiments of the present disclosure, there is provided a communication system comprising: an encoder as in any above; a decoder as in any above embodiments.

According to a sixth aspect of embodiments of the present disclosure, there is provided a computer readable storage medium, wherein the computer readable storage medium stores computer instructions which, when executed by a processor, implement a method as in any of the embodiments described above.

Other features of the present disclosure and its advantages will become apparent from the following detailed description of exemplary embodiments of the disclosure, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a flow chart of an encoding method according to an embodiment of the present disclosure;

2-6 are schematic illustrations of longitudinal and transverse subsections of some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of an encoder according to one embodiment of the present disclosure;

FIG. 8 is a flow chart of a decoding method according to an embodiment of the disclosure;

9-10 are schematic views of cross-bar subsections of some embodiments of the present disclosure;

FIG. 11 is a schematic diagram of a decoder according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a communication system according to an embodiment of the present disclosure.

It should be understood that the dimensions of the various elements shown in the figures are not drawn to actual scale. Further, the same or similar reference numerals denote the same or similar members.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative, and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, and the numerical values set forth in these examples should be construed as merely illustrative, and not limiting unless specifically stated otherwise.

The use of the terms "comprising" or "including" and the like in this disclosure means that elements preceding the term encompass the elements recited after the term, and does not exclude the possibility of also encompassing other elements.

All terms (including technical or scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs, unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

Fig. 1 is a flow chart illustrating an encoding method according to an embodiment of the present disclosure. In some embodiments, the following encoding method is performed by an encoder.

In step 101, an initial bit sequence of length N is processed to generate m initial w transversal subsections of length N, the initial bit sequence comprising source information bits, freeze bits and null bits.

In some embodiments, N, m and n are each an integer power of 2.

In step 102, the m initial w transverse subsections are subjected to w- > b subsection transformation processing to generate m initial b transverse subsections with a length of n, wherein among the m initial b transverse subsections, h initial b transverse subsections comprise mixed bits and null bits, and q initial b transverse subsections comprise null bits, and m=h+q.

It should be noted that the w- > b sub-segment transform is a sub-segment transform from the w sub-segment to the b sub-segment.

In some embodiments, in m initial b lateral subsections: the 1 st to the s-th bits of the 1 st to the h th initial w-th transversal sub-segments consist of source information bits and freeze bits, and the s+1-th to the s+r-th bits consist of null bits. The h+1th to h+q th initial w transverse subsections consist of null bits.

In some embodiments, the w- > b sub-segment transform is processed as a multi-bit exclusive-or operation. The mixed bits in the initial b transversal sub-segment are obtained by exclusive-or operation of the source information bits, the freeze bits and the null bits in the initial w transversal sub-segment. The null bits in the initial b transversal sub-segment are obtained by exclusive-or operation of at least one null bit in the initial w transversal sub-segment.

For example, the w- > b sub-segment transformation formula is as follows:

where j=1, 2,3,..n.

In step 103, the same-position bits in the m initial b transversal sub-segments are combined to generate s initial b longitudinal sub-segments comprising mixed bits and null bits and r initial b longitudinal sub-segments comprising null bits, n=s+r, respectively.

In some embodiments, in n initial b longitudinal subsections: the 1 st bit to the h bit in the 1 st initial b longitudinal subsection to the s th initial b longitudinal subsection are respectively generated by source information bit, frozen bit and null bit through exclusive OR operation, and the h+1th bit to the h+q bit are generated by null bit through exclusive OR operation; bits in the s+1th initial b-longitudinal subsection to the s+r-th initial b-longitudinal subsection are generated from null bits by exclusive-or operations.

For example, the initial b longitudinal subsections are shown in FIG. 2.

As shown in fig. 2, the n initial b longitudinal subsections are divided into two categories. First category: b independent of w transverse sub-segment check code _ij /bc _ij The method comprises the steps of s longitudinal subsections in each subsection, wherein each b longitudinal subsection comprises q longitudinal subsection check code bits and h non-longitudinal subsection check code bits, and the q longitudinal subsection check code bits in each b longitudinal subsection are irrelevant to w longitudinal subsections check codes and w transverse subsections check codes. The second category: bcc obtained by transforming r w transverse sub-segment check code bits through w-b sub-segments _ij R b longitudinal subsections in the subsection, each b longitudinal subsection contains m b transverse subsections check code same position bits.

In step 104 s initial b longitudinal subsections are used to generate s b longitudinal subsections of length m comprising b longitudinal subsection check codes, b longitudinal subsection check code bits of s b longitudinal subsections are used and q temporary b transverse subsections of length n are composed of null bits of r longitudinal subsections.

In some embodiments, generating s b-longitudinal subsections of length m comprising b-longitudinal subsections check codes using s initial b-longitudinal subsections comprises: and performing check code generation operation on the mixed bits in the s initial b longitudinal subsections to obtain s b longitudinal subsections with the length m, wherein the s b longitudinal subsections comprise b longitudinal subsection check codes.

In step 105, m b transversal subsections including b transversal subsection check codes are generated using the h initial b transversal subsections and the q temporary b transversal subsections.

In some embodiments, a check code generation operation is performed on mixed bits in the h initial b transversal subsections to generate h b transversal subsections of length n containing b transversal subsections check codes. And performing check code generation operation on the mixed bits in the q temporary b transverse subsections and the b longitudinal subsections check code bits to generate q b transverse subsections with the length of n and containing the b transverse subsections check code.

In some embodiments, generating m b transversal subsections including b transversal subsections check codes using h initial b transversal subsections and q temporary b transversal subsections includes: m B-transversal subsections comprising h initial B-transversal subsections and q temporary B-transversal subsections are spliced into k B-transversal subsections, each B-transversal subsection comprising one or more B-transversal subsections. And respectively performing check code generation operation on the mixed bits in the k B transverse subsections and the B longitudinal subsections so as to generate B transverse subsections check codes of the k B transverse subsections.

For example, if k=1, there is only one B transversal sub-segment, which includes all m B transversal sub-segments, which includes one check code, and the check code bits are located in the check code bits of the m B transversal sub-segments.

If k is more than 1 and less than m, at least one B transverse sub-segment comprises a plurality of B transverse sub-segments, each B transverse sub-segment comprises a check code, and check code bits in each B transverse sub-segment are positioned in check code bits in the corresponding B transverse sub-segment.

If k=m, each B-transversal sub-segment serves as a B-transversal sub-segment, each B-transversal sub-segment includes a check code, and the check code bits in each B-transversal sub-segment are located in the check code bits in the corresponding B-transversal sub-segment.

In step 106, the m b transversal sub-segments are b- > w sub-segment transformed to generate m w transversal sub-segments.

It should be noted that the b- > w sub-segment transform is a sub-segment transform from the b sub-segment to the w sub-segment. The b- > w sub-segment transformation and the w- > b sub-segment transformation are inverse to each other.

For example, the b- > w sub-segment transform formula is as follows:

where j=1, 2,3,..n.

In step 107, the m w transversal subsections are combined into a bit sequence to be encoded of length N.

In step 108, the bit sequence to be encoded with length N is encoded, and a coded bit sequence is obtained and transmitted.

In some embodiments, the codes are polarization code codes.

Embodiments of the present disclosure are described below by way of specific examples.

Embodiment one: k=m, corresponding to the crossbar parity case

Segmenting an original bit sequence to be coded with a length of N according to a preset rule to obtain m initial w transverse subsections with a bit length of N, wherein each of the 1 st to m-1 st initial w transverse subsections comprises N-1 bits which are composed of source information bits and frozen bits, and an initial parity check code bit wcc _in (null bits), i=1, 2,3,..m-1, the m-th initial w transverse sub-segment contains the initial parity check code (null bits) of n initial w longitudinal sub-segments, where the initial parity check code wc of n-1 w longitudinal sub-segments _mj (null bit)) Initial parity code wcc for j=1, 2,3,..n-1, and 1 bit mth initial w transverse sub-segment _mn (null bits) as shown in fig. 3.

In FIG. 3, w _ij Sub-blocks: i=1, 2,3,..m-1, j=1, 2,3,..n-1. wc (what is a Chinese character) _mj Sub-blocks: j=1, 2,3,..n-1. wcc _in Sub-blocks: i=1, 2,3,..m.

Wherein N, m and N are the whole powers of 2, n=mjn. Wc in FIG. 3 _mj And wcc _in Is only an example, not the only wc _mj The location of (2) needs to satisfy two conditions: information bit wc _mj In the same row, j=1, 2,3,..n-1; wcc _in Also two conditions need to be met for the position of (c): information bit, wcc _in In the same column, i=1, 2,3,..m.

The method comprises the steps of respectively carrying out w-b sub-segment transformation on m initial w transverse sub-segments to obtain m initial b transverse sub-segments, wherein bits at the same position in the m initial b transverse sub-segments form n initial b longitudinal sub-segments, and the n initial b longitudinal sub-segments are divided into two groups: a first group of mixed bits, b, obtained by exclusive-or operation of source information bits, freeze bits and initial parity code bits (null bits) in the initial w transversal sub-segments _i1 /bc _i1 N-1 initial b longitudinal subsections in the sub-block, each initial b longitudinal subsection contains m-1 mixed bits obtained by exclusive OR operation of source information bits, frozen bits and null bits in the initial w subsection and 1 null bit obtained by transformation of the initial parity check code bits (null bits) in the initial w subsection from w- > b subsections. A second group of bcc obtained by transforming n initial parity check code bits (null bits) in m initial w transverse subsections by w- & gt b subsections _i1 1 initial b longitudinal sub-segment of length m in the sub-block, the initial b longitudinal sub-segment containing m bits as m b transverse sub-segment check code bits, as shown in fig. 4.

In FIG. 4, b _ij Sub-blocks: i=1, 2,3,..m-1, j=1, 2,3,..n-1. bc (bc) _mj Sub-blocks: j=1, 2,3,..n-1. bcc (bcc) _in Sub-blocks: i=1, 2,3,..m.

Wherein bc is as follows _mj And bcc (bcc) _in Is only an example and is not unique, the specific location is wc in w-bit space _mj /wcc _in And w- & gt b sub-segment transformation formula.

In the process of generating the b longitudinal sub-segment parity check codes, respectively for b _ij Performing parity check code generation operation on m-1 mixed bits in n-1 initial b longitudinal subsections in the subblock to obtain n-1 b longitudinal subsection check codes bc _mj J=1, 2,3,..n-1, n-1 b longitudinal sub-segment parity check codes and b, respectively _ij The corresponding m-1 mixed bits in the n-1 b longitudinal subsections in the sub-block constitute n-1 b longitudinal subsections.

In generating the b-transversal sub-segment parity check code, bc _ij A temporary b-transversal sub-segment consisting of parity codes and a null bit in n-1 b-longitudinal sub-segments in the sub-block.

B in m-1 initial b transverse subsections respectively _ij The mixed bits in the sub-blocks are subjected to parity check code generation operation to obtain m-1 b transverse sub-segment parity check codes, and the m-1 b transverse sub-segment parity check codes and b in the corresponding m-1 b transverse sub-segments _ij The mixed bits in the sub-blocks respectively constitute m-1 b transversal sub-segments. Finally, for a bc _mj And performing check code generation operation on a b longitudinal sub-segment check code bit sequence with the length of n-1 in the temporary b transverse sub-segment in the sub-block to obtain a b transverse check code, wherein the generated check code replaces a null bit in the temporary b transverse sub-segment.

Next, through the transformation of the b-w subsections, m w transverse subsections are obtained, the subsections are combined to obtain a bit sequence to be encoded with the length of N, and the bit sequence to be encoded with the length of N is encoded by a polarization code encoder to obtain an encoded bit sequence.

Embodiment two: k is more than or equal to 1 and less than m, and longitudinal parity check and transverse cyclic redundancy check are performed

Segmenting an original bit sequence to be coded with the length of N according to a preset rule to obtain m initial w transverse subsections with the bit length of N, wherein each of the 1 st to m-1 st initial w transverse subsections comprises total s bits consisting of source information bits and frozen bits, and r initial b transverse subsectionsIs the initial check code bit wcc of (2) _ij (null bits), i=1, 2,3,..m; j=s+1, s+2, s+3,..s+r; the m-th initial w transverse sub-segment contains s initial w longitudinal sub-segments of initial parity check codes wc _ij (null bits), i=m; j=1, 2,3,..s, and r initial CRC bits wcc for the initial w transverse subsections _ij (null bits), i=m; j=s+1, s+2, s+3,..s+r, as shown in fig. 5.

In FIG. 5, w _ij Sub-blocks: i=1, 2,3,..m-1, j=1, 2,3,..s. wc (what is a Chinese character) _ij Sub-blocks: i=m, j=1, 2,3,..s. wcc _ij Sub-blocks: i=1, 2,3,..m, j=s+1, s+2, s+3,..s+r.

Where N, m and N are the whole powers of 2, n=mjn, r is the length of the check code, s+r=n, and the initial check code bits are used only in the polarization code bit sequence u ₁ ^N The w bits of the spatial check code information bits are predetermined and occupy information bits, the initial check code bits being typically 0. Typically the freeze bit is 0. Wc in FIG. 5 _ij And wcc _ij Is only an example, not the only one, wc _ij The location of (2) needs to satisfy two conditions: information bit wc _ij In the same row, j=1, 2,3,..s; wcc _ij Also two conditions need to be met for the position of (c): information bit, wcc _ij In the same column, i=1, 2,3,..m.

And respectively carrying out w-b sub-segment transformation on the m initial w transverse sub-segments to obtain m initial b transverse sub-segments, wherein bits at the same position in the m initial b transverse sub-segments form n initial b longitudinal sub-segments, and the n initial b longitudinal sub-segments are divided into two groups. A first group: mixed bit, b, obtained by exclusive-or operation of source information bit, freeze bit and initial parity code bit (null bit) in initial w transverse sub-segment _ij /bc _ij And s initial b longitudinal subsections in the subsection, wherein each initial b longitudinal subsection comprises m-1 mixed bits obtained by exclusive OR operation of source information bits, frozen bits and null bits in the initial w subsection and 1 null bit obtained by transformation of the initial parity check code bits (null bits) in the initial w subsection from the w- > b subsection. Second group: from the following components Bcc obtained by transforming w- & gt sub-segments of initial CRC check code bits (null bits) in m initial w transverse sub-segments _i1 The r initial b-longitudinal subsections in the sub-block, each of which contains m bits as m b-transverse subsegment check code bits, as shown in fig. 6.

In FIG. 6, b _ij Sub-blocks: i=1, 2,3,..m-1, j=1, 2,3,..s. bc (bc) _ij Sub-blocks: i=m, j=1, 2,3,..s. bcc (bcc) _ij Sub-blocks: i=1, 2,3,..m, j=s+1, s+2, s+3,..s+r. Wherein bc is as follows _mj And bcc (bcc) _ij Is only an example and is not unique, the specific location is wc in w-bit space _mj /wcc _ij And w- & gt b sub-segment transformation formula.

In the process of generating the b longitudinal sub-segment parity check codes, respectively for b _ij Performing parity check code generation operation on m-1 mixed bits in s initial b longitudinal subsections in the subblock to obtain s b longitudinal subsection check codes bc _mj J=1, 2,3,..s, s b longitudinal sub-segment parity check codes and b, respectively _ij The corresponding m-1 mixed bits in the s initial b longitudinal subsections in the sub-block constitute s b longitudinal subsections.

In the process of generating the b transverse subsegment CRC check code, bc _ij The parity check codes in s b longitudinal subsections in the subsections and r null bits form a temporary b transverse subsection.

Splicing m-1 initial B transverse subsections and 1 temporary B transverse subsections into k to-be-checked codes according to a preset sequence to generate B transverse subsections, wherein each to-be-checked code generation B transverse subsection comprises one or more initial B transverse subsections and zero or 1 temporary B transverse subsections, performing CRC check code generation operation on mixed bits in the k to-be-checked code generation B transverse subsections to obtain CRC check codes of k B transverse subsections, and the CRC check code of each B transverse subsection is bcc of one or more B transverse subsections of the same B transverse subsection _ij The CRC check code bits are allocated to one or more b-transversal subsections, each b-transversal subsection containing r CRC check code bits, according to a predetermined position, etc.

Fig. 7 is a schematic structural diagram of an encoder according to another embodiment of the present disclosure. As shown in fig. 7, the encoder includes a memory 71 and a processor 72.

The memory 71 is for storing instructions and the processor 72 is coupled to the memory 71, the processor 72 being configured to perform a method as referred to in any of the embodiments of fig. 1 based on the instructions stored by the memory.

As shown in fig. 7, the encoder further comprises a communication interface 73 for information interaction with other devices. Meanwhile, the encoder further includes a bus 74, and the processor 72, the communication interface 73, and the memory 71 perform communication with each other through the bus 74.

The memory 71 may comprise a high-speed RAM memory or may further comprise a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 71 may also be a memory array. The memory 71 may also be partitioned and the blocks may be combined into virtual volumes according to certain rules.

Further, the processor 72 may be a central processing unit CPU, or may be an application specific integrated circuit ASIC, or one or more integrated circuits configured to implement embodiments of the present disclosure.

The present disclosure also relates to a computer readable storage medium having stored thereon computer instructions which, when executed by a processor, implement a method as referred to in any of the embodiments of fig. 1.

Fig. 8 is a flow chart illustrating a decoding method according to an embodiment of the disclosure. In some embodiments, the following decoding method is performed by a decoder.

In step 801, a received bit sequence to be decoded with a length N is divided into m transverse subsections to be decoded with a length N, where the bit sequence to be decoded with a length N is a log likelihood ratio sequence.

In some embodiments, N, m and n are each an integer power of 2.

In step 802, the m lateral subsections to be decoded are independently decoded to obtain a decoding result of the a lateral subsection with m L alternative paths.

In some embodiments, the decoding process is an SCL decoding process.

In step 803, the bits in the same alternative path in the m a-transversal subsections, which are identical in position, are combined to generate s a-longitudinal subsections, wherein the s a-longitudinal subsections do not include an a-longitudinal subsection consisting of a-transversal subsections check codes.

At step 804, the m a lateral subsections are each checked to preserve the alternate paths that pass the check.

In some embodiments, parity is performed on each a-transversal sub-segment, and if there is an alternative path that passes parity, then the alternative path that does not pass parity is deleted, where bits at the same position on the multiple alternative paths that pass parity in each a-transversal sub-segment are divided into a single value bit and a split value bit, where the single value bit is 0 or 1, and the split value bit has both 0 and 1.

For example, verifying s a longitudinal subsections includes: and respectively concatenating the values of m bits in the s a longitudinal subsections into a plurality of alternative paths according to single value bits or split value bits, wherein 0 and 1 of the split value bits respectively participate in path combination, and reserving Lv alternative paths with the maximum occurrence probability.

And respectively carrying out parity check on Lv alternative paths of each a longitudinal subsection in the s a longitudinal subsections, wherein if the bits at the same position in a plurality of alternative paths passing through the parity check are all single-value bits, the corresponding single-value bits are the check result of the corresponding bits of the a transverse subsections, and deleting the alternative paths with inconsistent values of the corresponding bits in the alternative paths reserved in the a transverse subsections and the single-value bits. If only one alternative path is reserved currently, taking m bit values in the alternative path as decoding results of corresponding bits in m SCL decoders. If a plurality of alternative paths are reserved currently, taking m bit values in the alternative path with the largest occurrence probability as decoding results of corresponding bits in m SCL decoders.

In other embodiments, verifying the m a lateral subsections separately includes: the m a transverse subsections Duan Pinjie are divided into k a transverse subsections, each a transverse subsection comprises one or more a transverse subsections, and k is a positive integer which is more than 1 and less than or equal to m. And respectively checking the k transverse A subsections, and if an alternative path passing the check exists, deleting the alternative path not passing the check. Splitting the a transverse subsections so as to take the obtained a transverse subsections as corresponding decoding results, wherein bits at the same position on a plurality of alternative paths passing verification in each a transverse subsections are divided into single-value bits and split-value bits, the single value is 0 or 1, and the split values simultaneously have 0 and 1.

In some embodiments, verifying the k a transverse subsections separately includes: and respectively performing CRC check, parity check or CRC and parity combination check on the k A transverse subsections.

In some embodiments, dividing the m a-transversal subsections Duan Pinjie into k a-transversal subsections comprises: in the k-th group, the parameter i=1 is taken. Combining the L alternative paths in the ith a-transversal subsection with the L alternative paths of the 1 st a-transversal subsection to obtain L ² Alternate paths are striped. Will L ² The L alternative paths with the highest occurrence probability among the alternative paths are used as L alternative paths of the (i+1) th a transverse subsection. The parameter i is updated with i=i+1. If i < M, repeating the step of combining the L alternative paths in the ith a-transversal sub-segment and the L alternative paths of the (i+1) th a-transversal sub-segment. If i=m, the L alternative paths with the largest occurrence probability are taken as alternative paths of the k-th group a sub-segment.

In some embodiments, verifying the s a longitudinal subsections includes: and respectively concatenating the values of m bits in the s a longitudinal subsections into a plurality of alternative paths according to single value bits or split value bits, wherein the two split values respectively participate in path combination, and reserving Lv alternative paths with the maximum occurrence probability. And respectively carrying out parity check on Lv alternative paths of each a longitudinal subsection in the s a longitudinal subsections, wherein if the bits at the same position in the alternative paths passing through the parity check are all single-value bits, the corresponding single value is a check result of the corresponding bit of the a transverse subsection, and deleting the value of the corresponding bit in the alternative paths reserved in the a transverse subsection and the alternative paths with inconsistent single value. If only one alternative path is reserved currently, taking m bit values in the alternative path as decoding results of corresponding bits in m SCL decoders. If a plurality of alternative paths are reserved currently, taking m bit values in the alternative path with the largest occurrence probability as decoding results of corresponding bits in m SCL decoders.

In step 805, s a longitudinal subsections are checked to obtain m decoding results.

In step 806, the m decoding results are processed to obtain a decoded bit sequence.

In some embodiments, the m decoding results are subjected to sub-segment transformation to obtain m v sub-segments, and the m v sub-segments are subjected to correction processing to obtain m corrected v sub-segments. For example, the h+1th to h+qth a lateral subsections and the v subsections are exclusive-ored to obtain m corrected v subsections.

Next, the m modified v sub-segments are sub-segment combined to obtain a decoded bit sequence.

Embodiment three, crossbar parity

The received bit sequence to be decoded with the length of N is processed to obtain m decoding results of a transverse subsections containing L alternative paths, as shown in fig. 9.

In FIG. 9, a _ij Sub-blocks: i=1, 2,3,..m-1, j=1, 2,3,..n-1. ac _mj Sub-blocks: j=1, 2,3,..n-1. acc (acc) _in Sub-blocks: i=1, 2,3,..m.

Wherein a is _ij /ac _mi Each a-longitudinal sub-segment in the sub-block comprises a length-1 a-longitudinal sub-segment parity check code, acc _in Each a-transversal sub-segment in the sub-block contains a length 1 a-transversal sub-segment parity check code. Ac in FIG. 9 _mj And acc (sic) _in Is only an example and is not unique, a specific location and bc in sender b bit space _mj /bcc _in Is identical in position.

In the process of performing parity check on m a transverse subsections, performing parity check on L alternative paths of the m a transverse subsections respectively, reserving alternative paths passing the parity check, and deleting alternative paths not passing the parity check; if no alternative path passes the parity check, then the decoding fails. The bits at the same position on the multiple alternative paths passing the check in each of the m a-transversal subsections are divided into single value bits and split value bits, the single value is 0 or 1, and the split value has both 0 and 1.

In the process of performing the parity check of the s a longitudinal subsections (namely, the judgment of the parity check result of the transverse subsections), the values of m bits in the s a longitudinal subsections are respectively connected in series into a plurality of alternative paths according to single value bits or split value bits, the serial connection process is similar to the construction process of an SC decoding tree, the single value bits are similar to the frozen bits in the SC decoding tree and only one decoding path, and the split value bits are similar to the information bits in the traditional SC decoding tree and are split into 0 and 1 decoding paths.

And respectively executing parity check on the s a vertical subsections, if the same bit in the path passing through the parity check is a single value bit, the corresponding single value 0 or 1 is the parity check result of the corresponding bit of the a horizontal subsection, and the value of the corresponding bit in the alternative path reserved in the parity check of the a horizontal subsection is deleted from the alternative path which is inconsistent with the single value 0 or 1.

The more the number of single-value bits of the same bit in the alternative paths passing through the parity check of the a longitudinal subsections, the more the alternative paths reserved in the parity check of the a transverse subsections are deleted, if only one alternative path is left finally, m bit values in the alternative paths are used as decoding results of corresponding bits in an SCL decoder; if there are still multiple reserved alternative paths, taking m bit values in the alternative path with the largest occurrence probability as decoding results of corresponding bits in the SCL decoder.

The reliability of the parity check of the a horizontal sub-segment is further improved through the parity check of the a vertical sub-segment, and the SCL decoding error rate is reduced.

The decoding results of m SCL decoders are converted and processed by the a-v sub-segments and then output as decoders.

Embodiment four: longitudinal parity check-transverse cyclic redundancy check

And processing the received bit sequence to be decoded with the length of N to obtain decoding results of L alternative paths in m a transverse subsections, wherein m bits in the same position of the m a transverse subsections form an a longitudinal subsection, and the length of the a longitudinal subsection is m, as shown in fig. 10.

In FIG. 10, a _ij Sub-blocks: i=1, 2,3,..m-1, j=1, 2,3,..s. ac _ij Sub-blocks: i=m, j=1, 2,3,..s. acc (acc) _ij Sub-blocks: i=1, 2,3,..m, j=s+1, s+2, s+3,..s+r.

Wherein a is _ij /ac _ij Each a-longitudinal sub-segment in the sub-block comprises a length-1 a-longitudinal sub-segment parity check code, acc _ij Each a-transversal sub-segment in the sub-block comprises a sequence of a-transversal sub-segment CRC check code bits of length r. ac _ij And acc (sic) _ij Position of (c) and corresponding bc _ij And bcc (bcc) _ij One-to-one correspondence of locations.

In performing the B-transversal subsections CRC check, one or more a-transversal subsections are spliced into k A-subsections in the same order as the B-transversal subsections, except that multiple alternative paths of the a-transversal subsections need to be spliced at the same time. The specific splicing method comprises the following steps: the L alternative paths of the 1 st a transverse sub-segment and the L alternative paths of the 2 nd a transverse sub-segment in the k groups are combined two by two to obtain L2 alternative paths, the occurrence probability of the L alternative paths of the 2 nd a transverse sub-segment is updated, the L alternative paths with the largest occurrence probability are reserved, then the L alternative paths with the largest occurrence probability are spliced with the L alternative paths of the 3 rd a transverse sub-segment by the same method until the splicing of all the a transverse sub-segments is completed, and then the paths with the largest occurrence probability of the L alternative paths are reserved as alternative paths.

Performing CRC check on L alternative paths of the k A transverse subsections respectively, reserving alternative paths passing the CRC check, and deleting alternative paths not passing the CRC check; if none of the alternative paths passes the CRC check, L alternative paths are reserved. Splitting the A transverse sub-segment into a plurality of corresponding a transverse sub-segments to serve as a verification result of the corresponding SCL decoder. The bits at the same position on the multiple alternative paths through the CRC check in each of the m a-transversal subsections are divided into single value bits and split value bits, single value 0 or 1, with the split value having both 0 and 1.

In the process of performing the parity check of s a longitudinal subsections (determination of the CRC check result of a transverse subsections), the values of m bits in the s a longitudinal subsections are respectively connected in series into a plurality of alternative paths according to single value bits or split value bits, the serial connection process is similar to the construction process of an SC decoding tree, the single value bits are similar to the frozen bits in the SC decoding tree and only one decoding path, and the split value bits are similar to the information bits in the traditional SC decoding tree and are split into 0 and 1 decoding paths.

And respectively carrying out parity check on the s a longitudinal subsections, if the same bit in the path passing through the parity check is a single value bit, judging that the corresponding single value 0 or 1 is the final decoding result of the corresponding bit of the a transverse subsection, and deleting the alternative path with the inconsistent value of the corresponding bit in the alternative path reserved in the CRC check of the a transverse subsection and the single value 0 or 1.

The more the number of single-value bits of the same bit in the path passing through the parity check of the a longitudinal subsection is, the more the alternative paths reserved in the CRC check of the a transverse subsection are deleted, if only one alternative path is left finally, m bit values in the alternative paths are used as decoding results of corresponding bits in the SCL decoder; if there are still multiple reserved alternative paths, taking m bit values in the alternative path with the largest occurrence probability as decoding results of corresponding bits in the SCL decoder.

The a-longitudinal sub-segment parity further improves the reliability of the a-transverse sub-segment CRC check, especially when multiple alternative paths exist to pass the CRC check, reducing SCL decoding error rate.

The decoding result of the m sub-segment SCL decoders is output as a decoder after a-v sub-segment conversion and corresponding processing.

Fig. 11 is a schematic diagram of a decoder according to an embodiment of the disclosure. As shown in fig. 11, the decoder includes a memory 111, a processor 112, a communication interface 113, and a bus 11. Fig. 11 differs from fig. 7 in that in the embodiment shown in fig. 11, the processor 112 is configured to perform a method as referred to in any of the embodiments of fig. 8 based on instructions stored in the memory 111.

Fig. 12 is a schematic structural diagram of a communication system according to an embodiment of the present disclosure. As shown in fig. 12, the communication system includes an encoder 121 and a decoder 122. The encoder 121 is an encoder according to any one of the embodiments in fig. 7, and the decoder 122 is a decoder according to any one of the embodiments in fig. 11.

By implementing the above embodiments of the present disclosure, the following advantageous effects can be obtained:

1) The reliability of the a transverse sub-segment verification is further improved through the a longitudinal sub-segment verification, and the SCL decoding error rate is reduced.

2) and the vertical subsection a is checked, and the burst interference errors in the horizontal subsection a are scattered into different vertical subsections for checking, so that channel interleaving encoding and decoding are not needed, the complexity of the system is reduced, and the processing time is shortened.

3) Different verification modes can be flexibly adopted according to different requirements of coding rate, bit error rate/block error rate, different code lengths and different sub-sections: parity, cyclic redundancy check, different combinations of parity and cyclic redundancy check.

In some embodiments, the functional modules described above may be implemented as general-purpose processors, programmable logic controllers (Programmable Logic Controller, abbreviated as PLCs), digital signal processors (Digital Signal Processor, abbreviated as DSPs), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASICs), field programmable gate arrays (Field-Programmable Gate Array, abbreviated as FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any suitable combination thereof for performing the functions described herein.

Thus, embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concepts of the present disclosure, some details known in the art are not described. How to implement the solutions disclosed herein will be fully apparent to those skilled in the art from the above description.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that the foregoing embodiments may be modified and equivalents substituted for elements thereof without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method of encoding, comprising:

processing an initial bit sequence with the length of N to generate m initial w transverse subsections with the length of N, wherein the initial bit sequence comprises source information bits, frozen bits and null bits;

performing w- > b sub-segment transformation processing on m initial w transverse sub-segments to generate m initial b transverse sub-segments with the length of n, wherein among the m initial b transverse sub-segments, h initial b transverse sub-segments comprise mixed bits and null bits, q initial b transverse sub-segments comprise null bits, and m=h+q;

combining the bits with the same positions in m initial b transverse subsections respectively to generate s initial b longitudinal subsections comprising mixed bits and null bits and r initial b longitudinal subsections comprising null bits, wherein n=s+r;

Generating s b longitudinal subsections with the length of m and comprising b longitudinal subsection check codes by using the s initial b longitudinal subsections, and forming q temporary b transverse subsections with the length of n by using b longitudinal subsection check code bits in the s b longitudinal subsections and null bits in the r longitudinal subsections;

generating m b transverse subsections comprising b transverse subsection check codes by utilizing the h initial b transverse subsections and the q temporary b transverse subsections;

b- > w sub-segment transformation is carried out on the m b transverse sub-segments so as to generate m w transverse sub-segments;

merging the m w transverse subsections into a bit sequence to be coded with the length of N;

and coding the bit sequence to be coded with the length of N to obtain a coded bit sequence and transmitting the coded bit sequence.

2. The method according to claim 1, wherein:

n, m and n are each an integer power of 2;

the code is a polarization code.

3. The method of claim 1, wherein, among m initial b lateral subsections:

the 1 st to the s bit in the 1 st to the h th initial w-direction subsections are composed of source information bits and freeze bits, and the s+1 to the s+r bits are composed of null bits;

the h+1th to h+q th initial w transverse subsections consist of null bits.

4. The method of claim 1, wherein,

the w- > b sub-segment transformation is processed into multi-bit operation;

the mixed bit in the initial b transverse sub-segment is obtained by calculating the source information bit, the frozen bit and the null bit in the initial w transverse sub-segment;

the null bits in the initial b transversal sub-segment are calculated from at least one null bit in the initial w transversal sub-segment.

5. The method of claim 1, wherein, among n initial b longitudinal subsections:

the 1 st bit to the h bit in the 1 st initial b longitudinal subsection to the s th initial b longitudinal subsection are respectively generated by the source information bit, the frozen bit and the null bit through operation, and the h+1th bit to the h+q bit are generated by the null bit through operation;

bits in the s+1th initial b-longitudinal sub-segment to the s+r th initial b-longitudinal sub-segment are generated by a null bit through operation.

6. The method of claim 1, wherein generating s b-longitudinal subsections of length m comprising b-longitudinal subsection check codes using the s initial b-longitudinal subsections comprises:

and performing check code generation operation on the mixed bits in the s initial b longitudinal subsections to obtain s b longitudinal subsections with the length m, wherein the s b longitudinal subsections comprise b longitudinal subsection check codes.

7. The method of claim 1, wherein generating m b-transversal subsections comprising b-transversal subsections check codes using the h initial b-transversal subsections and the q temporary b-transversal subsections comprises:

performing check code generation operation on the mixed bits in the h initial b transverse subsections to generate h b transverse subsections with the length of n and containing b transverse subsections check codes;

and performing check code generation operation on the mixed bits in the q temporary b transverse subsections and the b longitudinal subsection check code bits to generate q b transverse subsections with the length of n and containing the b transverse subsections check code.

8. The method of claim 1, wherein,

the b- > w sub-segment transformation and the w- > b sub-segment transformation are inverse to each other.

9. The method of claim 1, wherein generating m b-transversal subsections comprising b-transversal subsections check codes using the h initial b-transversal subsections and the q temporary b-transversal subsections comprises:

splicing m B transverse subsections comprising the h initial B transverse subsections and the q temporary B transverse subsections into k B transverse subsections, wherein each B transverse subsection comprises one or more B transverse subsections;

and respectively performing check code generation operation on the mixed bits in the k B transverse subsections and the B longitudinal subsections so as to generate B transverse subsections check codes of the k B transverse subsections.

10. The method of claim 9, wherein,

b the vertical sub-segment check code comprises a cyclic redundancy check code, a parity check code, or a combination of a cyclic redundancy check code and a parity check code.

11. The method of claim 9, wherein,

if k=1, only one B transversal sub-segment is provided, the one B transversal sub-segment comprising all m B transversal sub-segments, the B sub-segment comprising a check code, and the check code bits being located in the check code bits of the m B transversal sub-segments;

if k is more than 1 and less than m, at least one B transverse sub-segment comprises a plurality of B transverse sub-segments, each B transverse sub-segment comprises a check code, and check code bits in each B transverse sub-segment are positioned in check code bits in the corresponding B transverse sub-segment;

12. An encoder, comprising:

a memory configured to store instructions;

a processor coupled to the memory, the processor configured to perform the method of any of claims 1-11 based on instructions stored by the memory.

13. A method of decoding, comprising:

dividing a received bit sequence to be decoded with the length of N into m transverse subsections to be decoded with the length of N, wherein the bit sequence to be decoded with the length of N is a log likelihood ratio sequence;

independently carrying out code-polishing processing on the m transverse subsections to be decoded to obtain a decoding result of m a transverse subsections with L alternative paths;

respectively combining bits with the same position in the same alternative path in m a transverse subsections to generate s a longitudinal subsections, wherein the s a longitudinal subsections do not comprise a longitudinal subsections consisting of a transverse subsections check codes;

respectively checking m a transverse subsections so as to reserve alternative paths passing the check;

checking the s longitudinal subsections a to obtain m decoding results;

and processing the m decoding results to obtain a decoding bit sequence.

14. The method of claim 13, wherein,

n, m and n are each an integer power of 2;

the decoding process is an SCL decoding process.

15. The method of claim 13, wherein processing the m SCL decoding results to obtain a decoded bit sequence comprises:

sub-segment transformation is carried out on m decoding results to obtain m v sub-segments;

Carrying out correction processing on the m v sub-segments to obtain m corrected v sub-segments;

and merging the m corrected v sub-segments to obtain a decoding bit sequence.

16. The method of claim 13, wherein verifying the m a lateral subsections, respectively, comprises:

parity checking is performed on each a transverse sub-segment;

if the alternative paths passing through the parity check exist, deleting the alternative paths not passing through the parity check;

wherein the bits at the same position on the multiple alternative paths passing the check in each a transverse subsection are divided into single value bits and split value bits, the single value bits are 0 or 1, and the split value bits have 0 and 1 at the same time.

17. The method of claim 16, wherein verifying s a longitudinal subsections comprises:

respectively concatenating the values of m bits in the s a longitudinal subsections into a plurality of alternative paths according to single value bits or split value bits, wherein 0 and 1 of the split value bits respectively participate in path combination, and reserving Lv alternative paths with the maximum occurrence probability;

respectively carrying out parity check on Lv alternative paths of each a longitudinal subsection in the s a longitudinal subsections, wherein if the bits at the same position in a plurality of alternative paths passing through the parity check are single-value bits, the corresponding single-value bits are the check result of the corresponding bits of the a transverse subsections, and deleting the alternative paths with inconsistent values of the corresponding bits in the alternative paths reserved in the a transverse subsections and the single-value bits;

If only one alternative path is reserved currently, taking the alternative path as an SCL decoding result;

if a plurality of alternative paths are reserved currently, the alternative path with the largest occurrence probability is taken as an SCL decoding result.

18. The method of claim 13, wherein verifying the m a lateral subsections, respectively, comprises:

dividing m a transverse subsections Duan Pinjie into k A subsections, wherein each A subsection comprises one or more a transverse subsections, and k is a positive integer which is more than 1 and less than or equal to m;

respectively checking k A subsections;

if the alternative paths passing the verification exist, deleting the alternative paths not passing the verification;

splitting the a sub-segment so as to take the obtained a sub-segment as a corresponding decoding result, wherein bits at the same position on a plurality of alternative paths passing verification in each a sub-segment are divided into single value bits and split value bits, wherein the single value is 0 or 1, and the split value simultaneously has 0 and 1.

19. The method of claim 18, wherein verifying k a subsections separately comprises:

and respectively performing CRC check, parity check or CRC and parity combination check on the k A sub-segments.

20. The method of claim 18, wherein dividing m a transversal subsections Duan Pinjie into k a subsections comprises:

In the k-th group, the parameter i=1 is taken;

combining the L alternative paths in the ith a-transversal subsection with the L alternative paths of the 1 st a-transversal subsection to obtain L ² Alternate paths;

will L ² The L alternative paths with the highest occurrence probability among the alternative paths are used as L alternative paths of the (i+1) th a transverse subsection;

updating the parameter i with i=i+1;

if i is less than M, repeating the step of combining the L alternative paths in the ith a transverse subsection and the L alternative paths of the (i+1) th a transverse subsection;

if i=m, the L alternative paths with the largest occurrence probability are taken as alternative paths of the k-th group a sub-segment.

21. The method of claim 20, wherein combining the L alternative paths in the i-th a-lateral sub-segment and the L alternative paths of the 1-th a-lateral sub-segment comprises:

and combining the L alternative paths in the ith transverse subsection and the L alternative paths of the 1 st transverse subsection according to a serial splicing mode of splicing one by one, a parallel splicing mode of splicing all groups simultaneously after grouping or a serial and parallel mixed splicing mode.

22. The method of claim 18, wherein verifying s a longitudinal subsections comprises:

Respectively concatenating the values of m bits in the s a longitudinal subsections into a plurality of alternative paths according to single value bits or split value bits, wherein the two split values respectively participate in path combination, and reserving Lv alternative paths with the maximum occurrence probability;

respectively carrying out parity check on Lv alternative paths of each a longitudinal subsection in the s a longitudinal subsections, wherein if the bits at the same position in the alternative paths passing through the parity check are all single-value bits, the corresponding single value is a check result of the corresponding bit of the a transverse subsection, and deleting the value of the corresponding bit in the alternative paths reserved in the a transverse subsection and the alternative paths with inconsistent single value;

if only one alternative path is reserved currently, taking the alternative path as a decoding result;

if a plurality of alternative paths are reserved currently, the alternative path with the largest occurrence probability is taken as a decoding result.

23. The method of claim 15, wherein performing correction processing on the m v subsections to obtain m corrected v subsections comprises:

and (3) carrying out operation on the h+1th to h+qh a transverse subsections and the v subsections to obtain m corrected v subsections.

24. A decoder, comprising:

a memory configured to store instructions;

A processor coupled to the memory, the processor configured to perform the method of any of claims 13-23 based on instructions stored by the memory.

25. A communication system, comprising:

the encoder of claim 12;

the decoder of claim 24.

26. A computer readable storage medium storing computer instructions which, when executed by a processor, implement the method of any one of claims 1-11, 13-23.