CN115549698A - Encoding method and encoder, decoding method and decoder, communication system - Google Patents
Encoding method and encoder, decoding method and decoder, communication system Download PDFInfo
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Abstract
The disclosure provides an encoding method, an encoder, a decoding method, a decoder and a communication system, and relates to the field of communication. The encoding method comprises the following steps: acquiring a plurality of bit sequences to be transmitted; and carrying out coding operation on each bit sequence to be transmitted in the plurality of bit sequences to be transmitted by utilizing a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models to obtain a plurality of coded bit sequences, wherein the plurality of frozen bit distribution models are arranged according to a preset sequence. The decoding method comprises the following steps: receiving a group of sequences to be decoded, wherein the sequences to be decoded comprise a plurality of log-likelihood ratio sequences to be decoded; and carrying out decoding operation on each log likelihood ratio sequence to be decoded in the plurality of log likelihood ratio sequences to be decoded by utilizing a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged according to a preset sequence, and the decoder is the same as the plurality of frozen bit distribution models arranged in the corresponding target encoder.
Description
Technical Field
The present disclosure relates to the field of communications, and in particular, to an encoding method, an encoder, a decoding method, a decoder, and a communication system.
Background
In a transmission system of CA-SCL (cyclic redundancy check assisted continuous elimination List) polarization code encoding and decoding, an encoding side and a decoding side adopt completely same frozen bit distribution models, and an SCL decoder directly judges bits as frozen bits (generally 0) no matter what log-likelihood ratio is obtained by calculating the frozen bits. Simulation results show that polar code decoding is very sensitive to the difference of the frozen bit distribution models, namely the frozen bit distribution model adopted by the decoder and the frozen bit distribution model adopted by the encoding side have only slight difference, and the decoding can also fail completely. Therefore, the multi-user transmission based on the polar code freezing bit distribution model can be very easily realized by utilizing the characteristic.
Disclosure of Invention
The inventors found through research that, in the related art, in a scenario of a short code (e.g., 128 bits), a high code rate of a medium code (e.g., N =512, r = 7/8), and a low code rate of the medium code (e.g., N =512, r = 1/8), the difference window length 2P that meets the decoding performance requirement is very small. That is, the number of available frozen bit distribution models is very small, and it is difficult to meet the needs of a large number of users.
Accordingly, the present disclosure provides a coding and decoding scheme, in which a plurality of frozen bit distribution models arranged in a predetermined order are provided on an encoder side and a decoder side, and if the number of the frozen bit distribution models used by the encoder and the decoder is different or the arrangement order of the frozen bit distribution models is different, a decoding failure may occur. Compared with the scheme that the encoder and the decoder are only provided with one frozen bit distribution model, the scheme that the encoder and the decoder are provided with a plurality of frozen bit distribution models arranged according to the preset sequence can effectively enlarge the user scale, and is suitable for multi-user encoding and decoding transmission in the scenes of high code rate of short codes and medium codes and low code rate of the medium codes.
According to a first aspect of the embodiments of the present disclosure, there is provided an encoding method, performed by an encoder, including: acquiring a plurality of bit sequences to be transmitted; and carrying out coding operation on each bit sequence to be transmitted in the plurality of bit sequences to be transmitted by utilizing a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models to obtain a plurality of coded bit sequences, wherein the plurality of frozen bit distribution models are arranged according to a preset sequence, and the plurality of frozen bit distribution models are not identical.
In some embodiments, the encoding operation comprises: arranging each bit sequence to be transmitted by utilizing a corresponding frozen bit distribution model to generate a plurality of bit sequences to be coded; and respectively encoding each bit sequence to be encoded in the plurality of bit sequences to be encoded to generate a plurality of encoded bit sequences.
In some embodiments, separately encoding each of the plurality of bit sequences to be encoded comprises: and respectively carrying out polarization code coding on each bit sequence to be coded in the plurality of bit sequences to be coded.
In some embodiments, arranging each bit sequence to be transmitted with a corresponding frozen bit distribution model to generate a plurality of bit sequences to be encoded includes: respectively carrying out check code generation operation on each bit sequence to be transmitted in the plurality of bit sequences to be coded to obtain a plurality of check codes; and arranging each check code in the plurality of check codes and the corresponding bit sequence to be transmitted by utilizing the corresponding frozen bit distribution model respectively to generate a plurality of bit sequences to be coded.
In some embodiments, the plurality of coded bit sequences is sent to a decoder.
According to a second aspect of embodiments of the present disclosure, there is provided an encoder comprising: a first encoding processing module configured to obtain a plurality of bit sequences to be transmitted; the second encoding processing module is configured to perform encoding operation on each bit sequence to be transmitted in the plurality of bit sequences to be transmitted by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models to obtain a plurality of encoded bit sequences, wherein the plurality of frozen bit distribution models are arranged according to a preset sequence, and the plurality of frozen bit distribution models are not identical.
In some embodiments, the second encoding processing module is configured to arrange each bit sequence to be transmitted with a corresponding frozen bit distribution model to generate a plurality of bit sequences to be encoded, and encode each bit sequence to be encoded in the plurality of bit sequences to be encoded respectively to generate a plurality of encoded bit sequences.
In some embodiments, the second encoding processing module is configured to perform polarization code encoding on each of the plurality of bit sequences to be encoded, respectively.
In some embodiments, the second encoding processing module is configured to perform check code generation operation on each bit sequence to be transmitted in the plurality of bit sequences to be encoded respectively to obtain a plurality of check codes, and arrange each check code in the plurality of check codes and the corresponding bit sequence to be transmitted respectively by using the corresponding frozen bit distribution model to generate the plurality of bit sequences to be encoded.
In some embodiments, the second encoding processing module is configured to send the plurality of encoded bit sequences to a decoder.
According to a third aspect of embodiments of the present disclosure, there is provided an encoder comprising: a memory configured to store instructions; a processor coupled to the memory, the processor configured to perform an encoding method implementing any of the embodiments described above based on instructions stored by the memory.
According to a fourth aspect of the embodiments of the present disclosure, there is provided a decoding method, performed by a decoder, including: receiving a group of sequences to be decoded, wherein the sequences to be decoded comprise a plurality of log-likelihood ratio sequences to be decoded; and performing decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a preset sequence, the plurality of frozen bit distribution models are not completely the same, and the plurality of frozen bit distribution models and the arrangement sequence in the decoder are the same as the plurality of frozen bit distribution models and the arrangement sequence in the corresponding target encoder.
In some embodiments, the coding operation comprises: and carrying out polar code decoding operation on each log likelihood ratio sequence to be decoded in the plurality of log likelihood ratio sequences to be decoded by utilizing a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models.
In some embodiments, the polar code decoding operation comprises: respectively carrying out polarization code decoding on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded according to the sequence to generate a plurality of groups of alternative bit sequences, wherein each group of alternative bit sequences comprises a plurality of alternative bit sequences; checking each group of alternative bit sequences in the multiple groups of alternative bit sequences respectively to obtain multiple decoding bit sequences; and if at least one alternative bit sequence in each group of alternative bit sequences passes the verification, judging that the group of sequences to be decoded comes from a target encoder, and inversely arranging each decoded bit sequence in the plurality of decoded bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
In some embodiments, if at least one of the multiple groups of alternative bit sequences fails to pass the check, determining whether the M groups of sequences to be decoded are from the target encoder according to a check result of the multiple groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded that are continuously received, where M is a positive integer; if at least one alternative bit sequence in each group of alternative bit sequences passes the verification in a plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in M groups of sequences to be decoded which are continuously received, judging that the M groups of sequences to be decoded come from a target encoder, and inversely arranging each decoding bit sequence in the plurality of decoding bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
In some embodiments, if at least one of the multiple sets of candidate bit sequences corresponding to each of the M sets of sequences to be decoded that are received consecutively fails to be checked, it is determined that the M sets of sequences to be decoded are from the non-target encoder.
In some embodiments, the magnitude of the parameter M is positively correlated to the block error rate.
According to a fifth aspect of the embodiments of the present disclosure, there is provided a decoder, including: the decoding device comprises a first decoding processing module, a second decoding processing module and a decoding processing module, wherein the first decoding processing module is configured to receive a group of sequences to be decoded, and the sequences to be decoded comprise a plurality of log-likelihood ratio sequences to be decoded; and the second decoding processing module is configured to perform decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a preset sequence, the plurality of frozen bit distribution models are not completely the same, and the plurality of frozen bit distribution models and the arrangement sequence in the decoder are the same as the plurality of frozen bit distribution models and the arrangement sequence in the corresponding target encoder.
In some embodiments, the second decoding processing module is configured to perform a polar code decoding operation on each of the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model of a preset plurality of frozen bit distribution models.
In some embodiments, the second decoding processing module is configured to perform polarization code decoding on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded respectively according to an order to generate a plurality of groups of alternative bit sequences, where each group of alternative bit sequences includes a plurality of alternative bit sequences, check each group of alternative bit sequences in the plurality of groups of alternative bit sequences respectively to obtain a plurality of decoded bit sequences, determine that the group of sequences to be decoded is from the target encoder if at least one alternative bit sequence in each group of alternative bit sequences passes the check, and perform inverse arrangement on each decoded bit sequence in the plurality of decoded bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
In some embodiments, the second decoding processing module is configured to determine whether the M groups of sequences to be decoded are from the target encoder according to a check result of the multiple groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded that are continuously received if at least one alternative bit sequence in each group of alternative bit sequences in the M groups of sequences to be decoded that are continuously received passes the check, where if at least one alternative bit sequence in each group of alternative bit sequences in the M groups of sequences to be decoded that are continuously received passes the check, it is determined that the M groups of sequences to be decoded are from the target encoder, and each of the multiple decoded bit sequences is inversely arranged by using a corresponding frozen bit distribution model to obtain multiple decoding results.
In some embodiments, the second decoding processing module is configured to determine that the M groups of sequences to be decoded are from the non-target encoder if at least one group of alternative bit sequences in the multiple groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded that are continuously received does not pass the check.
In some embodiments, the magnitude of the parameter M is positively correlated to the block error rate.
According to a sixth aspect of the embodiments of the present disclosure, there is provided a decoder, including: a memory configured to store instructions; a processor coupled to the memory, the processor configured to perform a decoding method implementing any of the embodiments described above based on instructions stored in the memory.
According to a seventh aspect of the embodiments of the present disclosure, there is provided a communication system including: an encoder as in any preceding embodiment; a decoder as claimed in any preceding embodiment.
According to an eighth aspect of embodiments of the present disclosure, there is provided a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which when executed by a processor, implement the method according to any of the embodiments described above.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic flow chart of an encoding method according to an embodiment of the present disclosure;
FIG. 2 is a schematic encoder-side flow diagram according to an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of an encoder according to an embodiment of the present disclosure;
FIG. 4 is a schematic structural diagram of an encoder according to another embodiment of the present disclosure;
FIG. 5 is a flowchart illustrating a decoding method according to an embodiment of the disclosure;
FIG. 6 is a schematic decoder-side flow diagram according to an embodiment of the present disclosure;
FIG. 7 is a block diagram of a decoder according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a decoder according to another embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a communication system according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a flowchart illustrating an encoding method according to an embodiment of the disclosure. In some embodiments, the following encoding method is performed by an encoder.
In step 101, a plurality of bit sequences to be transmitted is obtained.
In step 102, each bit sequence to be transmitted in the plurality of bit sequences to be transmitted is encoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models to obtain a plurality of encoded bit sequences, wherein the plurality of frozen bit distribution models are arranged in a predetermined order.
It should be noted here that the frozen bit distribution model is a distribution rule of the frozen bits in the bit sequence to be encoded, and different frozen bit distribution models are obtained according to different distribution rules of the frozen bits in the bit sequence to be encoded.
The frozen channel distribution model is determined according to the reliability of the polarization channel of the polarization code, the length of the polarization code and the number of information bits. The frozen bit distribution model is determined by the frozen channel distribution model, and the distribution rule of the frozen bits in the bit sequence to be coded is completely the same as the distribution rule of the frozen channel in the polarization channel of the polarization code.
In some embodiments, the encoding operation comprises:
1) And arranging each bit sequence to be transmitted by utilizing a corresponding frozen bit distribution model to generate a plurality of bit sequences to be coded.
In some embodiments, a check code generation operation is performed on each bit sequence to be transmitted in the plurality of bit sequences to be encoded, respectively, to obtain a plurality of check codes. And then, arranging each check code in the plurality of check codes and the corresponding bit sequence to be transmitted by utilizing the corresponding frozen bit distribution model respectively to generate a plurality of bit sequences to be coded.
For example, the 1 st bit sequence to be transmitted and the corresponding check code are arranged by using the 2 nd frozen bit distribution model to obtain the 1 st bit sequence to be encoded. And arranging the 2 nd bit sequence to be transmitted and the corresponding check code by using the 1 st frozen bit distribution model to obtain the 2 nd bit sequence to be coded.
2) And respectively encoding each bit sequence to be encoded in the plurality of bit sequences to be encoded to generate a plurality of encoded bit sequences.
In some embodiments, each of the plurality of bit sequences to be encoded is separately polarization code encoded to generate a plurality of encoded bit sequences.
In some embodiments, a plurality of coded bit sequences are sent to a decoder.
It should be noted that the decoder and the corresponding target encoder are provided with the same set of frozen bit distribution models, that is, the number of the frozen bit distribution models is the same, and the arrangement order is the same. Therefore, the decoder can only successfully decode the sequence to be decoded from the target encoder, and cannot successfully decode the sequence to be decoded from the non-target encoder, so that multi-user transmission based on a polar code freezing bit distribution model is effectively realized.
As shown in fig. 2, at the encoder side, a check code generation operation is performed on each bit sequence to be transmitted in a plurality of bit sequences to be encoded, respectively, to obtain a plurality of check codes.
And then, arranging each check code in the plurality of check codes and the corresponding bit sequence to be transmitted by utilizing the corresponding frozen bit distribution model in the frozen bit distribution model group respectively to generate a plurality of bit sequences to be coded.
Next, each of the plurality of bit sequences to be encoded is polarization code encoded to generate a plurality of encoded bit sequences, and the plurality of encoded bit sequences are transmitted to the decoder side through a channel.
Fig. 3 is a schematic structural diagram of an encoder according to an embodiment of the present disclosure. As shown in fig. 3, the encoder includes a first encoding processing module 31 and a second encoding processing module 32.
The first encoding processing module 31 is configured to obtain a plurality of bit sequences to be transmitted.
The second encoding processing module 32 is configured to perform an encoding operation on each of the plurality of bit sequences to be transmitted by using a corresponding frozen bit distribution model of a plurality of preset frozen bit distribution models, so as to obtain a plurality of encoded bit sequences, where the plurality of frozen bit distribution models are arranged in a predetermined order, and the plurality of frozen bit distribution models are not identical.
In some embodiments, the second encoding processing module 32 arranges each bit sequence to be transmitted by using the corresponding frozen bit distribution model to generate a plurality of bit sequences to be encoded, and encodes each bit sequence to be encoded in the plurality of bit sequences to be encoded respectively to generate a plurality of encoded bit sequences.
For example, the second encoding processing module 32 performs polarization code encoding on each bit sequence to be encoded in the plurality of bit sequences to be encoded, respectively, to generate a plurality of bit sequences to be encoded.
In some embodiments, the second encoding processing module 32 performs check code generation operation on each bit sequence to be transmitted in the plurality of bit sequences to be encoded respectively to obtain a plurality of check codes, and arranges each check code in the plurality of check codes and the corresponding bit sequence to be transmitted by using the corresponding frozen bit distribution model respectively to generate the plurality of bit sequences to be encoded.
In some embodiments, the second encoding processing module 32 sends a plurality of encoded bit sequences to the decoder.
It should be noted that the decoder and the encoder are provided with the same frozen bit distribution model group, that is, the frozen bit distribution models in the frozen bit distribution model group are not exactly the same, the number of the frozen bit distribution models is the same, and the arrangement order is the same. Therefore, the decoder can be ensured to successfully decode only the sequence to be decoded from the target encoder, and the sequence to be decoded from the non-target encoder cannot be successfully decoded, so that multi-user transmission based on a polar code freezing bit distribution model is effectively realized.
Fig. 4 is a schematic structural diagram of an encoder according to another embodiment of the present disclosure. As shown in fig. 4, the encoder includes a memory 41 and a processor 42.
The memory 41 is used for storing instructions, the processor 42 is coupled to the memory 41, and the processor 42 is configured to execute the method according to any embodiment in fig. 1 based on the instructions stored in the memory.
As shown in fig. 4, the encoder further comprises a communication interface 43 for information interaction with other devices. Meanwhile, the encoder further comprises a bus 44, and the processor 42, the communication interface 43 and the memory 41 are communicated with each other through the bus 44.
The memory 41 may comprise a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 41 may also be a memory array. The storage 41 may also be partitioned, and the blocks may be combined into virtual volumes according to certain rules.
Further, the processor 42 may be a central processing unit CPU, or may be an application specific integrated circuit ASIC, or one or more integrated circuits configured to implement embodiments of the present disclosure.
The present disclosure also relates to a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the instructions, when executed by a processor, implement the method according to any one of the embodiments in fig. 1.
Fig. 5 is a flowchart illustrating a decoding method according to an embodiment of the disclosure. In some embodiments, the following decoding method is performed by a decoder.
In step 501, a set of sequences to be decoded is received, where the sequences to be decoded include a plurality of log-likelihood ratio sequences to be decoded.
In step 502, a decoding operation is performed on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a predetermined order, the plurality of frozen bit distribution models are not completely the same, and the plurality of frozen bit distribution models and the arrangement order in the decoder are the same as the plurality of frozen bit distribution models and the arrangement order in the corresponding target encoder.
In some embodiments, the decoding operation includes: and carrying out polar code decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by utilizing a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models.
For example, the above-mentioned polar code decoding operation includes:
1) And respectively carrying out polarization code decoding on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded according to the sequence to generate a plurality of groups of alternative bit sequences, wherein each group of alternative bit sequences comprises a plurality of alternative bit sequences.
For example, each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded is subjected to CA-SCL decoding or PC-CA-SCL decoding respectively according to the sequence to generate a plurality of groups of alternative bit sequences.
2) And checking each group of alternative bit sequences in the plurality of groups of alternative bit sequences respectively to obtain a plurality of decoding bit sequences.
3) If at least one alternative bit sequence in each group of alternative bit sequences passes the verification, judging that the received group of sequences to be decoded comes from the target encoder, and inversely arranging each decoded bit sequence in the plurality of decoded bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results. A polar code that does not pass the verification may be referred to herein as a block error.
It should be noted that the reverse arrangement performed by the decoder and the arrangement performed by the target encoder are reciprocal operations.
In some embodiments, if at least one of the multiple sets of candidate bit sequences fails to pass the check, it is determined whether each of the M sets of sequences to be decoded is from the target encoder according to a check result of the multiple sets of candidate bit sequences corresponding to the each of the M sets of sequences to be decoded that are continuously received, where M is a positive integer.
If at least one alternative bit sequence in each group of alternative bit sequences passes the verification in a plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in M groups of sequences to be decoded which are continuously received, judging that the M groups of sequences to be decoded come from a target encoder, and inversely arranging each decoded bit sequence in the plurality of decoded bit sequences by utilizing a corresponding frozen bit distribution model to obtain a plurality of decoding results.
And if at least one group of alternative bit sequences in a plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded which are continuously received does not pass the check, judging that the M groups of sequences to be decoded are from the non-target encoder.
It should be noted here that if one of the multiple sets of candidate bit sequences fails to check, the candidate bit sequences may be caused by channel noise interference, or may be caused by setting different sets of frozen bit distribution models for the non-target encoder. In this case, it is necessary to perform decoding operation on a plurality of sets of sequences to be decoded that are continuously received, and if at least one alternative bit sequence in each set of alternative bit sequences passes verification in a plurality of sets of alternative bit sequences corresponding to each set of sequences to be decoded in M sets of sequences to be decoded that are continuously received, it is determined that the M sets of sequences to be decoded are from the target encoder. And if at least one group of alternative bit sequences in the multiple groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded which are continuously received do not pass the verification, judging that the M groups of sequences to be decoded are from the non-target encoder.
In some embodiments, the magnitude of the parameter M is positively correlated with the block error rate. The larger the block error rate is, the larger the number of groups of the continuously received sequences to be decoded is, and the smaller the block error rate is, the smaller the number of groups of the continuously received sequences to be decoded is.
As shown in fig. 6, at the decoder side, CA-SCL decoding or PC-CA-SCL decoding is performed on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded, respectively, in order to generate a plurality of groups of alternative bit sequences, where each group of alternative bit sequences includes a plurality of alternative bit sequences.
Next, each group of alternative bit sequences in the plurality of groups of alternative bit sequences is checked respectively to obtain a plurality of decoded bit sequences.
And then, if at least one alternative bit sequence in each group of alternative bit sequences passes the verification, judging that the received group of sequences to be decoded comes from the target encoder, and inversely arranging each decoded bit sequence in the plurality of decoded bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
Fig. 7 is a schematic structural diagram of a decoder according to an embodiment of the disclosure. As shown in fig. 7, the decoder includes a first decoding processing module 71 and a second decoding processing module 72.
The first decoding processing module 71 is configured to receive a set of sequences to be decoded, where the sequences to be decoded include a plurality of log-likelihood ratio sequences to be decoded.
The second decoding processing module 72 is configured to perform a decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, where the plurality of frozen bit distribution models are arranged in a predetermined order, the plurality of frozen bit distribution models are not identical, and the plurality of frozen bit distribution models and the arrangement order in the decoder are identical to the plurality of frozen bit distribution models and the arrangement order in the corresponding target encoder.
In some embodiments, the second decoding processing module 72 performs a polar code decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models.
For example, the second decoding processing module 72 performs polarization code decoding on each log-likelihood ratio sequence to be decoded in the multiple log-likelihood ratio sequences to be decoded respectively according to the sequence to generate multiple sets of alternative bit sequences, where each set of alternative bit sequence includes multiple alternative bit sequences, checks each set of alternative bit sequence in the multiple sets of alternative bit sequences respectively to obtain multiple decoded bit sequences, and if at least one alternative bit sequence in each set of alternative bit sequences passes the check, determines that one set of sequence to be decoded is from the target encoder, and performs inverse arrangement on each decoded bit sequence in the multiple decoded bit sequences by using a corresponding frozen bit distribution model to obtain multiple decoding results.
It should be noted that the reverse arrangement performed by the decoder and the arrangement performed by the target encoder are reciprocal operations.
For example, polar code decoding includes CA-SCL decoding or PC (parity) -CA-SCL decoding.
In some embodiments, the second decoding processing module 72 is configured to determine whether M sets of sequences to be decoded are from the target encoder or not according to the check result of the multiple sets of alternative bit sequences corresponding to each set of sequences to be decoded in the M sets of sequences to be decoded that are continuously received, if at least one set of alternative bit sequences in the multiple sets of alternative bit sequences does not pass the check, where M is a positive integer.
If at least one alternative bit sequence in each group of alternative bit sequences passes the verification in a plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in M groups of sequences to be decoded which are continuously received, judging that the M groups of sequences to be decoded come from a target encoder, and performing reverse arrangement on each decoding bit sequence in a plurality of decoding bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
And if at least one group of alternative bit sequences in a plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded which are continuously received does not pass the check, judging that the M groups of sequences to be decoded are from the non-target encoder.
In some embodiments, the magnitude of the parameter M is positively correlated with the block error rate. The larger the block error rate is, the larger the number of groups of the continuously received sequences to be decoded is, and the smaller the block error rate is, the smaller the number of groups of the continuously received sequences to be decoded is.
Fig. 8 is a schematic structural diagram of a decoder according to another embodiment of the disclosure. As shown in fig. 8, the decoder includes a memory 41, a processor 42, a communication interface 43, and a bus 44. Fig. 8 differs from fig. 4 in that, in the embodiment shown in fig. 8, the processor 82 is configured to perform the method according to any of the embodiments in fig. 5 based on instructions stored in the memory 81.
The present disclosure also relates to a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the instructions, when executed by a processor, implement a method according to any one of the embodiments in fig. 5.
Fig. 9 is a schematic structural diagram of a communication system according to an embodiment of the present disclosure. As shown in fig. 9, the communication system includes an encoder 91 and a decoder 92. The encoder is the encoder according to any of the embodiments in fig. 3 or fig. 4, and the decoder 92 is the decoder according to any of the embodiments in fig. 7 or fig. 8.
It should be noted that, if the encoder and the decoder only allocate one frozen bit distribution model, the number of frozen bit distribution models that can be used is as shown in equation (1).
Assuming that the parameter P =4, the number of usable frozen bit distribution models obtained by equation (1) is 69.
If the encoder and decoder are configured with a set of frozen bit distribution models, respectively, the number of frozen bit distribution models that can be used is shown in equation (2).
Wherein m is the number of frozen bit distribution models in the set of frozen bit distribution models. If the set of frozen bit distribution models includes at most 2 frozen bit distribution models, if P =4, the number of usable frozen bit distribution models obtained by equation (2) is 4761.
Therefore, compared with a scheme that only one frozen bit distribution model is configured for the encoder and the decoder, the scheme that a plurality of frozen bit distribution models are arranged in a preset sequence is configured for the encoder and the decoder, so that the user size can be enlarged by dozens of times, and the method is suitable for multi-user encoding and decoding transmission in scenes of high code rate of short codes and medium codes and low code rate of medium codes.
In some embodiments, the functional units described above can be implemented as general purpose processors, programmable Logic Controllers (PLCs), digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), or other Programmable Logic devices, discrete Gate or transistor Logic, discrete hardware components, or any suitable combination thereof, for performing the functions described in this disclosure.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The description of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to practitioners skilled in this art. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (26)
1. An encoding method, performed by an encoder, comprising:
acquiring a plurality of bit sequences to be transmitted;
and carrying out coding operation on each bit sequence to be transmitted in the plurality of bit sequences to be transmitted by utilizing a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models to obtain a plurality of coded bit sequences, wherein the plurality of frozen bit distribution models are arranged according to a preset sequence, and the plurality of frozen bit distribution models are not identical.
2. The method of claim 1, wherein the encoding operation comprises:
arranging each bit sequence to be transmitted by utilizing a corresponding frozen bit distribution model to generate a plurality of bit sequences to be coded;
and respectively encoding each bit sequence to be encoded in the plurality of bit sequences to be encoded to generate a plurality of encoded bit sequences.
3. The method of claim 2, wherein separately encoding each of the plurality of bit sequences to be encoded comprises:
and respectively carrying out polarization code coding on each bit sequence to be coded in the plurality of bit sequences to be coded.
4. The method of claim 2, wherein arranging each of the bit sequences to be transmitted with a corresponding frozen bit distribution model to generate a plurality of bit sequences to be encoded comprises:
respectively carrying out check code generation operation on each bit sequence to be transmitted in the plurality of bit sequences to be coded to obtain a plurality of check codes;
and arranging each check code in the plurality of check codes and the corresponding bit sequence to be transmitted by utilizing the corresponding frozen bit distribution model respectively to generate a plurality of bit sequences to be coded.
5. The method of any of claims 1-4, further comprising:
the plurality of coded bit sequences are sent to a decoder.
6. An encoder, comprising:
a first encoding processing module configured to obtain a plurality of bit sequences to be transmitted;
the second encoding processing module is configured to perform encoding operation on each bit sequence to be transmitted in the plurality of bit sequences to be transmitted by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models to obtain a plurality of encoded bit sequences, wherein the plurality of frozen bit distribution models are arranged in a preset order, and the plurality of frozen bit distribution models are not identical.
7. The encoder of claim 6,
the second encoding processing module is configured to arrange each bit sequence to be transmitted by using the corresponding frozen bit distribution model to generate a plurality of bit sequences to be encoded, and encode each bit sequence to be encoded in the plurality of bit sequences to be encoded respectively to generate a plurality of encoded bit sequences.
8. The encoder of claim 7,
the second encoding processing module is configured to perform polarization code encoding on each bit sequence to be encoded in the plurality of bit sequences to be encoded respectively.
9. The encoder according to claim 7, wherein,
the second encoding processing module is configured to perform check code generation operation on each bit sequence to be transmitted in the plurality of bit sequences to be encoded respectively to obtain a plurality of check codes, and arrange each check code in the plurality of check codes and the corresponding bit sequence to be transmitted respectively by using the corresponding frozen bit distribution model to generate the plurality of bit sequences to be encoded.
10. The encoder according to any one of claims 6-9,
the second encoding processing module is configured to send the plurality of encoded bit sequences to a decoder.
11. An encoder, comprising:
a memory configured to store instructions;
a processor coupled to the memory, the processor configured to perform an implementation of the method recited in any of claims 1-5 based on instructions stored by the memory.
12. A decoding method, performed by a decoder, comprising:
receiving a group of sequences to be decoded, wherein the sequences to be decoded comprise a plurality of log-likelihood ratio sequences to be decoded;
and performing decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a preset sequence, the plurality of frozen bit distribution models are not completely the same, and the plurality of frozen bit distribution models and the arrangement sequence in the decoder are the same as the plurality of frozen bit distribution models and the arrangement sequence in the corresponding target encoder.
13. The method of claim 12, wherein the coding operation comprises:
and carrying out polar code decoding operation on each log likelihood ratio sequence to be decoded in the plurality of log likelihood ratio sequences to be decoded by utilizing a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models.
14. The method of claim 13, wherein the polar code coding operation comprises:
respectively carrying out polarization code decoding on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded according to the sequence to generate a plurality of groups of alternative bit sequences, wherein each group of alternative bit sequences comprises a plurality of alternative bit sequences;
checking each group of alternative bit sequences in the multiple groups of alternative bit sequences respectively to obtain multiple decoding bit sequences;
and if at least one alternative bit sequence in each group of alternative bit sequences passes the verification, judging that the group of sequences to be decoded comes from a target encoder, and inversely arranging each decoded bit sequence in the plurality of decoded bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
15. The method of claim 14, further comprising:
if at least one group of alternative bit sequences in the plurality of groups of alternative bit sequences does not pass the verification, determining whether the M groups of sequences to be decoded are from a target encoder or not according to the verification result of the plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded which are continuously received, wherein M is a positive integer;
if at least one alternative bit sequence in each group of alternative bit sequences passes the verification in a plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in M groups of sequences to be decoded which are continuously received, judging that the M groups of sequences to be decoded come from a target encoder, and inversely arranging each decoding bit sequence in the plurality of decoding bit sequences by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
16. The method of claim 15, further comprising:
and if at least one group of alternative bit sequences in a plurality of groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded which are continuously received does not pass the check, judging that the M groups of sequences to be decoded are from the non-target encoder.
17. The method of claim 15, wherein,
the magnitude of the parameter M has a positive correlation with the block error rate.
18. A decoder, comprising:
the decoding device comprises a first decoding processing module, a second decoding processing module and a decoding processing module, wherein the first decoding processing module is configured to receive a group of sequences to be decoded, and the sequences to be decoded comprise a plurality of log-likelihood ratio sequences to be decoded;
and the second decoding processing module is configured to perform decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a preset sequence, the plurality of frozen bit distribution models are not completely the same, and the plurality of frozen bit distribution models and the arrangement sequence in the decoder are the same as the plurality of frozen bit distribution models and the arrangement sequence in the corresponding target encoder.
19. The decoder according to claim 18,
the second decoding processing module is configured to perform a polar code decoding operation on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models.
20. The decoder of claim 19, wherein,
the second decoding processing module is configured to perform polarization code decoding on each log-likelihood ratio sequence to be decoded in the plurality of log-likelihood ratio sequences to be decoded respectively according to a sequence to generate a plurality of groups of alternative bit sequences, wherein each group of alternative bit sequences includes a plurality of alternative bit sequences, each group of alternative bit sequences in the plurality of groups of alternative bit sequences is checked respectively to obtain a plurality of decoded bit sequences, if at least one alternative bit sequence in each group of alternative bit sequences passes the check, it is determined that the group of sequences to be decoded is from the target encoder, and each decoded bit sequence in the plurality of decoded bit sequences is inversely arranged by using a corresponding frozen bit distribution model to obtain a plurality of decoding results.
21. The decoder of claim 20, wherein,
the second decoding processing module is configured to determine whether the M groups of sequences to be decoded are from the target encoder or not according to a check result of the multiple groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded that are continuously received if at least one alternative bit sequence in each group of sequences to be decoded in the M groups of sequences to be decoded that are continuously received passes the check, where if at least one alternative bit sequence in each group of sequences to be decoded in the multiple groups of sequences to be decoded that are continuously received passes the check, it is determined that the M groups of sequences to be decoded are from the target encoder, and each decoding bit sequence in the multiple decoding bit sequences is inversely arranged by using a corresponding frozen bit distribution model to obtain multiple decoding results.
22. The decoder of claim 21, wherein,
the second decoding processing module is configured to determine that the M groups of sequences to be decoded are from the non-target encoder if at least one group of alternative bit sequences in the multiple groups of alternative bit sequences corresponding to each group of sequences to be decoded in the M groups of sequences to be decoded that are continuously received does not pass the check.
23. The decoder according to claim 21, wherein,
the magnitude of the parameter M is positively correlated with the block error rate.
24. A decoder, comprising:
a memory configured to store instructions;
a processor coupled to the memory, the processor configured to perform an implementation of the method recited in any one of claims 12-17 based on instructions stored by the memory.
25. A communication system, comprising:
an encoder according to any one of claims 6-11;
the decoder of any of claims 18-24.
26. A non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions which, when executed by a processor, implement the method of any one of claims 1-5, 12-17.
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| CN115833847B (en) * | 2023-02-15 | 2023-06-13 | 南京创芯慧联技术有限公司 | Polar code decoding method, polar code decoding device, communication equipment and storage medium |
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