CN116344616A - High-voltage MOS device and testing method thereof - Google Patents
High-voltage MOS device and testing method thereof Download PDFInfo
- Publication number
- CN116344616A CN116344616A CN202310115524.4A CN202310115524A CN116344616A CN 116344616 A CN116344616 A CN 116344616A CN 202310115524 A CN202310115524 A CN 202310115524A CN 116344616 A CN116344616 A CN 116344616A
- Authority
- CN
- China
- Prior art keywords
- metal
- epitaxial layer
- section
- layer
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 100
- 239000002184 metal Substances 0.000 claims abstract description 100
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000012212 insulator Substances 0.000 claims description 28
- 230000015556 catabolic process Effects 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000012544 monitoring process Methods 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 4
- 238000010998 test method Methods 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract description 24
- 230000005855 radiation Effects 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 description 7
- 239000008186 active pharmaceutical agent Substances 0.000 description 5
- 239000002131 composite material Substances 0.000 description 5
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
- G01R31/2623—Circuits therefor for testing field effect transistors, i.e. FET's for measuring break-down voltage therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a high-voltage MOS device, which relates to the technical field of semiconductors and comprises a substrate layer, wherein a first epitaxial layer is overlapped at the top of the substrate layer, a second epitaxial layer is overlapped at the top of the first epitaxial layer, grid metal is arranged on the second epitaxial layer, a contact metal layer is wrapped outside the grid metal, the contact metal layer comprises a contact section which contacts the second epitaxial layer, source metal is arranged at the top of the contact section, and drain metal is arranged at the bottom of the substrate layer; a first insulating silicon section positioned on the left side and a second insulating silicon section positioned on the right side are arranged between the first epitaxial layer and the substrate layer, and a gap section is formed between the first insulating silicon section and the second insulating silicon section; a third insulating silicon section is arranged between the second epitaxial layer and the first epitaxial layer, and the third insulating silicon section faces the gap section; a method for testing the high-voltage MOS device is also disclosed. The invention has the advantages of safety, stability, strong reliability and strong single particle radiation resistance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-voltage MOS device and a testing method thereof.
Background
MOS devices (metal-oxide-semiconductor field effect transistors) are main devices in modern integrated circuits, and at present, during the continuous operation of the MOS devices under signals such as radio frequency, the electronic system caused by the radiation of a semiconductor material by a single energy particle or the sensitive area of the semiconductor device is disturbed or even broken, or the internal local potential difference is caused to be different, and the local potential difference can cause the internal parasitic devices of the semiconductor device to be triggered, so that abnormal paths or large currents occur to the semiconductor device, and finally the state of the semiconductor device is changed.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a high-voltage MOS device and a testing method thereof.
The high-voltage MOS device comprises a substrate layer, wherein a first epitaxial layer is stacked on the top of the substrate layer, a second epitaxial layer is stacked on the top of the first epitaxial layer, gate metal is arranged on the second epitaxial layer, a contact metal layer is wrapped outside the gate metal, the contact metal layer comprises a contact section which contacts the second epitaxial layer, source metal is arranged on the top of the contact section, and drain metal is arranged on the bottom of the substrate layer; a first silicon-on-insulator section positioned on the left side and a second silicon-on-insulator section positioned on the right side are arranged between the first epitaxial layer and the substrate layer, and a gap section is formed between the first silicon-on-insulator section and the second silicon-on-insulator section; and a third insulating silicon section is arranged between the second epitaxial layer and the first epitaxial layer, and the third insulating silicon section is opposite to the gap section. In the whole high-voltage MOS device, through the arrangement of the first epitaxial layer and the second epitaxial layer, the installation positions of the first insulating silicon section, the second insulating silicon section and the third insulating silicon section are formed on one hand, the breakdown voltage can be improved on the other hand, the current collapse effect of the device is effectively reduced, and the reliability of the device is improved; furthermore, a first insulating silicon section and a second insulating silicon section are arranged between the first epitaxial layer and the substrate layer separately, and a third insulating silicon section is arranged between the first epitaxial layer and the second epitaxial layer, so that two layers of staggered insulating silicon sections are formed, when heavy particles are injected into the whole high-voltage MOS device from the surface, all injection directions of the heavy particles can pass through the two layers of staggered insulating silicon sections, and obvious composite action exists on new electrons and new holes generated by heavy particle radiation through an interface formed by the first epitaxial layer, the insulating silicon section and the second epitaxial layer, so that the single particle radiation resistance of the device is greatly improved.
Preferably, the first silicon-on-insulator segment and the second silicon-on-insulator segment are made of silicon dioxide. And between the first epitaxial layer and the substrate layer, the silicon-silicon dioxide section has a composite effect on nascent electrons and nascent holes near the section, so that the quantity of the nascent electrons and the nascent holes in the heavy particle radiation track ionization region is reduced, and the single particle radiation resistance of the whole device is improved.
Preferably, the third silicon-on-insulator segment is made of silicon dioxide. Similarly, between the second epitaxial layer and the first epitaxial layer, the silicon-silicon dioxide section has a composite effect on nascent electrons and nascent holes near the section, so that the quantity of the nascent electrons and the nascent holes in the heavy particle radiation track ionization region is reduced, and the single particle radiation resistance of the whole device is improved.
Preferably, the source metal is externally provided with a passivation layer. The passivation layer is capable of blocking incident particles to some extent.
Preferably, a gate oxide layer is disposed between the gate metal and the second epitaxial layer.
Preferably, a source metal is stacked on the contact metal layer.
The method comprises a device breakdown voltage testing step, a current collapse testing step and a gate pulse testing step. The device breakdown voltage testing step is used for measuring breakdown voltage, which is an important index for measuring the performance of the device and determines the application environment of the device in a circuit. The off-state breakdown voltage of the power amplifier defines the voltage swing of the logic circuit and the output power density of the amplifier; the current collapse test step is used for testing the condition that the output leakage current is obviously compressed; the gate pulse test step is used to test the gate pulse characteristics, which reflect the switching characteristics of the device.
Preferably, the device breakdown voltage testing step includes: s11, current is introduced into drain metal of the device; s12, measuring the breakdown voltage of source metal and drain metal; s13, measuring the metal of the grid electrode and the metal of the drain electrodeBreakdown voltage. The drain metal is injected with a current preferably of a predetermined value, and then the gate metal voltage is gradually increased from zero, and the gate current is monitored during this scan (I G ) Drain source metal voltage (V DS ) And drain gate metal voltage (V) DG ) Is a variation of (c). When V is GS When the voltage is larger than the threshold voltage, the voltage is in a conducting state, and only a small V is needed DS Can make I D Equal to a preset value, so V at this time DS Near zero, I G Close to zero. When V is GS When the voltage is smaller than the threshold voltage, the leakage I is maintained D V must be increased when the value is equal to the preset value DS And V is DG ＝V DS -V GS And also increases, when I G Equal to-I D When the value is equal to the negative preset value, breakdown occurs between the gate metal and the drain metal.
Preferably, the current collapse test step comprises: s21, simultaneously applying two pulse signals at the gate metal and the drain metal of the device; s22, grounding the source metal; s23, monitoring effective electric signals on the drain metal and the gate metal. In the test process, the voltage signals on the gate electrode and the drain electrode are synchronous and alternate in the form of a first preset voltage, a second preset voltage and a first preset voltage.
Preferably, the gate pulse testing step includes: s31, electrically connecting drain metal and applying constant voltage with preset value; s32, electrically connecting the grid metal and applying a voltage pulse from an off state to an on state; s33, monitoring the change relation of the drain metal current and the gate metal voltage along with time. The response of the device drain metal current is typically delayed from the rise of the voltage on the gate metal by the presence of a large number of traps at the surface between the gate drain metals, and it is apparent that the smaller the time delay, the better the switching characteristics of the device.
The beneficial effects of the invention are as follows:
according to the invention, through the arrangement of the first epitaxial layer and the second epitaxial layer, the installation positions of the first insulating silicon section, the second insulating silicon section and the third insulating silicon section are formed on one hand, and the breakdown voltage can be improved on the other hand, so that the current collapse effect of the device is effectively reduced, and the reliability of the device is improved; furthermore, a first insulating silicon section and a second insulating silicon section are arranged between the first epitaxial layer and the substrate layer separately, and a third insulating silicon section is arranged between the first epitaxial layer and the second epitaxial layer, so that two layers of staggered insulating silicon sections are formed, when heavy particles are injected into the whole high-voltage MOS device from the surface, all injection directions of the heavy particles can pass through the two layers of staggered insulating silicon sections, and obvious composite action exists on new electrons and new holes generated by heavy particle radiation through an interface formed by the first epitaxial layer, the insulating silicon section and the second epitaxial layer, so that the single particle radiation resistance of the device is greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
Fig. 1 is a schematic structural diagram of a high-voltage MOS device of the present invention;
fig. 2 is a circuit schematic diagram of a device breakdown voltage testing step in the testing method of the high-voltage MOS device of the present invention;
fig. 3 is a circuit schematic diagram of a gate pulse test step in the test method of the high voltage MOS device of the present invention.
Reference numerals:
1-substrate layer, 2-first epitaxial layer, 3-second epitaxial layer, 4-gate metal, 5-contact metal layer, 51-contact segment, 6-source metal, 7-drain metal, 8-first silicon insulator segment, 9-second silicon insulator segment, 10-third silicon insulator segment, 11-gap segment, 12-passivation layer, 13-gate oxide layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In describing embodiments of the present invention, it should be noted that the directions or positional relationships indicated by the terms "inner", "outer", "upper", etc. are directions or positional relationships based on those shown in the drawings, or those that are conventionally put in place when the inventive product is used, are merely for convenience of description and simplification of description, and are not indicative or implying that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
As shown in fig. 1, a high-voltage MOS device includes a substrate layer 1, a first epitaxial layer 2 is stacked on top of the substrate layer 1, a second epitaxial layer 3 is stacked on top of the first epitaxial layer 2, a gate metal 4 is disposed on the second epitaxial layer 3, a contact metal layer 5 is wrapped outside the gate metal 4, the contact metal layer 5 includes a contact section 51 contacting the second epitaxial layer 3, a source metal 6 is disposed on top of the contact section 51, and a drain metal 7 is disposed on bottom of the substrate layer 1; a first silicon-on-insulator section 8 positioned on the left side and a second silicon-on-insulator section 9 positioned on the right side are arranged between the first epitaxial layer 2 and the substrate layer 1, and a gap section 11 is formed between the first silicon-on-insulator section 8 and the second silicon-on-insulator section 9; a third silicon-on-insulator segment 10 is arranged between the second epitaxial layer 3 and the first epitaxial layer 2, and the third silicon-on-insulator segment 10 faces the gap segment 11.
In this embodiment, the arrangement of the first epitaxial layer 2 and the second epitaxial layer 3 in the entire high-voltage MOS device forms the mounting positions of the first silicon-on-insulator segment 8, the second silicon-on-insulator segment 9 and the third silicon-on-insulator segment 10, and can improve the breakdown voltage, effectively reduce the current collapse effect of the device and improve the reliability of the device; further, by separately arranging the first insulating silicon section 8 and the second insulating silicon section 9 between the first epitaxial layer 2 and the substrate layer 1 and arranging the third insulating silicon section 10 between the first epitaxial layer 2 and the second epitaxial layer 3, two layers of staggered insulating silicon sections are formed, and when heavy particles are injected into the whole high-voltage MOS device from the surface, all injection directions of the heavy particles pass through the two layers of staggered insulating silicon sections, and obvious composite action exists on new electrons and new holes generated by heavy particle radiation through an interface formed by the first epitaxial layer 2-insulating silicon section-the second epitaxial layer 3, so that the single particle radiation resistance of the device is greatly improved.
Specifically, the first silicon insulator segment 8 and the second silicon insulator segment 9 are made of silicon dioxide.
In this embodiment, between the first epitaxial layer 2 and the substrate layer 1, the silicon-silicon dioxide cross section has a recombination effect on the new electrons and new holes near the cross section, which causes a reduction in the number of new electrons and new holes in the heavy particle radiation track ionization region, thereby achieving an improvement in the single particle radiation resistance of the entire device.
Specifically, the third silicon-on-insulator segment 10 is made of silicon dioxide.
In this embodiment, similarly, between the second epitaxial layer 3 and the first epitaxial layer 2, the silicon-silicon dioxide cross section has a recombination effect on the new electrons and new holes near the cross section, and the number of new electrons and new holes in the heavy particle radiation track ionization region is reduced, thereby improving the single particle radiation resistance of the whole device.
Specifically, the source metal 6 is externally provided with a passivation layer 12.
In the present embodiment, the passivation layer 12 can block incident particles to some extent.
Specifically, a gate oxide layer 13 is provided between the gate metal 4 and the second epitaxial layer 3.
Specifically, the source metal 6 is stacked on the contact metal layer 5.
The method comprises a device breakdown voltage testing step, a current collapse testing step and a gate pulse testing step.
In this embodiment, it should be noted that, the breakdown voltage testing step is used to measure the breakdown voltage, where the breakdown voltage is an important indicator for measuring the performance of the device, and determines the application environment of the device in the circuit. The off-state breakdown voltage of the power amplifier defines the voltage swing of the logic circuit and the output power density of the amplifier; the current collapse test step is used for testing the condition that the output leakage current is obviously compressed; the gate pulse test step is used to test the gate pulse characteristics, which reflect the switching characteristics of the device.
Specifically, the device breakdown voltage testing step includes: s11, current is introduced into drain metal 7 of the device; s12, measuring breakdown voltages of the source metal 6 and the drain metal 7; and S13, measuring breakdown voltages of the gate metal 4 and the drain metal 7.
In this embodiment, as shown in fig. 2, the drain metal 7 is injected with a current of a predetermined value, and then the voltage of the gate metal 4 is gradually increased from zero, and the change of the gate current (), the drain-source metal 6 voltage () and the drain-gate metal 4 voltage () is monitored during the scanning. When the voltage is larger than the threshold voltage, the voltage is in a conducting state, and the voltage is equal to a preset value only by small voltage, so that the voltage is close to zero at the moment and is close to zero. When the threshold voltage is smaller than the threshold voltage, the leakage current must be increased to maintain the value equal to the preset value, and = -is increased accordingly, and when the value is equal to-equal to the negative preset value, the breakdown occurs between the gate metal 4 and the drain metal 7.
Specifically, the current collapse test step includes: s21, simultaneously applying two pulse signals at a gate metal 4 and a drain metal 7 of the device; s22, grounding the source metal 6; s23, monitoring the effective electrical signals on the drain metal 7 and the gate metal 4.
In this embodiment, during the test, the voltage signals on the gate electrode and the drain electrode are alternately changed in the form of the first preset voltage, the second preset voltage, and the first preset voltage in synchronization.
Specifically, the gate pulse testing step includes: s31, electrically connecting the drain metal 7 and applying a constant voltage with a preset value; s32, electrically connecting the grid metal 4 and applying a voltage pulse from an off state to an on state; and S33, monitoring the change relation between the current of the drain metal 7 and the voltage of the gate metal 4 along with time.
In this embodiment, as shown in fig. 3, the presence of a large number of traps at the surface between the gate and drain metals 7 generally causes the response of the current of the drain metal 7 of the device to be delayed from the rise of the voltage on the gate metal 4, and obviously, the smaller the time delay, the better the switching characteristics of the device.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
Claims (10)
1. The high-voltage MOS device is characterized by comprising a substrate layer, wherein a first epitaxial layer is stacked on the top of the substrate layer, a second epitaxial layer is stacked on the top of the first epitaxial layer, gate metal is arranged on the second epitaxial layer, a contact metal layer is wrapped outside the gate metal, the contact metal layer comprises a contact section which contacts the second epitaxial layer, source metal is arranged on the top of the contact section, and drain metal is arranged on the bottom of the substrate layer; wherein,,
a first silicon-on-insulator section positioned on the left side and a second silicon-on-insulator section positioned on the right side are arranged between the first epitaxial layer and the substrate layer, and a gap section is formed between the first silicon-on-insulator section and the second silicon-on-insulator section;
and a third insulating silicon section is arranged between the second epitaxial layer and the first epitaxial layer, and the third insulating silicon section is opposite to the gap section.
2. The high voltage MOS device of claim 1, wherein the first and second silicon-on-insulator segments are made of silicon dioxide.
3. The high voltage MOS device of claim 1, wherein the third silicon-on-insulator segment is made of silicon dioxide.
4. The high voltage MOS device of claim 1, wherein the source metal is externally provided with a passivation layer.
5. The high voltage MOS device of claim 1, wherein a gate oxide layer is disposed between the gate metal and the second epitaxial layer.
6. The high voltage MOS device of claim 1, wherein the source metal is stacked on the contact metal layer.
7. A method of testing a high voltage MOS device according to any of claims 1 to 6, comprising a device breakdown voltage testing step, a current collapse testing step, and a gate pulse testing step.
8. The method for testing a high voltage MOS device of claim 7, wherein the device breakdown voltage testing step comprises: s11, current is introduced into drain metal of the device; s12, measuring the breakdown voltage of source metal and drain metal; and S13, measuring the breakdown voltage of the gate metal and the drain metal.
9. The method for testing a high-voltage MOS device of claim 7, wherein the current collapse testing step comprises: s21, simultaneously applying two pulse signals at the gate metal and the drain metal of the device; s22, grounding the source metal; s23, monitoring effective electric signals on the drain metal and the gate metal.
10. The method for testing a high voltage MOS device of claim 7, wherein the gate pulse testing step comprises: s31, electrically connecting drain metal and applying constant voltage with preset value; s32, electrically connecting the grid metal and applying a voltage pulse from an off state to an on state; s33, monitoring the change relation of the drain metal current and the gate metal voltage along with time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310115524.4A CN116344616A (en) | 2023-02-15 | 2023-02-15 | High-voltage MOS device and testing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310115524.4A CN116344616A (en) | 2023-02-15 | 2023-02-15 | High-voltage MOS device and testing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116344616A true CN116344616A (en) | 2023-06-27 |
Family
ID=86881330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310115524.4A Pending CN116344616A (en) | 2023-02-15 | 2023-02-15 | High-voltage MOS device and testing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116344616A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699340A (en) * | 2023-08-07 | 2023-09-05 | 成都高投芯未半导体有限公司 | Semiconductor device testing equipment and method |
-
2023
- 2023-02-15 CN CN202310115524.4A patent/CN116344616A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116699340A (en) * | 2023-08-07 | 2023-09-05 | 成都高投芯未半导体有限公司 | Semiconductor device testing equipment and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Liu et al. | Time-dependent dielectric breakdown of commercial 1.2 kV 4H-SiC power MOSFETs | |
| US7701241B2 (en) | Circuit for protecting DUT, method for protecting DUT, testing apparatus and testing method | |
| US9476933B2 (en) | Apparatus and methods for qualifying HEMT FET devices | |
| KR101322745B1 (en) | Jig for semiconductor test | |
| Tousi et al. | Nonlinear resistive electric field grading in high-voltage, high-power wide bandgap power module packaging | |
| CN116344616A (en) | High-voltage MOS device and testing method thereof | |
| US9401314B2 (en) | Method of testing semiconductor device | |
| CN112582290B (en) | Semiconductor test device, method for testing semiconductor device, and method for manufacturing semiconductor device | |
| CN112242444A (en) | High electron mobility transistor and manufacturing method thereof | |
| Yao et al. | Investigations of UIS failure mechanism in 1.2 kV trench SiC MOSFETs using electro-thermal-mechanical stress analysis | |
| Kang et al. | An online gate oxide degradation monitoring method for SiC MOSFETs with contactless PCB rogowski coil approach | |
| Borghese et al. | Short-circuit and Avalanche Robustness of SiC Power MOSFETs for Aerospace Power Converters | |
| Stoffels et al. | Stability evaluation of insulated gate AlGaN/GaN power switching devices under heavy-ion irradiation | |
| Lu et al. | Short Circuit Capability and Performance Degradation of Cascode GaN Devices-A Case Study | |
| CN110824322A (en) | Apparatus and method for measuring high electron mobility transistors | |
| Deltour et al. | Partial Discharges and AC Breakdown Voltage Tests on Thick Metallized Aluminum Nitride Substrates for High Voltage Power Modules | |
| You et al. | Partial discharge behaviors in power module under very high dv/dt repetitive square voltages | |
| Zeng et al. | 710 V breakdown voltage in field plated Ga203 MOSFET | |
| JP7508948B2 (en) | Testing apparatus, testing method and manufacturing method | |
| CN108037131B (en) | Method for detecting plug defect | |
| US10886392B2 (en) | Semiconductor structure for improving thermal stability and Schottky behavior | |
| Liu et al. | Impacts of Area-Dependent Defects on the Yield and Gate Oxide Reliability of SiC Power MOSFETs | |
| US20220334167A1 (en) | Method for detecting defects in gallium nitride high electron mobility transistor | |
| Van Vonno et al. | Destructive single-event effects testing of the Intersil ISL70023SEH and ISL70024SEH Gallium Nitride power transistors | |
| CN112230119B (en) | Power device conduction voltage non-stop measuring circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |