CN116344613A - Semiconductor device having isolation structure and method of manufacturing the same - Google Patents

Semiconductor device having isolation structure and method of manufacturing the same Download PDF

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Publication number
CN116344613A
CN116344613A CN202111599705.6A CN202111599705A CN116344613A CN 116344613 A CN116344613 A CN 116344613A CN 202111599705 A CN202111599705 A CN 202111599705A CN 116344613 A CN116344613 A CN 116344613A
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region
doped region
conductivity type
doped
buried layer
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李永顺
金华俊
宋亮
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to CN202111599705.6A priority Critical patent/CN116344613A/en
Priority to PCT/CN2022/134890 priority patent/WO2023116357A1/en
Publication of CN116344613A publication Critical patent/CN116344613A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/7818—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H01L29/7819—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode

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Abstract

The invention relates to a semiconductor device with an isolation structure and a manufacturing method thereof, wherein the device comprises: a substrate; a buried layer of a first conductivity type disposed in the substrate; the drift region is arranged on the buried layer; the drain electrode region is arranged in the drift region; the body region is arranged on the buried layer; the source region is arranged in the body region; first to fourth doped regions on the buried layer and sequentially arranged in a direction in which the drift region is away from the body region; when the semiconductor device works, the voltage of the potential connected with the third doped region and the fourth doped region is higher than that of the potential connected with the first doped region and the second doped region. When the body diode of the device freewheels, the triode formed by the second doping region, the third doping region and the fourth doping region works in the amplifying region, so that current flowing into the buried layer of the first conductivity type can be absorbed, and the current is prevented from flowing into the substrate, thereby obviously shielding the substrate leakage caused by the freewheels of the body diode.

Description

Semiconductor device having isolation structure and method of manufacturing the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device having an isolation structure, and a method for manufacturing the device isolation structure.
Background
In the exemplary LDMOS, isolation may be performed by a well region isolation structure with a PN junction reverse biased, for example, by a DN-BN-DN (deep N-well-N-buried layer-deep N-well) ring. However, when the LDMOS is applied to the dead time condition, because the Body diode of the LDMOS freewheels, a negative voltage drop is generated at a PN junction formed by an N-type Drift region (N-Drift) and a P-Body region (P-Body) of the Body diode, and an electron current largely flows into the P-Body, and an NPN triode formed by the N-type Drift region/P-Body region/N-type buried layer is turned on and works in an amplifying region, and a part of the electron current flows into BN under the effect of a reverse bias electric field formed by BN and P-Body. Due to the existence of the DN-BN-DN ring high-resistance region, the potential on the BN ring is rapidly reduced and even lower than the potential of a P-type substrate (Psub), PN junctions formed by the Psub and the BN are positively biased, hole carriers in the Psub are injected into the BN, electrons in the BN are injected into the Psub, and accordingly larger Psub electric leakage is formed.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor device having an isolation structure capable of improving substrate leakage caused by body diode freewheel.
A semiconductor device having an isolation structure, comprising: a substrate having a second conductivity type; a buried layer of a first conductivity type disposed in the substrate; a drift region having a first conductivity type and disposed on the buried layer of the first conductivity type; a drain region of a first conductivity type disposed within the drift region; the body region is provided with a second conductive type and is arranged on the buried layer of the first conductive type; a source region of a first conductivity type disposed within the body region; the first doped region is provided with a second conductivity type and is arranged on one side of the drift region opposite to the body region and on the buried layer of the first conductivity type; the second doped region is provided with a first conductive type and is arranged on one side of the first doped region opposite to the drift region and on the buried layer of the first conductive type; the third doped region is provided with a second conductivity type and is arranged on one side of the second doped region opposite to the first doped region and on the buried layer of the first conductivity type; a fourth doped region having the first conductivity type and arranged on the first conductivity type buried layer on the opposite side of the third doped region from the second doped region; the first conductive type and the second conductive type are opposite conductive types, and when the semiconductor device works, the voltage of the potential connected with the third doped region and the fourth doped region is higher than that of the potential connected with the first doped region and the second doped region.
In one embodiment, the doping concentration of the third doped region is less than the doping concentration of the first doped region.
In one embodiment, the doping concentration of the second doped region is greater than the doping concentration of the fourth doped region.
The doping concentration of the first conductive type buried layer is greater than the doping concentrations of the second doping region and the fourth doping region.
In one embodiment, a second conductivity type doped region is further arranged between the drift region and the body region and the first conductivity type buried layer.
In one embodiment, the semiconductor device further comprises a gate electrode arranged above the region between the drain region and the source region.
In one embodiment, the method further comprises: the first contact region is provided with a second conductivity type and is arranged on the surface of the first doped region, and the doping concentration of the first contact region is larger than that of the first doped region; the second contact region is provided with a first conductive type and is arranged on the surface of the second doped region, and the doping concentration of the second contact region is greater than that of the second doped region; the third contact region is provided with a second conductivity type and is arranged on the surface of the third doped region, and the doping concentration of the third contact region is greater than that of the third doped region; and the fourth contact region is provided with the first conductivity type and is arranged on the surface of the fourth doped region, and the doping concentration of the fourth contact region is larger than that of the fourth doped region.
In one embodiment, the semiconductor device is an LDMOS device.
In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the third doped region is a P-type ring.
In one embodiment, the third doped region and the fourth doped region are electrically connected to the anode lead, and the first doped region and the second doped region are electrically connected to the cathode lead.
In one embodiment, the doping concentration of the drain region is greater than the doping concentration of the drift region.
In one embodiment, the doping concentration of the source region is greater than the doping concentration of the body region.
In one embodiment, the semiconductor device further comprises a shallow trench isolation structure, wherein the shallow trench isolation structure is arranged between the top of the drift region and the top of the first doped region, between the top of the first doped region and the top of the second doped region, between the top of the second doped region and the top of the third doped region, and between the top of the third doped region and the top of the fourth doped region.
It is also necessary to provide a method of manufacturing a semiconductor device having an isolation structure.
A method of manufacturing a semiconductor device having an isolation structure, comprising: acquiring a wafer; the wafer comprises: a substrate, a first conductive type buried layer in the substrate, a drift region on the first conductive type buried layer, a body region on the first conductive type buried layer, a drain region in the drift region and a source region in the body region; the substrate and the body region have a second conductivity type, and the drift region, the drain region, and the source region have a first conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; forming a first doped region, a second doped region, a third doped region and a fourth doped region which are sequentially arranged in the direction of deviating from the body region of the drift region on the first conductive type buried layer, wherein the first doped region and the third doped region have a second conductive type, and the second doped region and the fourth doped region have a first conductive type; forming a first electrode lead electrically connected with the third doped region and the fourth doped region and a second electrode lead electrically connected with the first doped region and the second doped region; when the semiconductor device works, the voltage of the first electrode lead-out access is higher than that of the second electrode lead-out access.
In one embodiment, the step of obtaining the wafer includes: forming a first conductive type doped region on the first conductive type buried layer by ion implantation; implanting second conductivity type ions into the first conductivity type doped region to neutralize the doped ions in a partial region of the first conductivity type doped region to form a body region, wherein a region of the first conductivity type doped region which is not neutralized is used as a drift region; the source region, drain region, and gate over a region between the drain region and source region are formed.
In one embodiment, before the step of forming a first electrode lead electrically connected to the third doped region and the fourth doped region and a second electrode lead electrically connected to the first doped region and the second doped region, the method further includes a step of forming a first contact region, a second contact region, a third contact region, and a fourth contact region by ion implantation; the first contact region is provided with a second conductive type and is arranged on the surface of the first doped region, and the doping concentration of the first contact region is larger than that of the first doped region; the second contact region has a first conductivity type and is arranged on the surface of the second doped region, and the doping concentration of the second contact region is greater than that of the second doped region; the third contact region has a second conductivity type and is arranged on the surface of the third doped region, and the doping concentration of the third contact region is greater than that of the third doped region; the fourth contact region has a first conductivity type and is arranged on the surface of the fourth doped region, and the doping concentration of the fourth contact region is greater than that of the fourth doped region; the first electrode lead-out forms ohmic contact with the third contact region and the fourth contact region, and the second electrode lead-out forms ohmic contact with the first contact region and the second contact region.
In one embodiment, before the step of forming the first conductivity type doped region on the first conductivity type buried layer by ion implantation, the method further includes: forming a buried layer of a first conductivity type in the substrate by doping; epitaxially forming an epitaxial layer of a second conductivity type on the substrate and the buried layer of the first conductivity type; the first conductivity type doped region is formed in the epitaxial layer.
In one embodiment, the first electrode is an anode lead and the second electrode is a cathode lead.
In one embodiment, after forming the buried layer of the first conductivity type, the method further comprises a step of forming a shallow trench isolation structure; the shallow trench isolation structure is formed between the top of the drift region and the top of the first doped region, between the top of the first doped region and the top of the second doped region, between the top of the second doped region and the top of the third doped region, and between the top of the third doped region and the top of the fourth doped region.
According to the semiconductor device with the isolation structure and the manufacturing method thereof, the voltage of the potential connected with the third doped region and the fourth doped region is higher than the voltage of the potential connected with the first doped region and the second doped region during operation, so that when the body diode consisting of the body region and the drift region is in continuous current, the triode consisting of the second doped region, the third doped region and the fourth doped region is operated in the amplifying region, and current rushing into the buried layer of the first conductivity type can be absorbed, and the current rushing into the substrate is prevented from flowing into the substrate, so that substrate leakage caused by continuous current of the body diode is obviously shielded.
Drawings
For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.
FIG. 1 is a schematic diagram of a semiconductor device having an isolation structure in one embodiment;
FIG. 2 is a flow chart of a method of fabricating a semiconductor device having an isolation structure in one embodiment;
fig. 3 is a schematic view of a method for manufacturing a semiconductor device having an isolation structure in an embodiment to form a buried layer of a first conductivity type;
fig. 4 is a schematic diagram of drift region implantation performed by a method for manufacturing a semiconductor device having an isolation structure according to an embodiment;
fig. 5 is a schematic view of a method for manufacturing a semiconductor device with an isolation structure to form a body region in one embodiment;
fig. 6 is a schematic diagram illustrating a method for manufacturing a semiconductor device having an isolation structure according to an embodiment to form a first doped region and a third doped region;
fig. 7 is a schematic diagram illustrating a method for manufacturing a semiconductor device having an isolation structure according to an embodiment to form a second doped region and a fourth doped region;
fig. 8 is a schematic structural diagram of a semiconductor device having an isolation structure in another embodiment.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
Fig. 1 is a schematic structural diagram of a semiconductor device having an isolation structure in an embodiment. In this embodiment, the semiconductor device having the isolation structure includes a substrate 110, a buried layer 120 of the first conductivity type, a source region 130, a drain region 140, a body region 132, a drift region 142, a first doped region 162, a second doped region 164, a third doped region 166, and a fourth doped region 168. The substrate 110 has a second conductivity type. A buried layer 120 of a first conductivity type is provided on the substrate 110. The drift region 142 has a first conductivity type and is disposed on the first conductivity type buried layer 120. The drain region 140 has a first conductivity type and is disposed within the drift region 142. The body region 132 has a second conductivity type and is disposed on the buried layer 120 of the first conductivity type. The source region 130 has a first conductivity type and is disposed within the body region 132. The first doped region 162 has the second conductivity type, is disposed on a side of the drift region 142 opposite to the body region 132, and is disposed on the buried layer 120 of the first conductivity type. The second doped region 164 has the first conductivity type, is disposed on a side of the first doped region 162 opposite to the drift region 142, and is disposed on the buried layer 120 of the first conductivity type. The third doped region 166 has the second conductivity type, is disposed on the opposite side of the second doped region 164 from the first doped region 162, and is disposed on the buried layer 120 of the first conductivity type. The fourth doped region 168 has the first conductivity type, is disposed on a side of the third doped region 166 opposite to the second doped region 164, and is disposed on the buried layer 120 of the first conductivity type. The first conductive type buried layer 120 may entirely cover the bottom of the fourth doped region 168 as shown in fig. 1, or may partially cover, i.e., the right boundary of the first conductive type buried layer 120 is not flush with the right boundary of the fourth doped region 168 in fig. 1. The first conductive type buried layer 120, the first doped region 162, the second doped region 164, the third doped region 166, and the fourth doped region 168 serve as isolation structures. When the semiconductor device is operated, the voltage of the electric potential connected to the third doped region 166 and the fourth doped region 168 is higher than the voltage of the electric potential connected to the first doped region 162 and the second doped region 164, and the third doped region 166 and the fourth doped region 168 can be connected to a high electric potential, and the first doped region 162 and the second doped region 164 can be connected to a low electric potential. Thus, when the body diode composed of the body region 132 and the drift region 142 is freewheeled, the triode composed of the second doped region 164, the third doped region 166 and the fourth doped region 168 works in the amplifying region, and the current rushing into the buried layer 120 of the first conductivity type can be absorbed, so that the current is prevented from flowing into the substrate 110, and the substrate leakage caused by the freewheeled body diode is obviously shielded. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type, so the BJT formed by the second doped region 164-the third doped region 166-the fourth doped region 168 is an NPN transistor. In the embodiment shown in fig. 1, the third doped region 166 and the fourth doped region 168 are electrically connected to an Anode lead (Anode), and the first doped region 162 and the second doped region 164 are electrically connected to a Cathode lead (Cathode).
The drift region 142 and the body region 132 may be disposed at intervals or may be disposed adjacently (i.e., the drift region 142 and the body region 132 are in direct contact) as shown in fig. 1. The spaced apart arrangement of the drift region 142 and the body region 132 may increase the Breakdown Voltage (BV) of the entire device, while the breakdown voltage of the entire device may be reduced, although compared to the spaced apart arrangement, when the drift region 142 and the body region 132 are arranged adjacently.
The drift region 142 and the first doped region 162 may be disposed adjacent to each other (i.e., the drift region 142 is in direct contact with the first doped region 162) as shown in fig. 1, or may be disposed at intervals. In the embodiment shown in fig. 1, a second conductivity type doped region 122 is also provided between the drift region 142 and the body region 132 and the buried layer 120 of the first conductivity type. In one embodiment of the present application, the drift region 142 is an N-drift, and the second conductivity type doped region 122 under the N-drift is a P-type reduced surface field region (P-RESURF). The second conductive type doped region 122 and the first conductive type buried layer 120 may be disposed adjacent to each other (i.e., the second conductive type doped region 122 is in direct contact with the first conductive type buried layer 120) as shown in fig. 1, or may be disposed at intervals.
Referring to fig. 8, in another embodiment of the present application, the buried layer 120 of the first conductivity type is at least partially in contact with the fourth doped region 168, and bottoms of the first doped region 162, the second doped region 164 and the third doped region 166 are spaced apart from 120. The structure can also shield the substrate from electric leakage. The embodiment shown in fig. 8 may form an NPNP structure with the risk of latch-up due to the second doped region 164, the second conductivity type doped region 122, the buried layer 120 of the first conductivity type and the substrate 110, compared to the embodiment shown in fig. 1. Although there is a risk of latch-up, substrate leakage can still be better shielded.
In one embodiment of the present application, the doping concentration of the third doped region 166 is less than the doping concentration of the first doped region 162. The third doped region 166 is used as a base region of the BJT structure for discharging parasitic leakage, and properly reducing the doping concentration can increase the gain of the BJT and improve the leakage shielding capability. In addition, if the doping concentration of the third doped region 166 is too high, a parasitic leakage path formed by the third doped region 166, the buried layer 120 of the first conductivity type, and the substrate 110 is introduced, and instead substrate leakage is increased. In one embodiment of the present application, the first doped region 162 is a deep P-well and the third doped region 166 is a deep P-type ring.
In one embodiment of the present application, the doping concentration of the second doped region 164 is greater than the doping concentration of the fourth doped region 168. The second doped region 164 serves as an emitter of the BJT structure for discharging parasitic leakage, and increasing the doping concentration thereof can increase the emitter injection efficiency, thereby improving the capability of shielding substrate leakage.
In the embodiment shown in fig. 1, the semiconductor device having the isolation structure further includes a gate 150 disposed over the region between the drain region 140 and the source region 130. In one embodiment of the present application, the gate 150 is a polysilicon material, and in other embodiments, a metal, metal nitride, metal silicide, or similar compound may be used as the material of the gate 150. A gate dielectric layer may also be disposed under gate 150, which may comprise a conventional dielectric material such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).
In one embodiment of the present application, the semiconductor device having the isolation structure further includes a first contact region 161, a second contact region 163, a third contact region 165, and a fourth contact region 167. The first contact region 161 has a second conductivity type and is disposed on the surface of the first doped region 162, and the doping concentration of the first contact region 161 is greater than that of the first doped region 162. The second contact region 163 has the first conductivity type and is disposed on the surface of the second doped region 164, and the doping concentration of the second contact region 163 is greater than that of the second doped region 164. The third contact region 165 has the second conductivity type and is disposed on the surface of the third doped region 166, and the doping concentration of the third contact region 165 is greater than that of the third doped region 166. The fourth contact region 167 has the first conductivity type and is disposed on the surface of the fourth doped region 168, and the doping concentration of the fourth contact region 167 is greater than that of the fourth doped region 168. In the embodiment shown in fig. 1, the first contact region 161 and the second contact region 163 form ohmic contacts with the cathode lead, and the third contact region 165 and the fourth contact region 167 form ohmic contacts with the anode lead. It should be noted that the first doped region 162, the second doped region 164, the third doped region 166 and the fourth doped region 168 cannot be connected to the same potential, because when connected to the same potential, under the condition that the body diode formed by the body region 132 and the drift region 142 is free wheeling, a large amount of electron current rushing into the first conductive type buried layer 120 will cause the potential of the first conductive type buried layer 120 to be lower than that of the third doped region 166, so that the parasitic triode (PNP triode) formed by the third doped region 166, the first conductive type buried layer 120 and the substrate 110 is turned on, the leakage current of the substrate is increased, and the isolation structure is disabled.
In the embodiment shown in fig. 1, the semiconductor device with isolation structures further includes Shallow Trench Isolation (STI) structures 170. The shallow trench isolation structure 170 is disposed between the top of the drift region 142 and the top of the first doped region 162, between the top of the first doped region 162 and the top of the second doped region 164, between the top of the second doped region 164 and the top of the third doped region 166, and between the top of the third doped region 166 and the top of the fourth doped region 168. In other embodiments of the present application, the semiconductor device having the isolation structure further includes a local silicon oxide isolation (LOCOS) disposed between the top of the drift region 142 and the top of the first doped region 162, between the top of the first doped region 162 and the top of the second doped region 164, between the top of the second doped region 164 and the top of the third doped region 166, and between the top of the third doped region 166 and the top of the fourth doped region 168.
In the embodiment shown in fig. 1, the substrate 110 also has a structure leading from the front side of the wafer, i.e. the substrate is led out through the fifth contact region 169. The fifth contact region 169 has the second conductivity type and has a doping concentration greater than that of the substrate 110. In the embodiment shown in fig. 1, the fifth contact region 169 and the fourth contact region 167 are also isolated by a shallow trench isolation structure 170.
In one embodiment of the present application, the doping concentration of drain region 140 is greater than the doping concentration of drift region 142. The doping concentration of the source region 130 is greater than the doping concentration of the body region 132.
Alternatively, the doping concentration of the first-conductivity-type buried layer 120 is made as high as possible to ensure that the first-conductivity-type buried layer 120 does not generate a too large voltage drop when current is inrush into the first-conductivity-type buried layer 120 when the body diode freewheels. In one embodiment of the present application, the doping concentration of the first-conductivity-type buried layer 120 is greater than the doping concentration of the second doping region 164, and the doping concentration of the first-conductivity-type buried layer 120 is greater than the doping concentration of the fourth doping region 168.
The semiconductor device with the isolation structure is applied to a lateral device, such as an LDMOS (laterally diffused metal oxide semiconductor) device. Drain region 140, source region 130, gate 150, body region 132, and drift region 142 are the corresponding structures of an LDMOS.
The present application accordingly provides a method for manufacturing a semiconductor device having an isolation structure, which may be used to manufacture the semiconductor device having an isolation structure of any of the foregoing embodiments. Fig. 2 is a flow chart of a method for manufacturing a semiconductor device having an isolation structure according to an embodiment, including the steps of:
s210, obtaining a wafer.
It is necessary to form a buried layer of the first conductivity type in the substrate of the wafer. Referring to fig. 3, in one embodiment of the present application, a first conductive-type buried layer 320 may be formed by doping in a second conductive-type substrate 310, and then an epitaxial layer 322 of the second conductive-type is epitaxially grown on the substrate 310 and the first conductive-type buried layer 320, with subsequent device structures and isolation structures formed in the epitaxial layer 322. In another embodiment, the buried layer of the first conductivity type may also be formed directly in the middle of the substrate by high-energy ion implantation, and the subsequent device structure and isolation structure are formed in the substrate above the buried layer of the first conductivity type. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type.
After forming the buried layer of the first conductivity type, the drift region and the body region may be formed by doping. Referring to fig. 4 and 5, in one embodiment of the present application, a first conductive type doped region 341 is formed in the epitaxial layer 322 on the first conductive type buried layer 320 by ion implantation. Then, second conductivity type ions are implanted into the first conductivity type doped region 341, so that doped ions in a partial region of the first conductivity type doped region 341 are neutralized to form a body region 332, and a region of the first conductivity type doped region 341 which is not neutralized serves as a drift region 342. In one embodiment of the present application, the drift region 342 is an N-drift, the body region 332 is a P-body, and the ion implantation of the P-body uses a high-energy high-dose P-type impurity implantation. The drift region/body region forming mode can utilize P-RESURF injection at the bottom of the N-drift to improve the concentration of the P-body, thereby enhancing the recombination capability of the P-body on electron current generated during the follow current of the body diode.
In one embodiment of the present application, after forming the drift region 342 and the body region 332, the source region 330 may also be formed in the body region 332, the drain region 340 may be formed in the drift region 342, and the gate 350 may be formed over the region between the drain region 340 and the source region 330.
S220, forming a first doped region, a second doped region, a third doped region and a fourth doped region in the wafer.
Referring to fig. 6 and 7, in one embodiment of the present application, the first doped region 362 and the third doped region 366 may be formed by ion implanting ions of the second conductivity type, and then the second doped region 364 and the fourth doped region 368 may be formed by ion implanting ions of the first conductivity type. The first doped region 362, the second doped region 364, the third doped region 366, and the fourth doped region 368 are sequentially arranged in a direction of the drift region 342 away from the body region 332. In one embodiment of the present application, the doping concentration of the third doped region 366 is less than the doping concentration of the first doped region 362. In one embodiment of the present application, the doping concentration of the second doped region 364 is greater than the doping concentration of the fourth doped region 368. The first conductive type buried layer 320 may entirely cover the bottom of the fourth doped region 368 as shown in fig. 7, or may partially cover, i.e., the right boundary of the first conductive type buried layer 320 is not flush with the right boundary of the fourth doped region 368 in fig. 7. The implantation depths of the first doped region 362, the second doped region 364 and the third doped region 366 may not reach the first conductivity type buried layer 320, i.e., the first doped region 362, the second doped region 364 and the third doped region 366 may be separated from the first conductivity type buried layer 320 by the epitaxial layer 322.
S230, forming a third doped region, a fourth doped region, a first electrode and a second electrode which are electrically connected with the first doped region and the second doped region.
The first electrode lead is electrically connected to the third doped region 366 and the fourth doped region 368, and the second electrode lead is electrically connected to the first doped region 362 and the second doped region 364. When the semiconductor device works, the voltage led out and connected to the first electrode is higher than the voltage led out and connected to the second electrode. In one embodiment of the present application, the first electrode lead is an anode lead, the second electrode lead is a cathode lead, the first electrode is connected to a high potential, and the second electrode is connected to a low potential.
In an embodiment of the present application, step S230 further includes a step of forming the first contact region, the second contact region, the third contact region and the fourth contact region by ion implantation.
The first contact region is provided with a second conductive type and is arranged on the surface of the first doped region, and the doping concentration of the first contact region is larger than that of the first doped region; the second contact region has a first conductivity type and is arranged on the surface of the second doped region, and the doping concentration of the second contact region is greater than that of the second doped region; the third contact region has a second conductivity type and is arranged on the surface of the third doped region, and the doping concentration of the third contact region is greater than that of the third doped region; the fourth contact region has a first conductivity type and is arranged on the surface of the fourth doped region, and the doping concentration of the fourth contact region is greater than that of the fourth doped region; the first electrode lead-out forms ohmic contact with the third contact region and the fourth contact region, and the second electrode lead-out forms ohmic contact with the first contact region and the second contact region.
In one embodiment of the present application, after forming the first conductive-type buried layer 320 in step S210, a step of forming a shallow trench isolation structure is further included. Shallow trench isolation structures may be formed between the top of the drift region 342 and the top of the first doped region 362, between the top of the first doped region 362 and the top of the second doped region 364, between the top of the second doped region 364 and the top of the third doped region 366, and between the top of the third doped region 366 and the top of the fourth doped region 368. In other embodiments of the present application, after forming the first conductive-type buried layer 320 in step S210, a step of forming local silicon oxide isolation (LOCOS) provided between the top of the drift region 342 and the top of the first doped region 362, between the top of the first doped region 362 and the top of the second doped region 364, between the top of the second doped region 364 and the top of the third doped region 366, and between the top of the third doped region 366 and the top of the fourth doped region 368 is further included.
It should be understood that, although the steps in the flowcharts of this application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of this application may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages in other steps or others.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A semiconductor device having an isolation structure, comprising:
a substrate having a second conductivity type;
a buried layer of a first conductivity type disposed in the substrate;
a drift region having a first conductivity type and disposed on the buried layer of the first conductivity type;
a drain region of a first conductivity type disposed within the drift region;
the body region is provided with a second conductive type and is arranged on the buried layer of the first conductive type;
a source region of a first conductivity type disposed within the body region;
the first doped region is provided with a second conductivity type and is arranged on one side of the drift region opposite to the body region and on the buried layer of the first conductivity type;
the second doped region is provided with a first conductive type and is arranged on one side of the first doped region opposite to the drift region and on the buried layer of the first conductive type;
the third doped region is provided with a second conductivity type and is arranged on one side of the second doped region opposite to the first doped region and on the buried layer of the first conductivity type;
a fourth doped region having the first conductivity type and arranged on the first conductivity type buried layer on the opposite side of the third doped region from the second doped region;
the first conductive type and the second conductive type are opposite conductive types, and when the semiconductor device works, the voltage of the potential connected with the third doped region and the fourth doped region is higher than that of the potential connected with the first doped region and the second doped region.
2. The semiconductor device with an isolation structure according to claim 1, wherein a doping concentration of the third doped region is smaller than a doping concentration of the first doped region.
3. The semiconductor device with an isolation structure according to claim 1, wherein a doping concentration of the second doping region is greater than a doping concentration of the fourth doping region.
4. The semiconductor device according to claim 1, wherein a second conductivity type doped region is further provided between the drift region and the body region and the first conductivity type buried layer.
5. The semiconductor device with an isolation structure according to claim 1, wherein a doping concentration of the first conductivity type buried layer is greater than doping concentrations of the second doping region and the fourth doping region.
6. The semiconductor device with an isolation structure according to claim 1, further comprising:
the first contact region is provided with a second conductivity type and is arranged on the surface of the first doped region, and the doping concentration of the first contact region is larger than that of the first doped region;
the second contact region is provided with a first conductive type and is arranged on the surface of the second doped region, and the doping concentration of the second contact region is greater than that of the second doped region;
the third contact region is provided with a second conductivity type and is arranged on the surface of the third doped region, and the doping concentration of the third contact region is greater than that of the third doped region;
and the fourth contact region is provided with the first conductivity type and is arranged on the surface of the fourth doped region, and the doping concentration of the fourth contact region is larger than that of the fourth doped region.
7. The semiconductor device with isolation structure of claim 1, wherein the semiconductor device is an LDMOS device.
8. The semiconductor device with isolation structure according to any one of claims 1 to 7, wherein the first conductivity type is N-type, the second conductivity type is P-type, and the third doped region is a P-type ring.
9. A method of manufacturing a semiconductor device having an isolation structure, comprising:
acquiring a wafer; the wafer comprises: a substrate, a first conductive type buried layer in the substrate, a drift region on the first conductive type buried layer, a body region on the first conductive type buried layer, a drain region in the drift region and a source region in the body region; the substrate and the body region have a second conductivity type, and the drift region, the drain region, and the source region have a first conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types;
forming a first doped region, a second doped region, a third doped region and a fourth doped region which are sequentially arranged in the direction of deviating from the body region of the drift region on the first conductive type buried layer, wherein the first doped region and the third doped region have a second conductive type, and the second doped region and the fourth doped region have a first conductive type;
forming a first electrode lead electrically connected with the third doped region and the fourth doped region and a second electrode lead electrically connected with the first doped region and the second doped region;
when the semiconductor device works, the voltage of the first electrode lead-out access is higher than that of the second electrode lead-out access.
10. The method of manufacturing a semiconductor device having an isolation structure according to claim 9, wherein the step of obtaining the wafer comprises:
forming a first conductive type doped region on the first conductive type buried layer by ion implantation;
implanting second conductivity type ions into the first conductivity type doped region to neutralize the doped ions in a partial region of the first conductivity type doped region to form a body region, wherein a region of the first conductivity type doped region which is not neutralized is used as a drift region;
the source region, drain region, and gate over a region between the drain region and source region are formed.
CN202111599705.6A 2021-12-24 2021-12-24 Semiconductor device having isolation structure and method of manufacturing the same Pending CN116344613A (en)

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