CN116344588A

CN116344588A - SiC MOSFET device and preparation method thereof

Info

Publication number: CN116344588A
Application number: CN202310565977.7A
Authority: CN
Inventors: 邱艳丽; 孙博韬; 徐妙玲; 林信南; 张晨; 修德琦; 韩丽楠
Original assignee: Beijing Century Goldray Semiconductor Co ltd
Current assignee: Xinhe Semiconductor Hefei Co ltd
Priority date: 2023-05-18
Filing date: 2023-05-18
Publication date: 2023-06-27

Abstract

The application discloses a SiC MOSFET device and a preparation method thereof, the SiC MOSFET device forms a plurality of inversion injection regions which are distributed at intervals in a drift region, so that any two adjacent inversion injection regions and the drift region between the two adjacent inversion injection regions form a JFET region, namely the JFET region extends towards a substrate, so that the maximum electric field position is far away from the surface of the device and is transferred towards the inside of the drift region, the maximum electric field position is separated from a channel region with concentrated maximum current density, and the current density distribution of the drift region is more uniform, therefore, hot spots of the device after short circuit are not concentrated on the surface of the device near the channel any more, but are closer to the substrate, and are more uniformly distributed in the drift region, thereby reducing the failure probability of melting of a gate oxide layer and gate metal, delaying the occurrence time of heat escape, reducing the hot spot temperature, improving the short circuit resistance capability of the device and increasing the short circuit resistance time of the device.

Description

SiC MOSFET device and preparation method thereof

Technical Field

The application relates to the technical field of semiconductors, in particular to a SiC MOSFET device and a preparation method thereof.

Background

Silicon carbide (SiC) power devices belong to third-generation semiconductor power devices, have higher energy density and thermal conductivity compared with Si power devices, have important significance for promoting energy conservation, emission reduction and carbon neutralization, and are the trend of time development for replacing Si power devices by SiC power devices.

The SiC power device has a wider application range of SiC metal oxide semiconductor field effect transistors (MetalOxide Semiconductor Field Effect Transistor, MOSFETs), however, the short-circuit tolerance time of SiC MOSFETs is one of the serious problems in the current application process. Short circuit often appears in high-power application occasions such as motor drive, and when short circuit happens, the power device is directly connected with the extremely high busbar voltage, and a large amount of heat can be generated in the power device generally within a few microseconds, so that the power device is invalid, and the power device and equipment are damaged in a disastrous way due to high energy in the short circuit, and even serious damage, fire and other conditions of the equipment are caused. Short circuit reliability is one of the device reliability and can be used for measuring the capability of the SiC MOSFET to bear high voltage and high current simultaneously under the condition of channel opening. To avoid serious disasters caused by short circuits, the device is usually provided with a protection circuit to turn off the SiC MOSFET protection load in time. But before the protection circuit responds, it should be ensured that the SiC MOSFET has a certain short-circuit withstand time.

Due to the higher power density, denser cell arrangement, and the like of SiC MOSFET devices, the short-circuit withstand time of SiC MOSFET devices is significantly shorter than that of Si insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) devices, and in particular, siC MOSFET devices typically have a short-circuit withstand time of about 10 μs due to short-circuit and resulting power loss in the range of 2-3 μs. Therefore, how to improve the short-circuit tolerance time of SiC MOSFET devices is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In order to solve the technical problems, the embodiment of the application provides a SiC MOSFET device and a preparation method thereof, so as to improve the short-circuit tolerance time of the SiC MOSFET device.

In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions:

a SiC MOSFET device, comprising:

a SiC substrate;

the first drift region is positioned at one side of the SiC substrate, and the SiC substrate and the first drift region are both doped with the first type;

the well regions are arranged at intervals along a first direction and are positioned at one side of the first drift region, which is away from the SiC substrate, the well regions are of second type doping, source regions are arranged in the well regions, the source regions are of first type doping, and the first direction is parallel to the plane of the SiC substrate;

the first drift region comprises a first region between two adjacent well regions and a second region positioned at one side of the first region and the well region close to the SiC substrate, the second region is provided with a plurality of inversion implantation regions which are arranged at intervals along the first direction, and the inversion implantation regions are of second type doping;

the first drift region is arranged on the side, away from the SiC substrate, of the gate oxide layer, the gate electrode, the isolation medium layer and the source electrode, and the second drift region is arranged on the side, away from the first drift region, of the SiC substrate.

Optionally, in the first direction, the spacing between any two adjacent inversion implantation regions is equal.

Optionally, a surface of the well region facing away from the SiC substrate is a channel region;

in the first direction, a spacing between two adjacent inversion implantation regions distant from the channel region is larger than a spacing between two adjacent inversion implantation regions close to the channel region.

Optionally, the doping concentration of the inversion implantation region is greater than the doping concentration of the well region.

Optionally, the doping concentration of the inversion implantation region is in the range of 1×10 ¹⁷ cm ^-3 -1×10 ²² cm ^-3 Including endpoint values.

Optionally, the method further comprises:

and a second drift region between the SiC substrate and the first drift region, wherein the second drift region is doped with the first type, and the doping concentration of the first drift region is greater than that of the second drift region.

Optionally, the first drift region further comprises a third region located between the inversion implantation region and the second drift region.

Optionally, the well region, the source region and the first drift region all extend along a second direction, and the second direction is parallel to a plane of the SiC substrate and perpendicular to the first direction;

The well region is also provided with a plurality of source contact regions which are arranged at intervals along the second direction, the source contact regions penetrate through the source region and the well region, the source contact regions are doped with the second type, the doping concentration of the source contact regions is larger than that of the well region, and the source contact regions and the source form ohmic contact.

Optionally, the inversion implantation region extends along the second direction;

and a common contact region is arranged on at least one side of the first drift region along the second direction, the common contact region is doped with the second type, and ohmic contact is formed between the common contact region and the source electrode, so that each inversion implantation region is electrically connected with the source electrode through the common contact region.

A method of fabricating a SiC MOSFET device comprising:

providing a SiC substrate, forming an epitaxial layer on one side of the SiC substrate, wherein the SiC substrate and the epitaxial layer are both doped in a first mode;

performing first ion implantation on the epitaxial layer to enable at least part of the epitaxial layer to form a first drift region;

performing second type ion implantation on the first drift region by using a first preset mask, and forming a plurality of inversion implantation regions which are arranged at intervals along a first direction in the first drift region, wherein the first direction is parallel to the plane of the SiC substrate;

Performing second type ion implantation on one side, away from the SiC substrate, of part of the inversion implantation region in the first drift region by using a second preset mask plate to form a well region, wherein the well regions are arranged at intervals along the first direction, so that the first drift region comprises a first region between two adjacent well regions and a second region positioned on one side, close to the SiC substrate, of the first region and the well region, and the second region is provided with the inversion implantation region;

performing first type ion implantation on the well region by using a third preset mask plate, and forming a source region in the well region;

forming a gate oxide layer and a gate sequentially on one side of the well region and the first region, which is away from the SiC substrate;

forming an isolation medium layer, wherein the isolation medium layer is provided with a through hole which penetrates through, and the source region is exposed by the through hole;

forming a source electrode, wherein the source electrode forms ohmic contact with the source region through the through hole;

and forming a drain electrode on one side of the SiC substrate, which is away from the first drift region.

Compared with the existing SiC MOSFET device, only two adjacent well regions and a drift region between the two adjacent well regions form a JFET region, so that the maximum electric field position is concentrated at the corners of the well regions and is close to a channel region with concentrated maximum current density, the heat generation point of the device after short circuit is concentrated at the surface of the device near the channel, the short circuit tolerance time is short, and the SiC MOSFET device provided by the embodiment of the invention forms a plurality of inversion injection regions which are distributed at intervals in the well regions and the drift region between the two adjacent well regions, which are close to one side of a substrate, and the doping types of the inversion injection regions and the drift region are opposite, so that any two adjacent inversion injection regions and the drift region between the two adjacent inversion injection regions also form the JFET region, namely the JFET region extends towards the direction of the substrate; in the second aspect, after the carrier flow flows out of the channel, the carrier flow is dispersed by a plurality of inversion injection regions, flows through the JFET region between two adjacent inversion injection regions, then expands to the drift region, and flows out of the drain electrode, namely the current density distribution of the drift region is more uniform; because the heat generated everywhere in the device is proportional to the current density and the electric field intensity at the position, hot spots of the device after short circuit are not concentrated on the surface of the device near the channel, but are closer to the substrate and are more uniformly distributed in the drift region, so that the failure probability of gate oxide melting and gate metal melting is reduced, the time of thermal escape is delayed, the temperature at the hot spots is reduced, the short circuit resistance capability of the SiC MOSFET device is improved, and the short circuit resistance time of the SiC MOSFET device is prolonged.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic cross-sectional structure of a conventional SiC MOSFET device;

fig. 2 is a schematic cross-sectional structure of a SiC MOSFET device according to an embodiment of the present application;

fig. 3 is a schematic perspective view of a SiC MOSFET device according to an embodiment of the present application;

fig. 4 is a schematic diagram showing a current density distribution of a half cell structure of a conventional SiC MOSFET device at a short-circuit time t=1 μs;

fig. 5 is a schematic diagram of a current density distribution of a half cell structure of a SiC MOSFET device according to an embodiment of the present application at a short-circuit time t=1μs;

fig. 6 is a schematic diagram showing a temperature distribution of a half cell structure of a conventional SiC MOSFET device at a short-circuit time t=1 μs;

fig. 7 is a schematic diagram of a temperature distribution of a half cell structure of a SiC MOSFET device provided in an embodiment of the present application at a short-circuit time t=1μs;

FIG. 8 shows the gate voltage V of a conventional SiC MOSFET device and a SiC MOSFET device provided in an embodiment of the present application _gate Drain current I _drain And the highest temperature T in the device _max Comparing the schematic diagram with the change relation of the short circuit time t;

FIG. 9 is a schematic cross-sectional view of the SiC MOSFET device of FIG. 3 along AA';

fig. 10 (a) -fig. 10 (i) are schematic device structures corresponding to each process step in the method for manufacturing a SiC MOSFET device according to the embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the schematic drawings, wherein the cross-sectional views of the device structure are not to scale for the sake of illustration, and the schematic drawings are merely examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

It should be noted that the terms "first," "second," and "third" in the description and claims of the present application are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

FIG. 1 shows a schematic cross-sectional structure of a prior art SiC MOSFET device, as shown in FIG. 1, including N ⁺ Substrate 01 and located at N ⁺ N of substrate 01 one side is arranged in proper order ^- Drift region 02, N drift region 03, P well region 04, P ⁺⁺ Source contact regions 05 and N ⁺ Source region 06 with gate 07 and source 08 located in N drift region 03 facing away from N ⁺ A gate oxide layer 09 is arranged between the gate electrode 07 and the P well region 04 and between the gate electrode 07 and the N drift region 03, an isolation medium layer 010 is arranged between the gate electrode 07 and the source electrode 08, and the gate oxide layer 09 and the isolation medium layer 010 can be SiO ₂ Insulating layer, drain 011 is located at N ⁺ Substrate 01 facing away from N ^- Drift region 02 side. Wherein, two adjacent P-well regions 04 and an N-drift region 03 between the two adjacent P-well regions 04 form two back-to-back PN junctions, i.e., junction Field-Effect Transistor (JFET) regions, which generate a JFET effect.

During operation of the SiC MOSFET device, when no forward bias is applied to the gate 07 and no forward bias is applied to the drain 011, the SiC MOSFET is in a reverse off state, at which time the two PN junctions of the JFET region are in reverse bias, and the voltage applied between the drain 011 and the source 08 is defined by N ^- Drift region 02 and N drift region 03 (mainly consisting of N ^- Drift region 02) is assumed; when the gate 07 is forward biased and the drain 011 is also forward biased, the SiC MOSFET is in a forward-conducting state, at which time the two PN junctions of the JFET region remain in reverse bias, and the P-well region 04 faces away from N ⁺ The surface of the substrate 01 forms an inversion channel region through which electron flow from the source 08 flows into the JFET region and then extends down through the JFET region to the N drift region 03 and N ^- Drift region 02 flows out of drain 011.

As described in the background section, the short-circuit tolerance time of SiC MOSFETs is one of the serious problems in current applications. The inventor researches and discovers that when short circuit occurs, main heating points of the traditional SiC MOSFET device are concentrated on the surface of the device near a channel, so that the melting failure of a gate oxide layer, the breaking melting failure of a source metal and the thermal escape failure are easy to cause, and the short circuit tolerance time of the device is short. Short circuit failure of current SiC MOSFET devices is mainly manifested in the following three types.

The first is gate oxide melting failure, which is easily generated during the turn-off period of the SiC MOSFET device after the short circuit, at this time, the device loses control of the channel region, the current suddenly increases, a large amount of heat is generated to raise the junction temperature, and the channel heat is concentrated to cause the gate oxide melting failure.

The second is that the source metal is melted and failed, and since the source metal is usually aluminum metal, the device temperature is easily raised to the melting point of aluminum (about 660 ℃) after the occurrence of short circuit, and the aluminum electrode is melted and broken to fail.

And thirdly, the thermal runaway (thermal escape) is invalid, the temperature of the heat released by the channel region of the MOSFET can be increased, so that the temperature of a depletion region between the P-well region 04 and the N-drift region 03 is increased, the concentration of intrinsic carriers is increased sharply, larger drain current is formed after the carriers drift, the increased drain current can generate more heat, if the generated heat in unit time is larger than the heat dissipation power of the device, the temperature of the device can be increased continuously, and the higher temperature can lead to the further increase of the drain current, so that the positive temperature feedback effect of the temperature and the drain current is formed. Due to the characteristics of SiC materials, siC power devices are much thinner and much narrower than Si power devices, so that SiC power devices have higher power densities, junction temperatures during short circuits can even exceed 1000K, and thermal runaway failures are prone to occur when the heat dissipation rate is slower than the rate of heat increase due to drain current. And local defects or slight process variations in the device can lead to non-uniformity in current density and temperature, thereby forming local hot spots that melt the structure and cause device failure.

The inventors have further studied and found that, since the JFET effect of the conventional SiC MOSFET device is generated between the P-well region 04 and the N-drift region 03, the maximum electric field is concentrated at the corners of the P-well region 04, and at the same time, the maximum current density is concentrated at the channel region, and as can be seen from fig. 1, the corners of the P-well region 04 where the maximum electric field is located are located closer to the channel region where the maximum current density is concentrated. Because the heat generated by each part in the device is proportional to the power of the part, the larger the power is, the more the generated heat is, the higher the temperature is, and the power of the part is proportional to the current density and the electric field intensity of the part, namely the heat generated by each part in the device is proportional to the current density and the electric field intensity of the part, so that the main heating point of the traditional SiC MOSFET device is concentrated on the surface of the device near a channel, thereby easily causing the melting failure of a gate oxide layer, the melting failure of source metal and the thermal escape failure, and further shortening the short-circuit tolerance time of the device.

Based on the above-mentioned research, the embodiment of the present application provides a SiC MOSFET device and a method for manufacturing the same, where a plurality of inversion injection regions are formed in a well region and a drift region between two adjacent well regions, the inversion injection regions being arranged at intervals in a drift region near one side of a substrate, and doping types of the inversion injection regions and the drift region being opposite, so that any two adjacent inversion injection regions and the drift region between the two adjacent inversion injection regions also form a JFET region, i.e., the JFET region extends toward the substrate, and at this time, a maximum electric field position is located at a corner of the inversion injection region, i.e., the maximum electric field position is far away from the surface of the device and is shifted toward the inside of the drift region, and at the same time, the maximum electric field position is separated from a channel region having a concentrated maximum electric current density; in the second aspect, after the carriers flow out of the channel, the carriers are dispersed by a plurality of inversion injection regions, flow through the JFET region between two adjacent inversion injection regions, then spread to a drift region, and flow out of the drain, namely the current density distribution of the drift region is more uniform; because the heat generated everywhere in the device is proportional to the current density and the electric field intensity at the position, hot spots of the device after short circuit are not concentrated on the surface of the device near the channel, but are closer to the substrate and are more uniformly distributed in the drift region, so that the failure probability of gate oxide melting and gate metal melting is reduced, the time of thermal escape is delayed, the temperature at the hot spots is reduced, the short circuit resistance capability of the SiC MOSFET device is improved, and the short circuit resistance time of the SiC MOSFET device is prolonged.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Fig. 2 is a schematic cross-sectional structure of a SiC MOSFET device provided in an embodiment of the present application, fig. 3 is a schematic perspective structure of a SiC MOSFET device provided in an embodiment of the present application, and in combination with fig. 2 and 3, the SiC MOSFET device includes:

a SiC substrate 1;

the first drift region 2 is positioned on one side of the SiC substrate 1, and the SiC substrate 1 and the first drift region 2 are doped with the first type;

well regions 3 which are arranged at intervals along a first direction X and are positioned at one side of the first drift region 2 away from the SiC substrate 1, wherein the well regions 3 are doped with a second type, source regions 4 are arranged in the well regions 3, the source regions 4 are doped with the first type, and the first direction X is parallel to the plane of the SiC substrate 1;

the first drift region 2 comprises a first region 2a between two adjacent well regions 3 and a second region 2b positioned on one side of the first region 2a and the well regions 3 close to the SiC substrate 1, the second region 2b is provided with a plurality of inversion implantation regions 5 which are arranged at intervals along a first direction X, and the inversion implantation regions 5 are doped in a second type;

a gate oxide layer 6, a gate electrode 7, an isolation medium layer 8 and a source electrode 9 on the side of the first drift region 2 facing away from the SiC substrate 1, and a drain electrode 10 on the side of the SiC substrate 1 facing away from the first drift region 2.

In this embodiment of the present application, the first type doping and the second type doping are different, and optionally, the first type doping is N type doping, and then the second type doping is P type doping, whereas the first type doping is P type doping, and then the first type doping is N type doping.

In the embodiment of the present application, on the side of the first drift region 2 facing away from the SiC substrate 1, the gate oxide layer 6 and the gate electrode 7 are sequentially stacked in the direction facing away from the SiC substrate 1 (Z direction in fig. 2), and the gate oxide layer 6 and the gate electrode 7 cover the first region 2a of the first drift region 2 and at least part of the surface of the well region 3 facing away from the SiC substrate 1.

On the side of the first drift region 2 facing away from the SiC substrate 1, an isolation dielectric layer 8 covers the gate to isolate the gate 7 and the source 9, and the isolation dielectric layer 8 has a through-hole therethrough such that the source 9 forms an ohmic contact with the source region 4 through the through-hole penetrating the isolation dielectric layer 8. And, the source electrode 9 is also electrically connected to the well region 3 to transmit the electric potential of the source electrode 9 to the surface of the well region 3 facing away from the SiC substrate 1 and covered by the gate electrode 7 and the gate oxide layer 6, so that the well region 3 covered by the gate oxide layer 6 and the gate electrode 7 forms an inversion channel region when the gate electrode 7 is biased accordingly.

In the embodiment of the present application, the first drift region 2 is doped with the first type, and the well region 3 and the inversion injection region 5 are doped with the second type, so that, unlike the conventional SiC MOSFET device, not only the adjacent two well regions 3 and the drift region (the first region 2 a) between the adjacent two well regions 3 form a JFET region, but also any adjacent two inversion injection regions 5 and the drift region between the adjacent two inversion injection regions form a JFET region.

Compared with the existing SiC MOSFET device, only two adjacent well regions and a drift region between the two adjacent well regions form a JFET region, so that the maximum electric field position is concentrated at the corners of the well regions and is close to a channel region with concentrated maximum current density, a heating point of the device after short circuit is concentrated on the surface of the device near the channel, the melting of a gate oxide layer and the melting of source metal are easy to cause local failure of the device, the short circuit tolerance time is short, the JFET region extends towards the substrate direction, and at the moment, the maximum electric field position is located at the corners of an inversion injection region 5, namely the maximum electric field position is far away from the surface of the device and is transferred into the first drift region 2, and meanwhile, the maximum electric field position and the channel region with concentrated maximum current density are separated. Because the heat generated everywhere in the device is proportional to the current density and the electric field intensity at the position, hot spots of the device after short circuit are not concentrated on the surface of the device near the channel any more, but are generated in the drift region far away from the surface of the device, so that the failure probability of gate oxide melting and gate metal melting is reduced, the short circuit resistance capability of the SiC MOSFET device is improved, and the short circuit resistance time of the SiC MOSFET device is prolonged.

The following describes the operation of the SiC MOSFET device provided in the embodiment of the present application in a simple manner, taking the first type doping as N-type doping and the second type doping as P-type doping as an example.

In particular, when the gate 7 is forward biased and the drain 10 is also forward biased, the SiC MOSFET is in a forward on state, at this time, the well region 3 faces away from the SiC substrate 1 and the surface covered by the gate 7 and the gate oxide 6 forms an inversion channel region, and the JFET region formed by the two adjacent well regions 3 and the drift region (the first region 2 a) between the two adjacent well regions 3 and the JFET region formed by the two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 are all in reverse bias, and the electron flow flows from the source 9 through the channel region into the JFET region between the two adjacent well regions 3, is dispersed by the plurality of inversion injection regions 5, flows from the JFET region between the two adjacent inversion injection regions 5, and flows from the drain.

When the gate 7 is not forward biased and the drain 10 is forward biased, the SiC MOSFET is in a reverse off state, at which time the JFET region constituted by the adjacent two well regions 3 and the drift region (first region 2 a) between the adjacent two well regions 3 and the JFET region constituted by the adjacent two inversion implantation regions 5 and the drift region between the adjacent two inversion implantation regions 5 are also in reverse bias, and the voltage applied between the drain 10 and the source 9 is borne by the first drift region 2.

Wherein when the SiC MOSFET device is in a forward on state, it is desirable that the two reverse biased PN junctions in the JFET region not pinch off in order to allow electron flow through the JFET region, and when the SiC MOSFET device is in a reverse off state, it is desirable that the two reverse biased PN junctions in the JFET region pinch off in order to reduce drain current, so that the SiC MOSFET device has a smaller forward bias for the drain 10 in the forward on state and a larger forward bias for the drain 10 in the reverse off state.

Therefore, compared with the existing SiC MOSFET device, after the carrier flow (such as the electron flow) flows out from the channel, the carrier flow (such as the electron flow) extends to the drift region through the JFET region between the two adjacent well regions and then flows out from the drain, and in the SiC MOSFET device provided in this embodiment of the present application, the carrier flow (such as the electron flow) flows out from the channel, passes through the JFET region between the two adjacent well regions 3, and then is dispersed by the plurality of inversion injection regions 5, and flows through the JFET region between the two adjacent inversion injection regions 5 and then flows out from the drain, that is, the current density distribution of the first drift region 2 is more uniform. Since the heat generated everywhere inside the device is proportional to the current density and the electric field strength at the location, the current density and the generated heat of the device after the short circuit are more uniformly distributed in the first drift region 2, and the temperature at the hot spot can be reduced.

It will be appreciated that after a short circuit occurs, the heat build-up in the device reaches the critical energy E for the short circuit _c After that, the device will be locally disabled, in particular, the critical energy E of short circuit _c Can be expressed as:

wherein t is _sc For short-circuit tolerance time, V _ds Is the drain voltage, I _d Is the drain current.

After the temperature at the hot spot is reduced, the device can reach the short-circuit critical energy E _c Thereby improving the short circuit withstand time of the SiC MOSFET device.

In addition, as known from the foregoing, when the device temperature increases to a certain extent (for SiC MOSFET devices, up to 1000K), the intrinsic carrier concentration increases exponentially with the temperature, so that the drain current increases rapidly, the increased drain current generates more heat, if the heat generated per unit time is greater than the heat dissipation power of the device, the device temperature continues to increase, and the higher temperature causes the drain current to increase further, thereby forming a positive temperature feedback effect of the temperature and the drain current, and finally causing the device to generate thermal runaway and fail. In the SiC MOSFET device provided in the embodiment of the present application, the hot spot of the device after the short circuit is transferred to the inside of the first drift region 2 far away from the surface of the device, and the current density of the device after the short circuit and the generated heat are more uniformly distributed in the first drift region 2, so that the rising speed of the temperature of the device after the short circuit can be reduced, the highest temperature and the maximum current density of the device are reduced as a whole, and the time of the occurrence of the thermal runaway is delayed, thereby increasing the short circuit tolerance time of the SiC MOSFET device.

It is worth to describe that, the SiC MOSFET device provided in the embodiments of the present application improves the short-circuit resistance and increases the short-circuit tolerance time, and at the same time, other electrical properties of the device, such as the forward on-resistance and the reverse breakdown voltage, of the device are not affected by optimizing the structure and the doping design. The following is a detailed description.

In this embodiment of the present application, since a plurality of inversion implantation regions 5 are formed in the second region 2b of the first drift region 2 and are arranged at intervals, any two adjacent inversion implantation regions 5 and the drift region between the two adjacent inversion implantation regions 5 also form a JFET region, so that the forward on-resistance of the device can be increased. At this time, alternatively, the doping concentration of the first drift region 2 may be increased to reduce the forward on-resistance of the device, but it will be appreciated that this makes the drain reverse biased, so that the drain current is greater, resulting in a reduction in the reverse breakdown voltage of the device.

Alternatively, the forward on-resistance of the device can be reduced by increasing the distance between two adjacent inversion injection regions 5, so that the carrier flow (such as the electron flow) can flow more smoothly through the drift region between two adjacent inversion injection regions 5, i.e. the resistance of the JFET region formed by two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 is reduced, but the drain current is larger when the drain is reversely biased, so that the reverse breakdown voltage of the device is reduced.

Therefore, the doping concentration of the first drift region 2 and the distance between two adjacent inversion injection regions 5 in the SiC MOSFET device can be optimized, so that other electrical properties (such as forward on-resistance and reverse breakdown voltage) of the device can meet the requirements, namely the short circuit resistance of the device is improved, the short circuit tolerance time of the device is prolonged, and the other electrical properties of the device can not be influenced.

It should be noted that, as shown in fig. 2 and fig. 3, in a direction (Z direction) perpendicular to a plane where the SiC substrate 1 is located, the drain electrode 10, the SiC substrate 1, the first drift region 2, the well region 3, the source region 4, the gate oxide layer 6, the gate electrode 7, the isolation dielectric layer 8, and the source electrode 9 sequentially form a cell structure, specifically, as shown by solid line box marks in fig. 2, the dashed line box marks in fig. 2 are shown by half cell structures, and the number of cell structures included in the SiC MOSFET device is not limited in this application, which is specifically determined according to circumstances.

The number of inversion implantation regions 5 provided in the second region 2b of the first drift region 2 is not limited in the present application. It will be appreciated that the greater the number of inversion injection regions 5 provided in the second region 2b of the first drift region 2 along the first direction X, the more uniformly the carrier flow will flow out of the channel, the greater the device's resistance to shorting, the longer the device's resistance to shorting, but at the same time the device's forward on-resistance is relatively greater.

The doping concentration of the inversion implantation region 5 provided in the second region 2b of the first drift region 2 is not limited in the present application. It will be appreciated that the greater the doping concentration of the inversion implantation region 5, the smaller the volume of the inversion implantation region 5 required to achieve the same effect, and the more unobstructed the carrier flow can flow through the drift region between two adjacent inversion implantation regions 5, with less impact on the forward on-resistance of the device.

The depth of the inversion implantation region 5 provided in the second region 2b of the first drift region 2 is not limited in this application. It will be appreciated that the implantation depth of the inversion implantation region 5 refers to the distance between the surface of the inversion implantation region 5 on the side close to the SiC substrate 1 and the surface of the first region 2a of the first drift region 2 facing away from the SiC substrate 1, and that the deeper the implantation depth of the inversion implantation region 5, the further the location of the maximum electric field is from the device surface, so that the further the device is from the device surface after short-circuiting.

In addition, the doping concentration distribution of the first drift region 2 is not limited in this application, and may be a uniform distribution, or may be a non-uniform distribution, such as a superposition of a plurality of gaussian distributions, or the like, as the case may be.

Further, the inventor performs TCAD simulation verification on a half cell structure of an existing SiC MOSFET device and a half cell structure of the SiC MOSFET device provided by the embodiment of the present application, where the half cell structure of the existing SiC MOSFET device is shown by a dashed box in fig. 1, and the half cell structure of the SiC MOSFET device provided by the embodiment of the present application is shown by a dashed box in fig. 2, and includes a drain electrode, a SiC substrate, a drift region, a well region, a source region, a gate oxide layer, a gate electrode, an isolation medium layer, and a source electrode that are sequentially arranged.

Fig. 4 and fig. 5 are schematic diagrams showing the current density distribution of the half cell structure of the conventional SiC MOSFET device and the half cell structure of the SiC MOSFET device provided in the embodiments of the present application when the short-circuit time t=1μs, respectively, and comparing fig. 4 and fig. 5, it can be seen that, in the half cell structure of the conventional SiC MOSFET device, the maximum current density is concentrated near the channel and only slightly expands in the drift region; in the half cell structure of the SiC MOSFET device provided in the embodiment of the present application, although the maximum current density is still concentrated near the channel, the current density distribution in the first drift region 2 is more uniform due to the shunting effect of the plurality of inversion injection regions 5.

Fig. 6 and fig. 7 are schematic diagrams showing the temperature distribution of the half cell structure of the conventional SiC MOSFET device and the half cell structure of the SiC MOSFET device provided in the embodiments of the present application when the short-circuit time t=1 μs, respectively, and comparing fig. 6 and fig. 7, it can be seen that, in the half cell structure of the conventional SiC MOSFET device, the hot spots are mainly concentrated on the device surface near the channel, so that the gate oxide melting failure, the source metal breaking melting failure and the thermal escape failure are easily caused; in the half cell structure of the SiC MOSFET device provided by the embodiment of the application, hot spots are not concentrated on the surface of the device near the channel, but are generated in the drift region far away from the surface of the device, and are uniformly distributed in the drift region, so that the heat dissipation capacity of the whole device can be utilized, the failure probability of gate oxide melting and source metal melting is reduced, the time of thermal escape occurrence is delayed, the short circuit resistance capacity of the device is improved, and the short circuit resistance time is prolonged.

FIG. 8 shows the gate voltage V of a conventional SiC MOSFET device and a SiC MOSFET device provided in an embodiment of the present application _gate Drain current I _drain And the highest temperature T in the device _max Comparing the change relation with the short-circuit time t with a schematic diagram, wherein at the moment, the existing SiC MOSFET device and the SiC MOSFET device provided by the embodiment of the application are both N-channel MOSFET devices, and the device is short-circuited when the time t=0, and the drain-source voltage V is higher than the drain-source voltage V _ds When t=20ns, the gate voltage V is set to be positive _gate =20v. As can be seen from fig. 8, the short-circuit time for thermal runaway of the conventional SiC MOSFET device is about 1.7 μs after the short-circuit is turned on, and the short-circuit tolerance time of the SiC MOSFET device provided in the embodiment of the present application is increased to 4.2 μs, which is about 2.5 times longer than that of the conventional SiC MOSFET device.

For the spacing arrangement between two adjacent inversion implantation regions 5, alternatively, in one embodiment of the present application, as shown in fig. 2 and 3, the spacing between any two adjacent inversion implantation regions 5 may be equal in the first direction X. In the actual process, after forming the first drift region 2 of the first type doping on one side of the SiC substrate 1 of the first type doping, a plurality of inversion implantation regions 5 are formed in the first drift region 2 of the first type doping at intervals along the first direction X by an ion implantation process, and in this embodiment, the spacing between any two adjacent inversion implantation regions 5 is equal in the first direction X.

Alternatively, in another embodiment of the present application, considering that the surface of the well region 3 facing away from the SiC substrate 1 may be covered by the gate oxide layer 3 and the gate electrode 7 to form a channel region, and the channel region is a region in which the maximum current density is concentrated, in order to make the current density distribution of the first drift region 2 more uniform by expanding as much as possible along the first direction X after the carrier flow flows out of the channel region, therefore, in the present embodiment, the interval between two adjacent inversion injection regions 5 far from the channel region may be set larger than the interval between two adjacent inversion injection regions 5 near the channel region in the first direction X.

It will be appreciated that when a carrier flow circulates in the drift region between two adjacent inversion injection regions 5, the smaller the distance between two adjacent inversion injection regions 5, the narrower the drift region between two adjacent inversion injection regions 5 in which carriers can circulate, the larger the resistance formed by the JFET region between the two adjacent inversion injection regions 5, whereas the larger the distance between two adjacent inversion injection regions 5, the wider the drift region between two adjacent inversion injection regions 5 in which carriers can circulate, and the smaller the resistance formed by the JFET region between two adjacent inversion injection regions 5.

In the present embodiment, the distance between the adjacent two inversion injection regions 5 away from the channel region is set to be larger than the distance between the adjacent two inversion injection regions 5 close to the channel region, and therefore, the carrier flow tends to flow to the place where the resistance is smaller, and after flowing out of the channel region, the carrier flow tends to flow from the drift region between the adjacent two inversion injection regions 5 away from the channel region, and after flowing out of the channel region, the carrier flow expands as much as possible along the first direction X, so that the current density distribution of the first drift region 2 is more uniform.

Optionally, in an embodiment of the present application, the doping concentration of the inversion implantation region 5 is greater than the doping concentration of the well region 3.

The larger the doping concentration of the inversion injection region 5 is, the smaller the volume of the inversion injection region 5 required for forming depletion regions with the same width in the drift region between two adjacent inversion injection regions 5 is, so that the smaller the volume of all inversion injection regions 5 arranged in the second region 2b of the first drift region 2 is, and the larger the space of the drift region for carrying out carrier flow in the second region 2b of the first drift region 2 is, and the smaller the effect on the forward on-resistance of the device is; in addition, since the two adjacent inversion injection regions 5 and the drift region between the two adjacent well regions 3 and the two adjacent well regions 3 both form JFET regions, and the width of the drift region between the two adjacent inversion injection regions 5 is smaller than the width of the drift region between the two adjacent well regions 3 in the first direction X, in this embodiment, the doping concentration of the inversion injection regions 5 is set to be greater than the doping concentration of the well regions 3, so that the space of the drift region for carrying out carrier flow in the second region 2b of the first drift region 2 is sufficiently large, and the effect on the forward on-resistance of the device is small.

Since the doping concentration of the well region 3 is typically 1×10 ¹⁵ cm ^-3 -1×10 ²⁰ cm ^-3 Thus, further alternatively, in one embodiment of the present application, the doping concentration of the inversion implantation region 5 may be in the range of 1×10 ¹⁷ cm ^-3 -1×10 ²² cm ^-3 Including endpoint values. At this time, the inversion injection region 5 disposed in the second region 2b of the first drift region 2 not only effectively improves the short-circuit resistance of the device, but also makes the space of the drift region for the flow of carriers in the second region 2b of the first drift region 2 sufficiently large, and has less influence on the forward on-resistance of the device.

Alternatively to the implantation depth of the inversion implantation region 5, in one embodiment of the present application, the implantation depth of the well region 3 may be 0.1 μm to 1 μm, inclusive, and since the inversion implantation region 5 is located on the side of the well region 3 close to the SiC substrate, the implantation depth of the inversion implantation region 5 may be 0.5 μm to 1.5 μm, inclusive.

In the present embodiment, similarly to the implantation depth of the inversion implantation region 5, the implantation depth of the well region 3 refers to the distance between the surface of the well region close to the SiC substrate 1 and the surface of the first region 2a of the first drift region 2 facing away from the SiC substrate 1 (i.e., the surface of the well region 3 facing away from the SiC substrate 1).

Optionally, in one embodiment of the present application, as shown in fig. 2 and fig. 3, the SiC MOSFET device may further include: the second drift region 11 is located between the SiC substrate 1 and the first drift region 2, the second drift region 11 is doped of the first type, and the doping concentration of the first drift region 2 is greater than the doping concentration of the second drift region 11.

As is known from the foregoing, when the SiC MOSFET is in the reverse off state, the voltage applied between the drain 10 and the source 9 is borne by the first drift region 2, but in practice, the reverse breakdown voltage borne by the first drift region 2 is still small, so in this embodiment, the second drift region 11 is provided between the SiC substrate 1 and the first drift region 2, the second drift region 11 and the first drift region 2 are both doped with the same doping type as the first type, and the doping concentration of the first drift region 2 is greater than that of the second drift region 11, so that a depletion region (mainly in the second drift region) is formed with the second drift region 11 and the reverse injection region 5 having lower doping concentrations to bear a larger reverse voltage between the drain 10 and the source 9.

It should be noted that the second drift region 11 should be ensured to have a sufficient thickness so that the depletion region formed by the plurality of inversion injection regions 5 and the second drift region 11 (mainly in the second drift region 11) is sufficient to take up the reverse voltage between the drain 10 and the source 9, preventing the device from being broken down.

As is known from the foregoing, after the carrier flow has flowed out of the channel, it flows from the drift region between the two adjacent inversion injection regions 5, optionally, in one embodiment of the present application, as shown in fig. 2, the first drift region 2 further comprises a third region 2c located between the inversion injection regions 5 and the second drift region 11, in order to further spread the carrier flow flowing from the drift region between the two adjacent inversion injection regions 5 in the first direction X. In the present embodiment, the third region 2c may serve as a current expansion region such that a carrier flow flowing from a drift region between two adjacent inversion injection regions 5 expands in the first direction X and then flows out of the drain 10.

Optionally, in one embodiment of the present application, as shown in fig. 2 and 3, the well region 3, the source region 4 and the first drift region 2 all extend along a second direction Y, which is parallel to the plane of the SiC substrate 1 and perpendicular to the first direction X;

as shown in fig. 3, the well region 3 is further provided with a plurality of source contact regions 12 arranged at intervals along the second direction Y, the source contact regions 12 penetrate through the source region 4 and the well region 3, the source contact regions 12 are doped with the second type, the doping concentration of the source contact regions 12 is greater than that of the well region 3, and the source contact regions 12 and the source electrode 9 form ohmic contact.

As is known from the foregoing, the source 9 and the well region 3 are electrically connected to transmit the electric potential of the source 9 to the surface of the well region 3 facing away from the SiC substrate 1 and covered by the gate oxide 6 and the gate 7, so that when the gate 7 is biased accordingly, the surface of the well region 3 covered by the gate oxide 6 and the gate 7 facing away from the SiC substrate 1 forms an inverted channel region, and in this example, the well region 3, the source region 4 and the first drift region 2 all extend along the second direction Y, so that a plurality of source contact regions 12 are provided in the well region 3, which are arranged at intervals along the second direction Y, and since the source contact regions 12 penetrate the source region 4 and the well region 3 and the source contact regions 12 and the well region 3 are both doped with the second type, the doping concentration of the source contact regions 12 is greater than that of the well region 3, so that the source contact regions 12 form ohmic contacts with the source 9, and thus the electric potential of the source 9 can be transmitted to the surface of the well region 3 facing away from the SiC substrate 1 and covered by the gate oxide 6 and the gate 7 through the highly doped source contact regions 12, so that the transmission performance of the electric potential of the well region 9 to the surface of the well region 3 facing away from the SiC substrate 6 and the gate oxide 7 is improved.

Alternatively, in one embodiment of the present application, as shown in fig. 3, the inversion implantation region 5 extends in the second direction Y;

a common contact region 13 is arranged on at least one side of the first drift region 2 along the second direction, the common contact region 13 is doped with the second type, and the common contact region 13 forms ohmic contact with the source electrode 9, so that each inversion implantation region 5 is electrically connected with the source electrode 9 through the common contact region 13.

From the foregoing, it is known that the adjacent two inversion implantation regions 5 and the drift region between the adjacent two inversion implantation regions 5 constitute JFET regions, i.e. back-to-back reverse-biased PN junctions, and the drift region between the adjacent two inversion implantation regions 5 is electrically connected to the drain 10, so, in order to provide a potential to each inversion implantation region 5, in this embodiment, a common contact region 13 is provided on at least one side of the first drift region 2 along the second direction Y, the common contact region 13 and the inversion implantation regions 5 are both doped with the second type, and the common contact region 13 forms an ohmic contact with the source 9, in particular, fig. 9 shows a schematic cross-sectional view of AA' in fig. 3, at this time, each inversion implantation region 5 is electrically connected to the source 9 through the common contact region 13, so that the potential of the source 9 is provided to each inversion implantation region 5, so that the adjacent two inversion implantation regions 5 and the drift region between the adjacent two inversion implantation regions 5 constitute regions, and the SiC device is compact in structure.

Of course, alternatively, in other embodiments of the present application, the electric potential may be provided to each inversion implantation region 5 by providing an additional electrode or the like, as the case may be.

The embodiment of the application also provides a preparation method of the SiC MOSFET device, which comprises the following steps:

s10: as shown in fig. 10 (a), a SiC substrate 1 is provided, an epitaxial layer is formed on one side of the SiC substrate 1, and the SiC substrate 1 and the epitaxial layer are both doped with a first type; wherein the epitaxial layer is a SiC epitaxial layer.

S20: as shown in fig. 10 (a), a first type ion implantation is performed on the epitaxial layer, so that at least part of the epitaxial layer forms a first drift region 2; at this time, the first drift region 2 is also doped with the first type, and the doping concentration of the first drift region 2 is greater than that of the original epitaxial layer.

Optionally, in step S20, after the first type ion implantation is performed on the epitaxial layer, a second drift region 11 is still remained between the first drift region 2 and the SiC substrate 1, where the doping concentrations of the second drift region 11 and the original epitaxial layer are the same.

Specifically, taking an N-channel MOSFET device as an example, the first type doping is N-type doping, the first type ion implantation is N-type ion implantation, and the SiC substrate 1 is N ⁺ Doped, the second drift region 11 is N ^- The first drift region 2 is doped N.

S30: as shown in fig. 10 (b), the first drift region 2 is subjected to the second type ion implantation by using the first preset mask 14, and a plurality of inversion implantation regions 5 are formed in the first drift region 2 at intervals along a first direction X, which is parallel to the plane of the SiC substrate 1.

In step S30, the first preset mask 14 may be used to block the region of the first drift region 2 where ion implantation is not required, so as to perform second type ion implantation on the region of the first drift region 2 where ion implantation is required, and a plurality of inversion implantation regions 5 are formed in the first drift region 2 at intervals along the first direction X.

Specifically, taking an N-channel MOSFET device as an example, since the first drift region 2 is N-doped, the second type ion implantation is P-type ion implantation, i.e., the inversion implantation region 5 is P-doped.

S40: as shown in fig. 10 (c), by using a second preset mask 15, a second type ion implantation is performed on a side of the first drift region 2, where the side of the second type ion implantation region 5 is away from the SiC substrate 1, to form well regions 3, and the well regions 3 are arranged at intervals along the first direction X, so that the first drift region 2 includes a first region 2a interposed between two adjacent well regions 3, and a second region 2b located on the first region 2a and the side of the well region 3, where the second region 2b is near the SiC substrate 1, where the second region 2b is provided with the second type ion implantation region 5.

In step S40, the second preset mask 15 may be used to block the region of the first drift region 2 where ion implantation is not required, and perform second type ion implantation in the region of the first drift region 2 where well regions 3 are required to be formed, so as to form well regions 3 arranged at intervals along the first direction X.

Specifically, taking an N-channel MOSFET device as an example, since the first drift region 2 is N-doped, a P-type ion implantation is performed on a side of the partial inversion implantation region 5 facing away from the SiC substrate 1 in the first drift region 2 to form a P-doped well region 3.

Alternatively, in the previous step S30, the implantation depth of the inversion implantation region 5 may be controlled such that the first drift region 2 may further include a third region 2c located between the inversion implantation region 5 and the second drift region 11 to serve as a current spreading layer.

S50: as shown in fig. 10 (d), the well region 3 is subjected to the first type ion implantation by using the third preset mask plate 16, and the source region 4 is formed in the well region 3.

In step S50, a third preset mask 16 may be used to block a portion of the well region 3 and the region of the first drift region 2 where ion implantation is not required, and perform the first type ion implantation in the region of the well region 3 where the source region 4 is required to be formed, so as to form the source region 4 in the well region 3.

Specifically, taking an N-channel MOSFET device as an example, since the well region 3 is P-doped, N-type ion implantation is performed on the well region 3, thereby forming N in the well region 3 ⁺ Source region 4.

Optionally, on the basis of step S50, the method further includes:

s51: as shown in fig. 10 (e), the source region 4 and the well region 3 are subjected to the second type ion implantation by using the fourth preset mask 17 to form a source contact region 12, the source contact region 12 penetrates through the source region 4 and the well region 3, and the doping concentration of the source contact region 12 is greater than that of the well region 3.

In step S51, the fourth preset mask 17 may be used to block the well region 3, part of the source region 4, and the region of the first drift region 2 where the ion implantation is not required, and perform the second ion implantation on the source region 4 and the well region 3 to form the source contact region 12, so that the source contact region 12 penetrates through the source region 4 and the well region 3.

Specifically, taking an N-channel MOSFET device as an example, since the well region 3 is P-doped, the source region 4 is N ⁺ In step S51, the source region 4 and the well region 3 are doped with P-type ions to form P ⁺⁺ Doped source contact region 12.

Note that, as shown in fig. 3, since the well region 3, the source region 4, and the first drift region 2 all extend in the second direction Y, which is parallel to the plane of the SiC substrate 1 and perpendicular to the first direction X, the plurality of source contact regions 12 of the well region 3 are arranged at intervals in the second direction Y.

S60: as shown in fig. 10 (f), a gate oxide layer 6 and a gate electrode 7 are sequentially formed on the well region 3 and the first region 2a on the side facing away from the SiC substrate 1.

Specifically, in step S60, at least a portion of the source region 4 and the source contact region 12 may be blocked by using the fifth preset mask 18, so that the gate oxide layer 6 and the gate electrode 7 are sequentially deposited on the well region 3 and the first region 2a on a side facing away from the SiC substrate 1.

Optionally, the gate 7 is a polysilicon gate.

S70: as shown in fig. 10 (g), an isolation dielectric layer 8 is formed, and the isolation dielectric layer 8 has a through-hole therethrough exposing the source region 4 and exposing the source contact region 12.

Specifically, in step S70, the isolation dielectric layer 8 may be deposited on the entire surface, and then the entire isolation dielectric layer 8 is etched, so that the isolation dielectric layer 8 has a through hole, and the through hole exposes the source region 4 and exposes the source contact region 12.

Alternatively, the gate oxide layer 6 and the isolation dielectric layer 8 may be SiO ₂ A layer.

S80: as shown in fig. 10 (h), the source electrode 9 is formed, the source electrode 9 forms ohmic contact with the source region 1 through the via hole, and the source electrode 9 forms ohmic contact with the source contact region 12 through the via hole.

S90: as shown in fig. 10 (i), a drain electrode 10 is formed on the SiC substrate 1 side facing away from the first drift region 2.

Referring to fig. 3, the inversion implantation regions 5 extend along the second direction Y, and since two adjacent inversion implantation regions 5 and a drift region between the two adjacent inversion implantation regions 5 form JFET regions, that is, form back-to-back reverse-biased PN junctions, and the drift region between the two adjacent inversion implantation regions 5 is electrically connected to the drain 10, in order to provide a potential to each inversion implantation region 5, optionally, in one embodiment of the present application, a common contact region 13 is provided on at least one side of the first drift region 2 along the second direction Y, the common contact region 13 and the inversion implantation regions 5 are both doped with the second type, and the common contact region 13 forms an ohmic contact with the source 9, so that each inversion implantation region 5 is electrically connected to the source 9 through the common contact region 13.

Alternatively, in step S30, the second type ion implantation may be performed on at least one side of the first drift region 2 in the second direction Y, while the second type ion implantation is performed on the first type drift region 2 to form the inversion implantation region 5, to form the common contact region 13. Alternatively, the common contact region 13 may also be formed by performing a second type ion implantation on at least one side of the first drift region 2 in the second direction Y before forming the source electrode 9. As the case may be.

Specifically, taking an N-channel MOSFET device as an example, the common contact region 13 may be P ⁺⁺ Doping.

Since the structures of the parts of the SiC MOSFET device prepared by the preparation method provided in the embodiments of the present application are described in detail in the foregoing embodiments, the details are not repeated here.

In the description, each part is described in a parallel and progressive mode, and each part is mainly described as a difference with other parts, and all parts are identical and similar to each other.

The features described in the various embodiments of the present disclosure may be interchanged or combined with one another in the description to enable those skilled in the art to make or use the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SiC MOSFET device, comprising:

a SiC substrate;

2. The SiC MOSFET device of claim 1, wherein a spacing between any adjacent two of said inversion implantation regions is equal in said first direction.

3. The SiC MOSFET device of claim 1, wherein a surface of the well region facing away from the SiC substrate is a channel region;

4. The SiC MOSFET device of claim 1, wherein a doping concentration of the inversion implant region is greater than a doping concentration of the well region.

5. The SiC MOSFET device of claim 4, wherein the inversion implant region has a doping concentration ranging from 1 x 10 ¹⁷ cm ^-3 -1×10 ²² cm ^-3 Including endpoint values.

6. The SiC MOSFET device of claim 1, further comprising:

7. The SiC MOSFET device of claim 6, wherein the first drift region further comprises a third region located between the inversion implant region and the second drift region.

8. The SiC MOSFET device of claim 1, wherein the well region, the source region, and the first drift region each extend along a second direction that is parallel to a plane of the SiC substrate and perpendicular to the first direction;

9. The SiC MOSFET device of claim 8, wherein the inversion implant region extends in the second direction;

10. A method of fabricating a SiC MOSFET device comprising: