CN116344447A - Method for manufacturing semiconductor device and chip - Google Patents

Method for manufacturing semiconductor device and chip Download PDF

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Publication number
CN116344447A
CN116344447A CN202310465648.5A CN202310465648A CN116344447A CN 116344447 A CN116344447 A CN 116344447A CN 202310465648 A CN202310465648 A CN 202310465648A CN 116344447 A CN116344447 A CN 116344447A
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China
Prior art keywords
region
scribe line
width
test structure
exposure
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CN202310465648.5A
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Chinese (zh)
Inventor
丁一凡
梁成栋
何亮亮
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Priority to CN202310465648.5A priority Critical patent/CN116344447A/en
Publication of CN116344447A publication Critical patent/CN116344447A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)

Abstract

The invention provides a method for manufacturing a semiconductor device and a chip, wherein the semiconductor device comprises the following steps: a wafer having a plurality of exposure areas and a first scribe line region connecting adjacent ones of the exposure areas, the exposure areas having a plurality of chip areas and a second scribe line region connecting adjacent ones of the chip areas; a plurality of test structures are located at corners and centers of the first scribe line region and/or the exposure region. The technical scheme of the invention can effectively improve the quantity of chips formed by cutting each wafer and simultaneously ensure the quality of the chips, thereby improving the market competitiveness of the produced chips.

Description

Method for manufacturing semiconductor device and chip
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device and a chip.
Background
With the continuous development of semiconductor technology, the chip size is also continuously shrinking, however, in the process production, when the chip size is 14 nm or less, the cost of the process production is greatly increased. Therefore, under the condition of the prior art, the production cost is reduced by different modes, so that the market competitiveness is improved to be a new development trend.
In the prior art, as shown in fig. 1, a dicing street 11 of 80 microns or 60 microns is generally used in a wafer, and a plurality of test structures 12 are disposed in the dicing street 11, wherein the test structures 12 are used for detecting performance parameters of the wafer during the process, so as to ensure the stability of the wafer during the process. And after the process production of the wafer is completed, the wafer is cut into chips 13 of uniform size along the dicing streets 11 using a diamond blade. However, for the small chip 13, the excessive width of the scribe line 11 may result in waste of the wafer area; when the width of the scribe line 11 is reduced to less than 50 micrometers, the conventional width of the test structure 12 is about 50 micrometers, so that the test structure 12 cannot be placed in the scribe line 11. And since the width of the dicing street 11 becomes small, the stress generated when dicing the wafer with the diamond blade will have a certain quality impact on the chips 13 formed by dicing.
Therefore, how to effectively improve the number of chips formed by dicing each wafer and also ensure the quality of the chips, so as to improve the market competitiveness of the produced chips is a problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method of chips, which can effectively improve the number of chips cut by each wafer and ensure the quality of the chips, thereby improving the market competitiveness of the produced chips.
In order to solve the above technical problems, the present invention provides a semiconductor device, comprising:
a wafer having a plurality of exposure areas and a first scribe line region connecting adjacent ones of the exposure areas, the exposure areas having a plurality of chip areas and a second scribe line region connecting adjacent ones of the chip areas;
a plurality of test structures are located at corners and centers of the first scribe line region and/or the exposure region.
Preferably, when the width of the first scribe line region is greater than the width of the test structure and the width of the test structure is greater than the width of the second scribe line region, the test structure is located in the first scribe line region; when the width of the first cutting channel region is equal to that of the second cutting channel region and the width of the test structure is larger than that of the second cutting channel region, the test structure is positioned at the corner and the center of the exposure region, or the test structure is positioned at the corner and the center of the exposure region and the test structure positioned at the corner of the exposure region also extends to the first cutting channel region.
Preferably, the test structures have a width of 49 to 51 microns.
Preferably, when the width of the first scribe line region is greater than the width of the test structure and the width of the test structure is greater than the width of the second scribe line region, the width of the first scribe line region is 60 micrometers to 80 micrometers and the width of the second scribe line region is 19 micrometers to 20 micrometers; and when the width of the first cutting channel region is equal to that of the second cutting channel region and the width of the test structure is larger than that of the second cutting channel region, the widths of the first cutting channel region and the second cutting channel region are 19-20 micrometers.
Preferably, the test structure is located in the first scribe line region, and the test structure surrounds the exposure region.
Preferably, the number of the exposure areas is 60 to 70.
Preferably, the number of the test structures at the corners and the center of the first scribe line region located at the periphery of the single exposure region and/or the single exposure region is 70 to 80.
The invention also provides a manufacturing method of the chip, which comprises the following steps:
providing the semiconductor device;
and cutting the first cutting channel region and the second cutting channel region of the wafer to obtain chips.
Preferably, the wafer comprises a substrate and a passivation layer formed on the substrate, wherein a metal interconnection structure is formed in the passivation layer.
Preferably, the step of dicing the first dicing street region and the second dicing street region of the wafer comprises:
cutting a passivation layer on the metal interconnection structure of the first cutting channel region and the second cutting channel region and a top metal layer in the metal interconnection structure by adopting a dry etching process;
and cutting the passivation layer, the rest metal interconnection structure and the substrate which are remained in the first cutting channel region and the second cutting channel region by adopting laser.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. a semiconductor device of the present invention includes: a wafer having a plurality of exposure areas and a first scribe line region connecting adjacent ones of the exposure areas, the exposure areas having a plurality of chip areas and a second scribe line region connecting adjacent ones of the chip areas; the plurality of test structures are positioned at the corners and the centers of the first cutting channel area and/or the exposure area, so that the quantity of chips formed by cutting each wafer can be effectively improved, the quality of the chips can be ensured, and the market competitiveness of the produced chips is improved.
2. The manufacturing method of the chip of the invention comprises the following steps: providing the semiconductor device; and the first cutting channel area and the second cutting channel area of the wafer are cut to obtain chips, so that the quantity of the chips formed by cutting each wafer can be effectively improved, the quality of the chips can be ensured, and the market competitiveness of the produced chips is improved.
Drawings
FIG. 1 is a schematic illustration of a dicing lane and test structure arrangement;
FIG. 2 is a schematic diagram showing a distribution of test structures according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing the distribution of a test structure according to another embodiment of the present invention;
fig. 4 is a schematic structural view of a semiconductor device according to an embodiment of the present invention;
fig. 5 is a flowchart of a method of manufacturing a chip according to an embodiment of the present invention.
Wherein, the reference numerals of fig. 1 to 5 are as follows:
11-cutting lanes; 12-test structure; 13-chip; 21-wafer; 22-a first scribe line region; 23-a second scribe line region; 24-exposing area; 241-chip area; 25-test structure.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the following more particular description of the semiconductor device and method of manufacturing a chip according to the present invention will be presented in conjunction with the accompanying drawings and detailed description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
An embodiment of the present invention provides a semiconductor device including: a wafer having a plurality of exposure areas and a first scribe line region connecting adjacent ones of the exposure areas, the exposure areas having a plurality of chip areas and a second scribe line region connecting adjacent ones of the chip areas; a plurality of test structures are located at corners and centers of the first scribe line region and/or the exposure region.
The semiconductor device provided by the present invention will be described in detail with reference to fig. 2 to 4.
The semiconductor device comprises a wafer 21 and a plurality of test structures 25, wherein the test structures 25 are used for detecting performance parameters of the wafer 21 in the process, so as to ensure the stability of the wafer 21 in the process.
The wafer 21 has a plurality of exposure areas 24 and a first scribe line area 22 connecting adjacent ones of the exposure areas 24, the first scribe line area 22 dividing the wafer 21 into a plurality of divided exposure areas 24; the exposure area 24 has a plurality of chip areas 241 and a second scribe line area 23 connecting adjacent chip areas 241, and the second scribe line area 23 divides each exposure area 24 into a plurality of divided chip areas 241, so that after the wafer 21 is finished in the manufacturing process, chips are conveniently obtained by dicing the wafer 21 along the first scribe line area 22 and the second scribe line area 23.
The test structures 25 may be located at corners and centers of the first scribe line region 22 or the exposure region 24, or the test structures 25 may be located at corners and centers of both the first scribe line region 22 and the exposure region 24.
Also, when the test structure 25 is located at the corner and center of the exposure region 24, the test structure 25 may be located only in a chip region 241 in the exposure region 24 (as in the chip region 241 in which the test structure 25 is located at the center of the exposure region 24 shown in fig. 3), or the test structure 25 may be located in both the chip region 241 and the second scribe line region 23 in the exposure region 24 (as in the chip region 241 and the second scribe line region 23 in which the test structure 25 is located at the corner of the exposure region 24 shown in fig. 3).
When the test structure 25 is located in the first scribe line region 22, as shown in fig. 2, it is preferable that the test structure 25 surrounds the exposure region 24, so that the chip region 241 in the exposure region 24 can be surrounded by the test structure 25, thereby enabling the test structure 25 to stably detect the performance parameters of the wafer 21 while the wafer 21 is being processed.
When the test structures 25 are located at the corners and the center of the exposure area 24, the structure of the test structures 25 may be adjusted such that the test structures 25 are stacked at the corners and the center of the exposure area 24 in a direction perpendicular to the front surface of the wafer 21, thereby reducing the area occupied by the test structures 25 on the wafer 21.
Wherein when the width of the first scribe line region 22 is greater than the width of the test structure 25 and the width of the test structure 25 is greater than the width of the second scribe line region 23, the test structure 25 is located in the first scribe line region 22, and the width of the first scribe line region 22 is such that it accommodates the test structure 25, thereby enabling the test structure 25 to be located completely within the first scribe line region 22, avoiding occupying the area of the exposure region 24; in addition, the width of the second scribe line region 23 is small enough to separate more chip regions 241 from the exposure region 24, so that more chips with the same quality can be obtained when the wafer 21 is diced after the wafer 21 is subjected to the process.
When the width of the first scribe line region 22 is equal to the width of the second scribe line region 23 and the width of the test structure 25 is greater than the width of the second scribe line region 23 (i.e., greater than the width of the first scribe line region 22), the test structure 25 may be located at the corners and center of the exposure region 24 due to the fact that the width of the first scribe line region 22 does not accommodate the test structure 25, or the test structure 25 may be located at the corners and center of the exposure region 24 and the test structure 25 located at the corners of the exposure region 24 may also extend to the first scribe line region 22 at the periphery of the exposure region 24 such that all or most of the test structure 25 may be located within a single exposure region 24 and that the test structure 25 may occupy only the corners and center of the exposure region 24 due to the fact that the test structure 25 is stacked in a direction perpendicular to the front of the wafer 21 such that the test structure 25 may also cause a small area loss of the test structure 24 to the normal performance of the wafer 24 can be performed with the test structure; moreover, the widths of the first scribe line region 22 and the second scribe line region 23 are small enough to separate more chip regions 241 from the whole wafer 21, so that more chips with the same quality can be obtained when the wafer 21 is diced after the wafer 21 is subjected to the process.
Preferably, the test structures 25 have a width in the range of 49 micrometers to 51 micrometers.
As shown in fig. 2, when the width of the first scribe line region 22 is greater than the width of the test structure 25 and the width of the test structure 25 is greater than the width of the second scribe line region 23, the width of the first scribe line region 22 is preferably in the range of 60 micrometers to 80 micrometers and the width of the second scribe line region 23 is preferably in the range of 19 micrometers to 20 micrometers. It should be noted that the width of the first scribe line region 22 is not limited to the above-mentioned range, and in other embodiments, the width of the test structure 25 and the position of the test structure 25 may be adjusted.
As shown in fig. 3, when the width of the first scribe line region 22 is equal to the width of the second scribe line region 23 and the width of the test structure 25 is greater than the width of the second scribe line region 23, the width of each of the first scribe line region 22 and the second scribe line region 23 is preferably in the range of 19 micrometers to 20 micrometers.
Preferably, the number of the exposure areas 24 is 60 to 70, and the number of the first scribe line areas 22 located at the periphery of the single exposure area 24 and/or the test structures 25 at the corners and the center of the single exposure area 24 is 70 to 80. It should be noted that the number of the exposure regions 24 and the test structures 25 is not limited to the above description, and in other embodiments, the number may be adjusted according to the actual sizes of the wafer 21, the test structures 25 and the chip regions 241.
In one embodiment, the diameter of the wafer 21 is 300 mm, the length of the exposure area 24 is 30 mm, the width is 23 mm, the width of the test structure 25 is 50 micrometers, and the length is 1300 micrometers, and by arranging the test structure 25 according to the structure of the exposure area 24 in fig. 2 for the wafer 21, and using 60 micrometers of the first scribe line area 22 and 19.8 micrometers of the second scribe line area 23, the number of chips that can be obtained by the wafer 21 is increased by 15.9% compared with the number of chips obtained by using conventional 60 micrometer scribe lines; by arranging the test structures 25 on the wafer 21 according to the structure of the exposure area 24 in fig. 3, and using the first scribe line area 22 of 19.8 microns and the second scribe line area 23 of 19.8 microns, the number of chips obtained by the wafer 21 is increased by 17.2% compared with the number of chips obtained by using the conventional scribe line of 60 microns, and the quality of chips can be ensured while the number of chips formed by dicing per wafer is improved, thereby effectively improving the market competitiveness of the produced chips. It should be noted that the size of the exposure area 24 and the number of chips are not limited to the above description, and in other embodiments, the size may be adjusted according to the actual sizes of the wafer 21 and the chips.
In summary, the semiconductor device provided by the present invention includes: a wafer having a plurality of exposure areas and a first scribe line region connecting adjacent ones of the exposure areas, the exposure areas having a plurality of chip areas and a second scribe line region connecting adjacent ones of the chip areas; the plurality of test structures are positioned at the corners and the centers of the first cutting channel area and/or the exposure area, so that the quantity of chips formed by cutting each wafer can be effectively improved, the quality of the chips can be ensured, and the market competitiveness of the produced chips is improved.
An embodiment of the present invention further provides a method for manufacturing a chip, referring to fig. 5, where the method for manufacturing a chip includes:
step S1, providing the semiconductor device;
and S2, cutting the first cutting channel region and the second cutting channel region of the wafer to obtain chips.
The method for manufacturing the chip provided in this embodiment will be described in detail.
According to step S1, the semiconductor device is provided, and the description of the semiconductor device is referred to above, and will not be repeated here.
According to step S2, the first scribe line region 22 and the second scribe line region 23 of the wafer 21 are diced to obtain chips.
Preferably, the wafer 21 includes a substrate and a passivation layer formed on the substrate, wherein a metal interconnection structure is formed in the passivation layer. The passivation layer can comprise a plurality of stacked insulating layers, and the material of the passivation layer can comprise nitride and polyethylene oxide; the metal interconnection structure can comprise a plurality of metal layers, the metal layers are electrically connected through conductive plugs, and the material of the metal interconnection structure can comprise metals such as copper, tungsten and metal nitrides.
Preferably, the step of dicing the first dicing street region 22 and the second dicing street region 23 of the wafer 21 includes: firstly, cutting passivation layers on the metal interconnection structures of the first cutting channel region 22 and the second cutting channel region 23 and top metal layers in the metal interconnection structures by adopting a dry etching process; then, the passivation layer, the remaining metal interconnection structure, and the substrate remaining in the first and second scribe line regions 22 and 23 are cut using a laser.
The widths of the first scribe line region 22 and the second scribe line region 23 in the semiconductor device of the present invention are much reduced compared with the widths of scribe lines in the conventional semiconductor device, and if the first scribe line region 22 and the second scribe line region 23 are continuously cut by diamond, chips formed by dicing are damaged, and the quality of the chips is affected.
In summary, the method for manufacturing a chip provided by the present invention includes: providing the semiconductor device; and the first cutting channel area and the second cutting channel area of the wafer are cut to obtain chips, so that the quantity of the chips formed by cutting each wafer can be effectively improved, the quality of the chips can be ensured, and the market competitiveness of the produced chips is improved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a wafer having a plurality of exposure areas and a first scribe line region connecting adjacent ones of the exposure areas, the exposure areas having a plurality of chip areas and a second scribe line region connecting adjacent ones of the chip areas;
a plurality of test structures are located at corners and centers of the first scribe line region and/or the exposure region.
2. The semiconductor device of claim 1, wherein the test structure is located in the first scribe line region when the width of the first scribe line region is greater than the width of the test structure and the width of the test structure is greater than the width of the second scribe line region; when the width of the first cutting channel region is equal to that of the second cutting channel region and the width of the test structure is larger than that of the second cutting channel region, the test structure is positioned at the corner and the center of the exposure region, or the test structure is positioned at the corner and the center of the exposure region and the test structure positioned at the corner of the exposure region also extends to the first cutting channel region.
3. The semiconductor device of claim 2, wherein the test structure has a width of 49 microns to 51 microns.
4. The semiconductor device of claim 3, wherein the width of the first scribe line region is greater than the width of the test structure, and the width of the test structure is greater than the width of the second scribe line region, the width of the first scribe line region is between 60 microns and 80 microns, and the width of the second scribe line region is between 19 microns and 20 microns; and when the width of the first cutting channel region is equal to that of the second cutting channel region and the width of the test structure is larger than that of the second cutting channel region, the widths of the first cutting channel region and the second cutting channel region are 19-20 micrometers.
5. The semiconductor device of claim 1, wherein the test structure is located in the first scribe line region, the test structure surrounding the exposed region.
6. The semiconductor device according to claim 1, wherein the number of the exposure regions is 60 to 70.
7. The semiconductor device according to claim 1, wherein the number of the test structures at the first scribe line region located at the periphery of the single exposure region and/or the corners and the center of the single exposure region is 70 to 80.
8. A method of manufacturing a chip, comprising:
providing a semiconductor device according to any one of claims 1 to 7;
and cutting the first cutting channel region and the second cutting channel region of the wafer to obtain chips.
9. The method of manufacturing a chip of claim 8, wherein the wafer comprises a substrate and a passivation layer formed on the substrate, the passivation layer having a metal interconnect structure formed therein.
10. The method of manufacturing a chip of claim 9, wherein the step of dicing the first scribe line region and the second scribe line region of the wafer comprises:
cutting a passivation layer on the metal interconnection structure of the first cutting channel region and the second cutting channel region and a top metal layer in the metal interconnection structure by adopting a dry etching process;
and cutting the passivation layer, the rest metal interconnection structure and the substrate which are remained in the first cutting channel region and the second cutting channel region by adopting laser.
CN202310465648.5A 2023-04-26 2023-04-26 Method for manufacturing semiconductor device and chip Pending CN116344447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310465648.5A CN116344447A (en) 2023-04-26 2023-04-26 Method for manufacturing semiconductor device and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310465648.5A CN116344447A (en) 2023-04-26 2023-04-26 Method for manufacturing semiconductor device and chip

Publications (1)

Publication Number Publication Date
CN116344447A true CN116344447A (en) 2023-06-27

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Family Applications (1)

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CN202310465648.5A Pending CN116344447A (en) 2023-04-26 2023-04-26 Method for manufacturing semiconductor device and chip

Country Status (1)

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