CN116344337B - Method for processing back of compound semiconductor wafer - Google Patents
Method for processing back of compound semiconductor wafer Download PDFInfo
- Publication number
- CN116344337B CN116344337B CN202310622486.1A CN202310622486A CN116344337B CN 116344337 B CN116344337 B CN 116344337B CN 202310622486 A CN202310622486 A CN 202310622486A CN 116344337 B CN116344337 B CN 116344337B
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- bonding adhesive
- bonding
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 50
- 150000001875 compounds Chemical class 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 82
- 239000000853 adhesive Substances 0.000 claims abstract description 81
- 230000001070 adhesive effect Effects 0.000 claims abstract description 81
- 238000002844 melting Methods 0.000 claims abstract description 35
- 230000008018 melting Effects 0.000 claims abstract description 33
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 26
- 239000010980 sapphire Substances 0.000 claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims abstract description 17
- 238000000576 coating method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 7
- 239000003960 organic solvent Substances 0.000 claims abstract description 6
- 239000012790 adhesive layer Substances 0.000 claims abstract description 4
- 238000001816 cooling Methods 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 239000007788 liquid Substances 0.000 claims description 17
- 239000001993 wax Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- NQBXSWAWVZHKBZ-UHFFFAOYSA-N 2-butoxyethyl acetate Chemical compound CCCCOCCOC(C)=O NQBXSWAWVZHKBZ-UHFFFAOYSA-N 0.000 claims description 3
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- LLHKCFNBLRBOGN-UHFFFAOYSA-N propylene glycol methyl ether acetate Chemical compound COCC(C)OC(C)=O LLHKCFNBLRBOGN-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000003292 glue Substances 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 208000025962 Crush injury Diseases 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a method for processing the back of a compound semiconductor wafer, which comprises the following steps: coating a first layer of bonding adhesive with high melting point on the front surface of the wafer, completely covering the structural device as a device protection layer, coating a second layer of bonding adhesive with melting point lower than that of the first layer on the device protection layer, wherein the melting point of the first layer of bonding adhesive is higher than that of the second layer of bonding adhesive by more than 10 ℃, and the coating thickness of the second layer of bonding adhesive is more than 5 microns; heating to soften the second bonding adhesive layer to a melting point, pressurizing to bond the wafer and the sapphire carrier, and cooling to bond the wafer and the sapphire carrier together; thinning the wafer substrate by grinding with a grinding wheel; and (3) softening the second layer of bonding adhesive by heating, unloading the sapphire carrier from the thinned wafer, and cleaning the first layer of bonding adhesive and the second layer of bonding adhesive remained on the front surface of the wafer by using an organic solvent. The invention can ensure that the structural device is not damaged by crush in the bonding and unbinding process.
Description
Technical Field
The invention relates to the field of compound semiconductor manufacturing, in particular to a method for processing the back of a compound semiconductor wafer.
Background
The compound semiconductor fabrication process includes a wafer front side process and an immediately subsequent wafer back side process. In the wafer front side process, the copper pillar process is widely used because the copper pillar has good heat dissipation and conductivity properties, low resistance/inductance properties, low thermal resistance, better electromigration resistance and finer line spacing. In addition, in order to reduce the parasitic capacitance between metals, the connection line of the air bridge structure is also widely used in the wafer front side process. Therefore, structural devices such as copper pillars or air bridges are sometimes provided at the completion of the wafer front side process.
The back surface technology of the compound semiconductor wafer is carried out after heating bonding by using sapphire and the like as carriers and liquid wax or bonding glue and the like, and the wafer and the sapphire carriers are separated to finish the debonding after the back surface technology of the wafer is finished. As a prior art, CN103050480a discloses a process method for back patterning of a silicon wafer, and CN115172146a discloses a method for manufacturing a compound semiconductor wafer. However, in the prior art, during the bonding and debonding process, the parts of the structural devices such as copper pillars, air bridges, etc. may be damaged by the uncovered protective layer or the underlying unsupported parts of the devices.
Disclosure of Invention
The invention aims to provide a compound semiconductor wafer back surface process which can ensure that a structural device is not damaged by crush in the bonding and de-bonding processes.
One aspect of the present invention provides a method for processing a back surface of a compound semiconductor wafer, comprising:
and (3) a bonding adhesive coating step: coating a first layer of bonding adhesive with high melting point on the front surface of the wafer, completely covering the structural device as a device protection layer, coating a second layer of bonding adhesive with melting point lower than that of the first layer on the device protection layer, wherein the melting point of the first layer of bonding adhesive is higher than that of the second layer of bonding adhesive by more than 10 ℃, and the coating thickness of the second layer of bonding adhesive is more than 5 microns;
and a bonding step: heating to soften the second bonding adhesive layer to a melting point, pressurizing to bond the wafer and the sapphire carrier, and cooling to bond the wafer and the sapphire carrier together;
thinning: thinning the wafer substrate by grinding with a grinding wheel;
and (3) a step of de-bonding: and (3) softening the second layer of bonding adhesive by heating, unloading the sapphire carrier from the thinned wafer, and cleaning the first layer of bonding adhesive and the second layer of bonding adhesive remained on the front surface of the wafer by using an organic solvent.
Preferably, the first layer of bonding adhesive and the second layer of bonding adhesive are liquid wax or bonding adhesive, the liquid wax is ethylene glycol butyl ether acetate mixture, and the bonding adhesive is propylene glycol methyl ether acetate mixture.
Preferably, the melting point temperature of the first layer bonding adhesive and the second layer bonding adhesive is 100 to 200 ℃.
Preferably, the structural device is a copper pillar or an air bridge structure.
Preferably, the thickness of the copper column is 5-100 micrometers, and the thickness of the air bridge structure is 2-15 micrometers.
Preferably, the structural device is an air bridge structure, and the method further includes, after the thinning step and before the debonding step:
a back surface through hole forming step: and (3) coating photoresist on the back of the thinned wafer, opening the wafer substrate to expose the device power-on plate by using a photoetching mask plate and a position for forming a back through hole by developing, and cleaning the photoresist remained on the back of the wafer to form the back through hole of the wafer.
Preferably, the method further comprises:
a back metal deposition step: the bonding layer and the seed layer are deposited on the back of the wafer in a sputtering mode, and then gold is deposited on the back of the wafer and the through holes on the back by an electroplating mode and is interconnected with the device connecting electric disc of the through holes on the back to form wires.
Preferably, the material of the wafer substrate is gallium arsenide, silicon carbide, indium phosphide, sapphire, gallium nitride or lithium tantalate.
Preferably, in the thinning step, the wafer substrate is thinned to a thickness of 25 to 350 μm.
Preferably, the diameter of the sapphire carrier is 151-159 mm, and the thickness is 700-1500 microns.
According to the method for processing the back surface of the compound semiconductor wafer, which is disclosed by the invention, the structural device can be ensured not to be damaged by crush in the bonding and de-bonding processes.
Drawings
For a clearer description of the technical solutions of the present invention, the following description will be given with reference to the attached drawings used in the description of the embodiments of the present invention, it being obvious that the attached drawings in the following description are only some embodiments of the present invention, and that other attached drawings can be obtained by those skilled in the art without the need of inventive effort:
fig. 1 is a flowchart of a method for processing a back surface of a compound semiconductor wafer according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a method for processing the back surface of a compound semiconductor wafer. The front side of the compound semiconductor wafer (6 inch for example) is provided with structural devices such as copper pillars or air bridges, the total thickness of the wafer is about 500-800 micrometers (um) according to the substrate materials and the process, wherein the copper pillars have the structural thickness of about 5-100 micrometers and the air bridges have the structural thickness of about 2-15 micrometers according to the process requirements. The back processing method of the compound semiconductor wafer is applicable to the substrate materials such as gallium arsenide (GaAs), silicon carbide (SiC), indium phosphide (InP) and sapphire (Al) 2 O 3 ) Gallium nitride (GaN) or lithium tantalate (LiTaO) 3 ) Is a compound semiconductor wafer.
Fig. 1 is a flowchart of a method for processing a back surface of a compound semiconductor wafer according to an embodiment of the present invention. As shown in fig. 1, the method for processing the back surface of the compound semiconductor wafer according to the embodiment of the invention includes steps S1 to S4, wherein step S1 is a bonding adhesive coating step, step S2 is a bonding step, step S3 is a thinning step, and step S4 is a debonding step.
In the bonding adhesive coating step S1, two layers of bonding adhesives with different melting points are coated on the front surface of the wafer respectively, specifically, a first layer of bonding adhesive with a high melting point is coated on the front surface of the wafer, the structural device is completely covered to serve as a device protection layer, and a second layer of bonding adhesive with a melting point lower than that of the first layer is coated on the device protection layer.
In this step S1, the two layers of bonding glue may be liquid wax or bonding glue, wherein the liquid wax may be ethylene glycol butyl ether acetate mixture and the bonding glue may be propylene glycol methyl ether acetate mixture. The liquid wax and the bonding adhesive have different melting points according to different formulas, and the melting point temperature is about 100-200 ℃, so that the liquid wax and the bonding adhesive can be used as a first bonding adhesive and a second bonding adhesive with different melting points.
In this step S1, the first layer of bonding glue is to completely cover the structural device, such as a copper pillar or an air bridge structure, and the effect of protecting the structural device is achieved by requiring a complete coverage of the copper pillar structure with a thickness of about 5-100 micrometers and the air bridge structure with a thickness of about 2-15 micrometers.
In the step S1, the melting point of the first layer of bonding adhesive with a higher melting point is higher than that of the second layer of bonding adhesive with a lower melting point by more than 10 ℃, so that the effect of protecting the structural device cannot be achieved because the melting point of the first layer of bonding adhesive is close to that of the second layer of bonding adhesive in the subsequent bonding step and the debonding step, and the first layer of bonding adhesive is softened when the second layer of bonding adhesive is softened.
Because the first layer of bonding adhesive is required to completely cover the structural device, the thickness of the first layer of bonding adhesive is thicker, and the coating uniformity is relatively poorer, so that the thickness of the second layer of bonding adhesive is at least more than 5 micrometers, and the wafer is prevented from being separated from the sapphire carrier in the thinning step due to the fact that the uneven distribution of the second layer of bonding adhesive influences the adhesion effect after bonding in the subsequent bonding step.
In the bonding step S2, the second layer of bonding adhesive is heated to soften the second layer of bonding adhesive, and the wafer and the sapphire carrier are bonded together by pressing and then cooling.
In the prior art, devices such as copper columns or air bridges and the like are easy to be damaged by pressure injury due to softening of liquid wax or bonding adhesive and pressure bonding in the bonding process. In the method for processing the back surface of the compound semiconductor wafer according to the embodiment of the invention, two layers of bonding adhesives with different melting points are coated in the bonding adhesive coating step, the bonding between the wafer and the sapphire carrier is performed through the second layer of bonding adhesive with low melting point, and the first layer of bonding adhesive with high melting point is not softened, so that the structural devices on the compound semiconductor wafer are protected from being damaged during bonding or bonding release.
In this step S2, the sapphire carrier has a diameter of 151 to 159 mm and a thickness of 700 to 1500 μm.
In the thinning step S3, in order to obtain a better heat dissipation effect, a wafer substrate is thinned by utilizing a grinding wheel composed of diamond particles, and the thickness of the substrate is thinned to 25-350 microns according to the process requirement.
In one example, in the case where the structural device is an air bridge structure, the compound semiconductor wafer backside processing method according to the embodiment of the present invention further includes a backside via-hole forming step after the thinning step S3 and before the debonding step S4. The purpose of forming the back via is to enable the device to perform grounding and heat dissipation functions through the metal interconnect via the back via. In the case of the structural device being a copper pillar, the copper pillar can conduct out heat energy generated by the device through the front surface of the wafer, so that the substrate is only required to be thinned, and a back surface through hole is not required to be manufactured for heat dissipation of the device.
In the back through hole forming step, photoresist is coated on the back of the thinned wafer, and the substrate is opened to expose the device electric disc in a dry etching mode by utilizing the position of the photoetching mask plate for forming the back through hole through development. And (3) during photoresist removal, photoresist which is remained on the back of the wafer is cleaned by using a photoresist removing solution (NMP, N-methylpyrrolidone) or a photoresist remover at 80+/-5 ℃ to form a through hole on the back of the wafer.
In this example, the method of processing the back side of the compound semiconductor wafer according to the embodiment of the present invention may further include a back side metal deposition step.
In the back metal deposition step, an adhesive layer (titanium Ti, titanium tungsten TiW, nickel vanadium NiV and other metals) and a seed layer (gold Au) are deposited on the back of the wafer in a sputtering mode, and then gold with the diameter of 2.5-6 microns is deposited on the back of the wafer and the back through holes in an electroplating mode, and is interconnected with the device electric pads of the back through holes to form wires. The device can be used for grounding and heat dissipation by the back metal wire.
In the debonding step S4, the wafer needs to be unloaded from the sapphire carrier, and for this purpose, the second layer of bonding adhesive is heated to reach a melting point for softening, the sapphire carrier is unloaded from the thinned wafer, and the first layer of bonding adhesive and the second layer of bonding adhesive remained on the front surface of the wafer are cleaned by using an organic solvent.
In the step S4, after the second layer of bonding adhesive is softened by heating (100-200 ℃) to a melting point to reduce viscosity, the sapphire carrier is unloaded in a parallel manner, and then the residual bonding adhesive (liquid wax or bonding adhesive) on the front surface of the wafer is cleaned by using an organic solvent. Because the two layers of bonding adhesive are liquid wax or bonding adhesive with the same material, the two liquid waxes or bonding adhesives with different melting points can be cleaned simultaneously. As the organic solvent, acetone ACE, isopropyl alcohol IPA, etc. are generally used.
In the prior art, in the process of removing the sapphire carrier in a parallel manner after softening the liquid wax or bonding glue, devices such as copper columns or air bridges are easy to be damaged by crush injury due to the fact that the device part is not covered with a protective layer or no support is arranged below the device. In the method for processing the back surface of the compound semiconductor wafer, in the process of bonding, the second layer of bonding adhesive is heated to the melting point temperature of the second layer of bonding adhesive, so that the second layer of bonding adhesive is softened to unload the sapphire carrier from the thinned wafer, and at the moment, the first layer of bonding adhesive does not reach the melting point temperature yet, and the copper pillar structure or the air bridge structure can be protected from being damaged by crush injury in the bonding process.
And (4) finishing the back process of the compound semiconductor wafer after finishing the cleaning in the step (S4), subsequently performing a wafer cutting process, attaching the wafer with the front side facing upwards on a cutting adhesive tape for wafer cutting, and separating the wafer into a plurality of crystal grains by laser hidden cutting, laser full cutting, wheel knife cutting and other modes, and packaging the subsequent crystal grains.
In summary, the method for processing the back surface of the compound semiconductor wafer according to the embodiment of the invention has at least the following advantages:
1. the device on the compound semiconductor wafer is protected by using double-layer bonding adhesive (liquid wax or bonding adhesive), the first layer is coated with high-melting bonding adhesive to prevent the device from being damaged during bonding or unbinding, and the second layer is coated with low-melting bonding adhesive to attach and detach the wafer to and from the sapphire carrier.
2. In the cleaning after the de-bonding, two layers of liquid wax or bonding glue are made of the same material, so that the two liquid waxes or bonding glue with different melting points can be cleaned at the same time without adding a cleaning step.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that modifications may be made to the described embodiments in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive of the scope of the invention, which is defined by the appended claims.
Claims (10)
1. A method for processing a back surface of a compound semiconductor wafer, comprising:
and (3) a bonding adhesive coating step: coating a first layer of bonding adhesive with high melting point on the front surface of the wafer, completely covering the structural device as a device protection layer, coating a second layer of bonding adhesive with melting point lower than that of the first layer on the device protection layer, wherein the melting point of the first layer of bonding adhesive is higher than that of the second layer of bonding adhesive by more than 10 ℃, and the coating thickness of the second layer of bonding adhesive is more than 5 microns;
and a bonding step: heating to soften the second bonding adhesive layer to a melting point, pressurizing to bond the wafer and the sapphire carrier, and cooling to bond the wafer and the sapphire carrier together;
thinning: thinning the wafer substrate by grinding with a grinding wheel;
and (3) a step of de-bonding: and (3) softening the second layer of bonding adhesive by heating, unloading the sapphire carrier from the thinned wafer, and cleaning the first layer of bonding adhesive and the second layer of bonding adhesive remained on the front surface of the wafer by using an organic solvent.
2. The method of claim 1, wherein the first layer of bonding adhesive and the second layer of bonding adhesive are liquid waxes or bonding adhesives, the liquid waxes being ethylene glycol butyl ether acetate mixtures, the bonding adhesives being propylene glycol methyl ether acetate mixtures.
3. The method of claim 2, wherein the first layer of bonding adhesive and the second layer of bonding adhesive have melting temperatures of 100 to 200 ℃.
4. A method according to any one of claims 1 to 3, wherein the structural device is a copper pillar or an air bridge structure.
5. The method of claim 4, wherein the copper pillars have a thickness of 5 to 100 microns and the air bridge structure has a thickness of 2 to 15 microns.
6. A method according to any one of claims 1-3, wherein the structural device is an air bridge structure, the method further comprising, after the thinning step and before the debonding step:
a back surface through hole forming step: and (3) coating photoresist on the back of the thinned wafer, opening the wafer substrate to expose the device power-on plate by using a photoetching mask plate and a position for forming a back through hole by developing, and cleaning the photoresist remained on the back of the wafer to form the back through hole of the wafer.
7. The method as recited in claim 6, further comprising:
a back metal deposition step: the bonding layer and the seed layer are deposited on the back of the wafer in a sputtering mode, and then gold is deposited on the back of the wafer and the through holes on the back by an electroplating mode and is interconnected with the device connecting electric disc of the through holes on the back to form wires.
8. A method according to any of claims 1-3, wherein the material of the wafer substrate is gallium arsenide, silicon carbide, indium phosphide, sapphire, gallium nitride or lithium tantalate.
9. A method according to any one of claims 1-3, wherein in the thinning step the wafer substrate is thinned to a thickness of 25-350 microns.
10. A method according to any one of claims 1 to 3, wherein the sapphire carrier has a diameter of 151 to 159 mm and a thickness of 700 to 1500 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310622486.1A CN116344337B (en) | 2023-05-30 | 2023-05-30 | Method for processing back of compound semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310622486.1A CN116344337B (en) | 2023-05-30 | 2023-05-30 | Method for processing back of compound semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116344337A CN116344337A (en) | 2023-06-27 |
| CN116344337B true CN116344337B (en) | 2023-07-25 |
Family
ID=86880754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310622486.1A Active CN116344337B (en) | 2023-05-30 | 2023-05-30 | Method for processing back of compound semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116344337B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106611717A (en) * | 2015-10-22 | 2017-05-03 | 浙江中纳晶微电子科技有限公司 | Procedure of processing workpiece and apparatus designed for procedure |
| CN111326467A (en) * | 2019-10-16 | 2020-06-23 | 中国电子科技集团公司第五十五研究所 | Flexible inorganic semiconductor film and preparation method thereof |
| CN111834280A (en) * | 2020-07-24 | 2020-10-27 | 武汉新芯集成电路制造有限公司 | Temporary bonding method |
| CN112599409A (en) * | 2020-12-08 | 2021-04-02 | 武汉新芯集成电路制造有限公司 | Wafer bonding method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8592986B2 (en) * | 2010-11-09 | 2013-11-26 | Rohm Co., Ltd. | High melting point soldering layer alloyed by transient liquid phase and fabrication method for the same, and semiconductor device |
-
2023
- 2023-05-30 CN CN202310622486.1A patent/CN116344337B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106611717A (en) * | 2015-10-22 | 2017-05-03 | 浙江中纳晶微电子科技有限公司 | Procedure of processing workpiece and apparatus designed for procedure |
| CN111326467A (en) * | 2019-10-16 | 2020-06-23 | 中国电子科技集团公司第五十五研究所 | Flexible inorganic semiconductor film and preparation method thereof |
| CN111834280A (en) * | 2020-07-24 | 2020-10-27 | 武汉新芯集成电路制造有限公司 | Temporary bonding method |
| CN112599409A (en) * | 2020-12-08 | 2021-04-02 | 武汉新芯集成电路制造有限公司 | Wafer bonding method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116344337A (en) | 2023-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11652083B2 (en) | Processed stacked dies | |
| US7226812B2 (en) | Wafer support and release in wafer processing | |
| JP5591859B2 (en) | Substrate separation method and separation apparatus | |
| US7459343B2 (en) | Method of manufacturing semiconductor device and support structure for semiconductor substrate | |
| US11264231B2 (en) | Method for manufacturing backside metalized compound semiconductor wafer | |
| JP2005533376A (en) | Method and wafer for maintaining ultra-clean bonding pads on a wafer | |
| US20080318396A1 (en) | Grooving Bumped Wafer Pre-Underfill System | |
| WO2012056867A1 (en) | Stacked body and method for detaching stacked body | |
| KR20070070091A (en) | Method for manufacturing semiconductor device | |
| US6656820B2 (en) | Method for manufacturing a semiconductor device having a reliable thinning step | |
| CN101752273B (en) | Method of manufacturing semiconductor device | |
| JPH11204551A (en) | Manufacture of semiconductor device | |
| JP2007188967A (en) | Substrate support, substrate treatment method, and method of manufacturing semiconductor device | |
| WO2020108097A1 (en) | Method for holding ultra-thin semiconductor wafer in semiconductor integration process | |
| US10403598B2 (en) | Methods and system for processing semiconductor device structures | |
| US20100200957A1 (en) | Scribe-Line Through Silicon Vias | |
| US20160035616A1 (en) | Handler wafer removal by use of sacrificial inert layer | |
| US8420505B2 (en) | Process for manufacture of thin wafer | |
| CN116344337B (en) | Method for processing back of compound semiconductor wafer | |
| WO2023019819A1 (en) | Wafer cutting method | |
| JP2004186522A (en) | Manufacture method of semiconductor device | |
| CN106252279A (en) | Semiconductor structure and manufacture method thereof | |
| US7476606B2 (en) | Eutectic bonding of ultrathin semiconductors | |
| JPH07302772A (en) | Dicing, wafer, wafer fixing use tape and semiconductor device | |
| Chanchani | An Overview-temporary wafer bonding/debonding for 2.5 d and 3d technologies |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |