CN116338441A

CN116338441A - Chip testing device and testing system

Info

Publication number: CN116338441A
Application number: CN202310625876.4A
Authority: CN
Inventors: 方雅祺; 马茂松
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2023-06-27
Anticipated expiration: 2043-05-30
Also published as: CN116338441B

Abstract

The embodiment of the disclosure provides a chip testing device and a testing system. The device is used for providing a signal to be tested of a chip to be tested for analysis equipment, and comprises: a test platform having opposite first and second surfaces for providing test signals; the chip interface is arranged on the first surface of the test platform and is electrically connected with the test platform; the chip interface is used for being electrically connected with the chip to be tested, and transmitting the test signal from the test platform to the chip to be tested, so that the chip to be tested generates the signal to be tested; the test interface is arranged on the second surface of the test platform and is electrically connected with the chip interface; the test interface is used for being electrically connected with a connector of the analysis equipment so as to transmit a signal to be tested to the analysis equipment; in the direction perpendicular to the test platform, the test interface is correspondingly arranged with the chip interface; and the test base is arranged at the corresponding test interface of the second surface and is used for fixing the joint of the analysis equipment. The method and the device can reduce the loss of the signal, improve the quality of the signal and enable the test result to be more accurate.

Description

Chip testing device and testing system

Technical Field

The present disclosure relates to the field of semiconductor testing technologies, and in particular, to a chip testing device and a testing system.

Background

The chip is tested after production to verify its quality. When a logic analyzer is used for testing a chip, an adapter plate is usually required to be arranged on a test platform, various interfaces are arranged on the adapter plate, the chip to be tested is arranged on the adapter plate, and the chip to be tested is connected with the logic analyzer through the interfaces arranged on the adapter plate so as to perform the test.

However, due to the arrangement of the adapter plate, the wiring becomes longer, the signal transmission process becomes longer, the quality of signals is reduced, and the test result is easy to deviate.

The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and thus it may include information that does not form a related art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The embodiment of the disclosure provides a chip testing device, which is used for providing a signal to be tested of a chip to be tested for analysis equipment, and comprises a testing platform, a chip interface, a testing interface and a testing base. The test platform is provided with a first surface and a second surface which are opposite, and is used for providing a test signal; the chip interface is arranged on the first surface of the test platform and is electrically connected with the test platform; the chip interface is used for being electrically connected with the chip to be tested, and transmitting the test signal from the test platform to the chip to be tested, so that the chip to be tested generates the signal to be tested; the test interface is arranged on the second surface of the test platform and is electrically connected with the chip interface; the test interface is used for being electrically connected with a connector of the analysis equipment so as to transmit the signal to be tested to the analysis equipment; the test interface is correspondingly arranged with the chip interface in the direction perpendicular to the test platform; the test base is arranged at the position of the second surface of the test platform, which corresponds to the test interface and is used for fixing the joint of the analysis equipment during test.

In some embodiments of the disclosure, two opposite sides of the test interface are respectively provided with a plurality of first test points and a plurality of second test points, and the plurality of first test points positioned on one side of the test interface and the plurality of second test points positioned on the other side of the test interface are distributed in a central symmetry manner; the plurality of second test points positioned on one side of the test interface and the plurality of first test points positioned on the other side of the test interface are distributed in a central symmetry manner.

In some embodiments of the disclosure, the chip to be tested is a dual-channel chip, the first test point is used for testing the first channel in the dual-channel of the chip to be tested, and the second test point is used for testing the second channel in the dual-channel of the chip to be tested; when the first channel of the chip to be tested is tested, the connector of the analysis equipment is inserted into the test interface to be electrically connected with the first test point; and when the second channel of the chip to be tested is tested, the connector of the analysis equipment is inserted into the test interface to be electrically connected with the second test point after rotating 180 degrees.

In some embodiments of the present disclosure, the test base includes: a frame body surrounding an opening formed therethrough in a direction perpendicular to the test platform, one side of the frame body being connected to the second surface of the test platform, the frame body surrounding the test interface such that the test interface is exposed from the opening; the plurality of connecting pieces are arranged on the frame body and comprise first connecting parts, and the first connecting parts extend from one side of the frame body to a direction away from the test platform and are used for being connected with the connectors of the analysis equipment; the first connecting parts of the connecting pieces are distributed in a central symmetry mode, so that the connector of the analysis equipment can be connected with the first connecting parts after rotating 180 degrees.

In some embodiments of the disclosure, a first mounting groove and a second mounting groove which are symmetrically distributed in the center are further formed in one side, close to the test platform, of the frame body; the test base further comprises a fool-proof piece, the fool-proof piece is detachably arranged in the first mounting groove or the second mounting groove, the top surface of the fool-proof piece is flush with the surface of the frame body, which is close to the test platform, and the fool-proof piece protrudes out of the inner wall of the frame body.

In some embodiments of the disclosure, the fool-proof member includes a fixing portion and a fool-proof portion that are connected to each other, the fixing portion and the fool-proof portion each extend in a direction away from the test platform, the fixing portion is detachably mounted in the first mounting groove or the second mounting groove, a top surface of the fixing portion is flush with a surface of the frame body, which is close to the test platform, and the fool-proof portion protrudes from an inner wall of the frame body and is located in the opening.

In some embodiments of the disclosure, the device further includes a chip test socket detachably disposed on the chip interface and electrically connected to the chip interface for electrically connecting to the chip to be tested.

The embodiment of the disclosure also provides a test system, which comprises analysis equipment and a chip test device; the analysis equipment comprises a connector which is electrically connected with the chip testing device; the chip testing device comprises a testing platform, a chip interface, a testing interface and a testing base. The test platform is provided with a first surface and a second surface which are opposite, and is used for providing a test signal; the chip interface is arranged on the first surface of the test platform and is electrically connected with the test platform; the chip interface is used for being electrically connected with a chip to be tested, and transmitting the test signal to the chip to be tested so that the chip to be tested generates a signal to be tested; the test interface is arranged on the second surface of the test platform and is electrically connected with the chip interface; the test interface is electrically connected with the connector of the analysis equipment so as to transmit the signal to be tested to the analysis equipment; the test interface is correspondingly arranged with the chip interface in the direction perpendicular to the test platform; the test base is arranged at the position of the second surface of the test platform, which corresponds to the test interface, and is used for fixing the joint of the analysis equipment.

In some embodiments of the disclosure, two opposite sides of the test interface of the chip test device are respectively provided with a plurality of first test points and a plurality of second test points, and the plurality of first test points located at one side of the test interface and the plurality of second test points located at the other side of the test interface are distributed in a central symmetry manner; the plurality of second test points positioned on one side of the test interface and the plurality of first test points positioned on the other side of the test interface are distributed in a central symmetry manner; the chip to be tested is a double-channel chip, and the connector is inserted into the test interface, connected with the first test point and used for testing a first channel of the chip to be tested; and the connector is inserted into the test interface after rotating 180 degrees, is connected with the second test point and is used for testing the second channel of the chip to be tested.

In some embodiments of the present disclosure, the signal under test is an address command signal of the chip under test.

As can be seen from the above technical solutions, the chip testing device according to the embodiments of the present disclosure has at least one of the following advantages and positive effects:

in the embodiment of the disclosure, the chip interface is directly arranged on the first surface of the test platform, the test interface is directly arranged on the second surface of the test platform opposite to the first surface, and in the direction vertical to the test platform, the test interface is correspondingly arranged with the chip interface, and the electric connection between the chip interface and the test interface is realized through the test platform, so that the signal to be tested generated by the chip to be tested can be directly transmitted to the test interface through the test platform and then transmitted to the analysis equipment connected with the test interface.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIG. 1 is a simplified schematic diagram of a chip testing apparatus shown in some embodiments of the present disclosure;

FIG. 2 is a schematic perspective view of a chip testing apparatus according to some embodiments of the disclosure;

FIG. 3 is a schematic diagram showing the chip testing apparatus of FIG. 2 flipped 180, showing the test interface and the test base;

FIG. 4 is a schematic diagram of a test interface shown in some embodiments of the present disclosure;

FIG. 5 is a schematic perspective view of a test base shown in some embodiments of the present disclosure, with a fool-proof member inserted into a first mounting slot;

FIG. 6 is a schematic perspective view of a test base shown in some embodiments of the present disclosure, with a fool-proof member separated from a first mounting slot;

FIG. 7 is a schematic view of a connector coupled to a test base with a fool-proofing member inserted into a first mounting slot according to some embodiments of the present disclosure;

FIG. 8 is a schematic view of some embodiments of the present disclosure showing the fool-proofing member inserted into the second mounting slot after the connector is rotated 180 degrees and then connected to the test base;

FIG. 9 is a simplified schematic diagram of a chip testing apparatus according to further embodiments of the present disclosure;

FIG. 10 is a schematic diagram of a test system shown in some embodiments of the present disclosure;

FIG. 11 is a graph of test results of signal loss at a chip interface measured by an interposer disposed on a test platform and signal loss at a chip interface of an embodiment of the present disclosure;

FIG. 12 is a graph of test results of signal loss at a test interface measured by an interposer disposed on a test platform and signal loss at a test interface of an embodiment of the present disclosure;

FIG. 13 is a flow chart of a method of testing a chip, as shown in some embodiments of the present disclosure;

FIG. 14 is a schematic diagram of a computer device according to some embodiments of the present disclosure;

FIG. 15 is a schematic diagram of a computer-readable storage medium illustrating some embodiments.

Reference numerals illustrate:

100. a chip testing device; 1. a test platform; 11. a first surface; 12. a second surface; 2. a chip interface; 3. testing an interface; 31. a first test point; 32. a second test point; 4. a test base; 41. a frame; 411. a first frame edge; 412. a second frame edge; 413. a third frame edge; 414. a fourth frame edge; 415. a first mounting groove; 416. a second mounting groove; 42. an opening; 40. a connecting piece; 43. a first connection portion; 44. a second connecting portion; 45. a fool-proof member; 451. a fixing part; 452. a fool-proof part; 453. a connection part; 5. a chip test seat; 6. a system-on-chip; 200. an analysis device; 201. a joint; 300. and a chip to be tested.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.

In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the directions of examples in the drawings. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of structures to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like are used merely as labels, and are not intended to limit the numerals of their objects.

The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

In addition, in the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.

After the chip is produced, it is tested to check its quality. For example, using a logic analyzer to test the chip. The logic analyzer collects and displays signals to be tested of the chip from the chip testing device 100 by using a clock, and is mainly used for time sequence judgment.

The logic analyzer needs to collect the signal to be measured of the chip to be measured, so as to analyze and display. The signal to be tested is generated by a chip testing device. In general, an interposer is disposed on a test platform in a chip test apparatus, wiring is performed on the interposer, and a chip interface and two test interfaces are disposed on the same surface of the interposer. The two test interfaces are used for connecting the two connectors of the logic analyzer so as to transmit signals to be tested to the logic analyzer. A socket is typically soldered to the chip interface, after which the chip is placed on the socket. The test platform provides test signals, the test signals are transmitted to the chip through the adapter plate, after signals to be tested are generated at the chip, the signals are transmitted to the test interface through the adapter plate, and then the signals are transmitted to the logic analyzer through the connector.

After the test signal provided by the test platform is transmitted to the chip, the test signal is generated through the chip and transmitted to the test interface 3, the wiring in the adapter plate has branches, and in actual test, the test signal is affected, so that the test signal has reflection. In addition, when testing a chip with two channels, such as LPDDR4 (Low Power Double Data Rate, fourth generation mobile low power memory), two test interfaces and two connectors are required to be provided to collect signals to be tested, so that the cost is high.

Based on this, as shown in fig. 1, 9 and 10, the embodiment of the present disclosure provides a chip testing apparatus 100 for providing a signal to be tested of a chip to be tested 300 to an analysis device 200. As shown in fig. 1 to 3, the chip test apparatus 100 includes a test platform 1, a chip interface 2, a test interface 3, and a test base 4.

As shown in fig. 1 to 3, the test platform 1 has a first surface 11 and a second surface 12 opposite to each other, and the test platform 1 is configured to provide a test signal.

In some embodiments, the test platform 1 may be a wiring board. The circuit board may be a PCB (Printed Circuit Board ) comprising a substrate and conductive tracks (not shown in the figures) provided inside and on the surface of the substrate.

The test platform 1 has opposite first and second surfaces 11, 12, the test platform 1 being adapted to provide a test signal.

In some embodiments, as shown in fig. 9, the Chip testing apparatus 100 may further include a System On Chip (SOC) 6 electrically connected to the test platform 1 for issuing a command to the test platform 1 to cause the test platform 1 to provide a test signal.

In some embodiments, as shown in fig. 1 and 9, the chip interface 2 is disposed on the first surface 11 of the test platform 1 and is electrically connected to the test platform 1. The chip interface 2 is electrically connected to the chip 300 to be tested, and transmits the test signal provided by the test platform 1 from the test platform 1 to the chip 300 to be tested, so that the chip 300 to be tested generates the signal to be tested. Arrows in fig. 1 and 9 represent the transmission of signals.

Specifically, the chip interface 2 may include a plurality of channels, and each channel may be fixedly and electrically connected to one pin of the chip 300 to be tested, so as to correspondingly transmit the test signal to the chip 300 to be tested, and enable the chip 300 to be tested to generate the signal to be tested. The chip interface 2 is electrically connected to the test platform 1 through wires to be able to receive test signals. The trace may be a metal disposed inside the test platform 1, or may be a metal wire, a metal block, etc. formed on the surface of the test platform 1 by an electroplating process, which is not limited herein.

As shown in fig. 2, the chip testing apparatus 100 includes a chip testing seat 5 detachably disposed on the chip interface 2 and electrically connected to the chip interface 2 for electrically connecting to the chip 300 to be tested.

In particular, the chip test socket 5 may be understood as a socket, and the chip test socket 5 may be detachably connected to the chip interface 2, for example, the chip test socket 5 may be plugged onto the test platform 1 or may be screwed onto the test platform 1. During testing, the chip 300 to be tested is placed on the chip testing seat 5, and after testing, when other chips are replaced, the chip testing seat 5 can be detached for replacing the chip to be tested. Compared with the test seat welded on the test platform 1, the detachably mounted chip test seat 5 is convenient for replacing chips, has lower loss rate, saves cost and simultaneously avoids the adverse effect of welding operation on test signals.

In some embodiments, the test interface 3 is disposed on the second surface 12 of the test platform 1 and is electrically connected to the chip interface 2; the test interface 3 is used for electrically connecting with the connector 201 of the analysis device 200 to transfer the signal to be tested into the analysis device 200.

Specifically, as shown in fig. 1 to 3, the test interface 3 and the chip interface 2 are disposed on opposite sides of the test platform 1, and the test interface 3 and the chip interface 2 are disposed correspondingly in a direction perpendicular to the test platform 1. The test interface 3 is electrically connected with the chip interface 2 through the wiring of the test platform 1 so as to be capable of receiving the signal to be tested transmitted by the chip interface 2.

As shown in fig. 1, the test interface 3 is arranged corresponding to the chip interface 2 in a direction perpendicular to the test platform 1, i.e. the test interface 3 is located directly below the chip interface 2 in a direction perpendicular to the first surface 11 and/or the second surface 12 of the test platform 1. It will also be appreciated that the traces between the test interface 3 and the chip interface 2 may be perpendicular to the test platform 1.

Because the test interface 3 and the chip interface 2 are arranged on two opposite sides of the test platform 1, and the test interface 3 and the chip interface 2 are correspondingly arranged in the direction vertical to the test platform 1, wiring can vertically penetrate through the test platform 1 from the first surface 11 of the test platform 1 to reach the test interface 3 positioned on the second surface 12, wiring between the test interface 3 and the chip interface 2 can be shortened to the greatest extent, the transmission process of transmission signals is shortened, the stability of signal transmission is improved, and the test accuracy is further improved.

In some embodiments, as in fig. 4, a distribution of test points of the test interface 3 is shown. The opposite two sides of the test interface 3 are respectively provided with a plurality of first test points 31 and a plurality of second test points 32, and the first test points 31 positioned on one side of the test interface 3 and the second test points 32 positioned on the other side of the test interface 3 are distributed in a central symmetry manner. The plurality of second test points 32 located at one side of the test interface 3 and the plurality of first test points 31 located at the other side of the test interface 3 are distributed in a central symmetry manner.

Specifically, as shown in fig. 4, A1 to a27, B1 to B27 correspond to test points on both sides of the test interface 3, respectively. A test point is understood to mean a pin which can be plugged into a connector 201 of the analysis device 200 in order to achieve an electrical connection. A simplified schematic of the test base 4 is also shown in fig. 4, from which it can be seen that the frame 41 of the test base 4 surrounds the test points, so that after the connector 201 has been plugged into the test base 4, its probes can be connected correspondingly to the test points.

With continued reference to fig. 4, there are a plurality of first test points 31 on opposite sides of the test interface 3, for example, the test points corresponding to A1 to a15 and B1 to B12 are the first test points 31, and the test points corresponding to a16 to a27 and B13 to B27 are the second test points 32. When the chip 300 to be tested is a chip with two channels, the first test point 31 is used for testing the first channel of the chip 300 to be tested, and the second test point 32 is used for testing the second channel of the chip 300 to be tested. For convenience of distinction, the first test point 31 denoted by the suffix_a and the second test point 32 denoted by the suffix_b are marked on the outer sides of the corresponding A1 to a15 and B1 to B12, respectively. For example, A7 corresponds to cke0_a, indicating that A7 is connected to a clock signal for testing the first channel of the chip 300 under test. B21 corresponds to CKE0_B, and represents that B21 is connected to the clock signal for testing the second channel of the chip 300 to be tested.

With continued reference to fig. 4, the plurality of first test points 31 located on one side of the test interface 3 and the plurality of second test points 32 located on the other side are distributed in a central symmetry. Wherein, the central symmetry means that after one pattern rotates 180 degrees around a certain point, the pattern can be overlapped with the other pattern, and the two patterns are central symmetry about the point. In the embodiment of the disclosure, the first test points A1 to a15 located at one side and the second test points B13 to B27 located at the other side are distributed in a central symmetry manner, that is, after the first test points A1 to a15 rotate 180 ° around the central point, they can be overlapped with the second test points B13 to B27. For example, A7 and B21 are distributed in a central symmetry, A1 and B27 are distributed in a central symmetry, and A5 and B23 are distributed in a central symmetry, which are not shown here.

In addition, the second test points 32 on one side of the test interface 3 and the first test points 31 on the other side are distributed in a central symmetry manner. In the embodiment of the disclosure, the second test points a16 to a27 located at one side and the first test points B1 to B12 located at the other side are distributed in a central symmetry manner, that is, the second test points a16 to a27 can be overlapped with the first test points B1 to B12 after rotating 180 ° around the central point. For example, a16 and B12 are distributed in a central symmetry, a27 and B1 are distributed in a central symmetry, and a19 and B3 are distributed in a central symmetry, which is not shown here.

In the embodiment of the disclosure, the test points located at two opposite sides of the test interface 3 are arranged to be distributed in a central symmetry manner, if the chip 300 to be tested has two channels, after the first channel is tested, the connector 201 of the analysis device 200 can be rotated 180 degrees, and still can be connected with each test point, so that the electrical connection between the connector 201 and the test interface 3 is ensured.

Based on this, in the embodiment of the disclosure, the chip 300 to be tested is a dual-channel chip, for example, the chip 300 to be tested is LPDDR4, the first test point 31 is used for testing a first channel in dual channels of the chip 300 to be tested, and the second test point 32 is used for testing a second channel in dual channels of the chip 300 to be tested. In the testing of the first channel of the chip 300 to be tested, the connector 201 of the analysis device 200 is inserted into the test interface 3 to be electrically connected with the first test point 31. When testing the second channel of the chip 300 to be tested, the connector 201 of the analysis device 200 is inserted into the test interface 3 after rotating 180 ° to be electrically connected with the second test point 32.

In the embodiment of the disclosure, the clock signals accessed by the first test point A7 and the second test point B21 are unchanged when testing is performed. That is, during the first channel test of the chip 300 to be tested, the clock signal needs to be connected to the first test point A7, and during the second channel test of the chip 300 to be tested, the clock signal needs to be connected to the second test point B21, so that when the second channel is tested, the probe receiving the clock signal in the connector 201 is still connected to B21, and receives the clock signal, and other probes can be correspondingly connected to other test points. Probes in the connector 201 can be selected to be electrically connected with test points corresponding to the test requirements according to the test requirements. For example, when testing the second channel, after rotating the joint 201 by 180 ° and connecting with the test interface 3, the first test point 31 and the joint 201 may be selected to be electrically disconnected by controlling, the B21 in the second test point 32 is electrically connected with the test joint 201, and if the test requirements are the test contents corresponding to the B17 and the B18, the B17 and the B18 in the second test point 32 may be selected to be electrically connected with the joint 201 respectively. Those skilled in the art can select the electrical connection between the connector 201 and the test point according to the actual test requirement, so as to obtain the required test result.

In the embodiment of the disclosure, since the DQ (data) signal rate of the LPDDR chip is faster, the analysis device 200 (e.g. a logic analyzer) is harder to grasp the DQ signal, so the chip test apparatus 100 of the embodiment of the disclosure may test only the CA (Command address) signal of the chip, that is, the test points of the test interface 3 are only used for testing the CA signal, and the number of required test points is smaller, so only one test interface 3 may be provided in the embodiment of the disclosure. Thus, the chip 300 to be tested with two channels can be tested by using only one connector 201, so that the cost is saved and the operation is flexible.

In some embodiments, as shown in fig. 9, the Chip test apparatus 100 further includes a System On Chip (SOC) 6, and the SOC 6 may be disposed on the test platform 1 and electrically connected to the test platform 1. The system on chip 6 is arranged to issue commands such that the test platform 1 provides test signals.

In the embodiment of the present disclosure, as shown in fig. 2 and 3, the test base 4 is provided at the corresponding test interface 3 of the second surface 12 of the test platform 1, for fixing the connector 201 of the analysis device 200 during the test.

In some embodiments, as shown in fig. 5, the test base 4 includes a frame 41 and a plurality of connectors 40. The frame 41 surrounds an opening 42 penetrating in a direction perpendicular to the test platform 1, one side of the frame 41 is connected to the second surface 12 of the test platform 1, and the frame 41 surrounds the test interface 3, so that the test interface 3 is exposed from the opening 42; the plurality of connectors 40 are provided in the frame 41, and the connectors 40 include a first connection portion 43, and the first connection portion 43 extends from one side of the frame 41 in a direction away from the test platform 1 for connection with the connector 201 of the analysis device 200. Wherein the plurality of first connection parts 43 of the plurality of connection members 40 are arranged in a central symmetry so that the connector 201 of the analyzing apparatus 200 can be connected with the plurality of first connection parts 43 after being rotated 180 °.

In particular, the shape of the opening 42 of the test base 4 may correspond to the shape of the access end profile of the connector 201 to allow the connector 201 to be stably connected with a test site. In some embodiments, as shown in fig. 5, the opening 42 is rectangular in shape. The frame 41 includes a first frame edge 411, a second frame edge 412, a third frame edge 413, and a fourth frame edge 414, which are connected end to end in order to form the opening 42. Wherein the first frame edge 411 is opposite to the third frame edge 413, and the second frame edge 412 is opposite to the fourth frame edge 414.

The frame 41 includes a top surface and a bottom surface, and the "top" and "bottom" are positional relationships thereof from the perspective of fig. 5, and are not limited only for distinguishing the two surfaces. After mounting the frame 41 to the test platform 1, the top surface is mounted to the second surface 12 of the test platform 1 and the bottom surface is remote from the test platform 1.

With continued reference to fig. 2 and 5, a plurality of connectors 40 may be provided at four corners of the frame 41 and pass through the frame 41. The connecting member 40 may include a first connecting portion 43 and a second connecting portion 44, and the first connecting portion 43 and the second connecting portion 44 may be integrally formed or may be fixedly connected, which is not limited herein. The first connection portion 43 protrudes from the bottom surface of the frame 41, that is, when the test base 4 is disposed on the test platform 1, the first connection portion 43 extends away from the test platform 1. For example, the first connection portion 43 may be a cylinder, and a groove matching with the first connection portion 43 is provided on the connector 201 so that the connector 201 is connected with the first connection member 43.

In some embodiments, the plurality of connecting members 40 are distributed in a central symmetry, and the first connecting portions 43 are also distributed in a central symmetry. That is, when the joint 201 is rotated 180 °, it can still be fittingly connected with the first connecting part 43. In one embodiment, the structure and the dimensions of each first connection portion 43 are the same, and the structure and the dimensions of the groove on the connector 201 that mates with the first connection portion 43 are also the same.

In some embodiments, the number of the connecting members 40 may be two, four or six, so long as the first connecting portion 43 can be connected to the connector 201 when testing the first channel, and the connector 201 can still be connected after rotating 180 ° when testing the second channel, which is not particularly limited herein.

In some embodiments, as shown in fig. 5, the second connection portion 44 protrudes from a surface of the frame 41 near the test platform 1, that is, a top surface of the frame 41 described in the above embodiments. The second connection portion 44 is used for connecting with the test platform 1. In some embodiments, the second connection portion 44 may be a cylinder, and an outer surface thereof has threads to be screwed with the bottom of the test platform 1. As shown in fig. 5, the connector 40 has four, and the second connector 44 has four, which are provided at four corners of the frame 41, respectively. Of course, the number of the connectors 44 may be two, three, six or more, so long as they can be connected to the test platform 1, and those skilled in the art can set the number according to the actual situation, and the number is not particularly limited herein.

In some embodiments, the connecting pieces 40 are integrally formed pillars and penetrate through four corners of the frame 41, the portion extending from the bottom surface of the frame 41 toward the direction away from the test platform 1 is a first connecting portion 43, the portion extending from the top surface of the frame 41 toward the direction close to the test platform 1 is a second connecting portion 44, and the four connecting pieces 40 may be arranged in a central symmetry manner because the first connecting portion 43 is to be connected with the connector 201. When the test base 4 is connected to the test platform 1, the first connecting portion 43 can be screwed, so that the second connecting portion 43 can be screwed into the corresponding threaded hole of the test platform 1, and the test base 4 is connected with the test platform 1. Thus, the connecting member 40 is movably inserted into the frame 41.

In other embodiments, the connecting member 40 may not include the second connecting portion 44, i.e. the connecting member 40 is disposed in the frame 41 in a penetrating manner, and one end of the connecting member extends from the bottom surface of the frame 41 in a direction away from the testing platform 1, and the other end of the connecting member does not extend out of the top surface of the frame 41, i.e. only includes the first connecting portion 43, so that when the testing base 4 is connected to the testing platform 1, the top surface of the frame 1 of the testing base 4 may be adhered or welded to the second surface 12 of the testing platform 1.

In some embodiments, as shown in fig. 5 and 6, a side of the frame 41 near the test platform 1 is further provided with a first mounting groove 415 and a second mounting groove 416 that are symmetrically distributed in the center. The test base 4 further comprises a fool-proof member 45, the fool-proof member 45 is detachably mounted in the first mounting groove 415 or the second mounting groove 416, the top surface of the fool-proof member 45 is flush with the top surface of the frame 41, which is close to the test platform 1, and the fool-proof member 45 protrudes laterally from the inner wall of the frame 41.

Specifically, as shown in fig. 6, the first mounting groove 415 and the second mounting groove 416 may be formed in the first frame edge 411 and the third frame edge 413 of the frame 41, and the first mounting groove 415 and the second mounting groove 416 are distributed in a central symmetry, and the first mounting groove 415 and the second mounting groove 416 are identical in structure and size, so that the same fool-proof member 45 can be inserted into both the first mounting groove 415 and the second mounting groove 416. Of course, the first mounting groove 415 and the second mounting groove 416 may be provided on the second frame side portion 412 and the fourth frame side portion 414, respectively, or on the second frame side portion 412 and the third frame side portion 413, respectively, and the two may be distributed in a central symmetry manner. That is, after the insertion of the fool-proof member 45, the fool-proof member is not particularly limited as long as it can be rotated 180 ° at the joint 201 and still can play a fool-proof role.

In some embodiments, the fool-proof member 45 includes a fixing portion 451 and a fool-proof portion 452 that are connected to each other, where the fixing portion 451 and the fool-proof portion 452 each extend in a direction away from the test platform 1, the fixing portion 451 is detachably mounted in the first mounting groove 415 or the second mounting groove 416, a top surface of the fixing portion 451 is flush with a surface of the frame 41 near the test platform 1, and the fool-proof portion 452 protrudes laterally from an inner wall of the frame 41 and is located in the opening 42.

Specifically, the fixing portion 451 of the fool-proof member 45 is connected to the fool-proof portion 452, the fixing portion 451 and the fool-proof portion 452 are disposed in parallel, and the fixing portion 451 can be inserted into the first mounting groove 415 or the second mounting groove 416 such that the fool-proof member 45 is detachably mounted in the first mounting groove 415 or the second mounting groove 416.

With continued reference to fig. 6, the first mounting slot 415 has an opening toward the second mounting slot 416, and the second mounting slot 416 has an opening toward the first mounting slot 415. When the first mounting groove 415 is formed in the first frame edge 411 and the second mounting groove 416 is formed in the third frame edge 413, the opening of the first mounting groove 415 is formed in the inner wall of the first frame edge 411, and the opening of the second mounting groove 416 is formed in the inner wall of the third frame edge 413, so that after the fixing portion 451 is inserted into the first mounting groove 415 or the second mounting groove 416, the opening can play a role of giving way to the fool-proof portion 452, so that the top surface of the fixing portion 451 is flush with the surface of the frame 41, and the connection between the chip test socket 5 and the test platform 1 is prevented.

In some embodiments, the fool-proof member 45 may further include a connection portion 453, and the fixing portion 451 and the fool-proof portion 452 may be connected to one side of the connection portion 453 at a distance and extend in the same direction from the one side, and the other side of the connection portion 453 is a plane. The first mounting groove 415 is provided with a fixing hole, and the fixing hole is provided corresponding to the fixing portion 451. When the fool-proof member 45 is mounted in the first mounting groove 415, the fixing portion 451 is inserted into the fixing hole, so as to prevent the fool-proof member 45 from being displaced in the lateral direction (i.e., the extending direction of the second frame edge portion 412 in fig. 6) such that the connector 201 cannot be accurately connected to the test base 4. The connection portion 453 is located in the first mounting groove 415, and a plane of the other side of the connection portion 453 is flush with the surface of the frame body 41, so that the test base 4 is stably connected with the test platform 1. The connection portion 453 extends at least to the opening of the first mounting groove 415 in the lateral direction so that the fool-proof portion 452 is located inside the inner wall of the first frame side 411, i.e., in the opening 42, and thus the connector 201 can be inserted accurately and quickly. Regarding the structure of the fool-proof member 45 mounted in the second mounting groove 416, reference may be made to the above-described structure of the fool-proof member 45 mounted in the first mounting groove 415, and the description thereof will not be repeated here.

In other embodiments, the fool-proof member 45 may include only the connection portion 453 and the fool-proof portion 452, i.e., the fixing portion 451 is not provided, unlike the above-described embodiments. The first mounting groove 415 and the second mounting groove 416 may not be provided with fixing holes, and the connection portion 453 may be directly inserted into the first mounting groove 415 and the second mounting groove 416. After the first channel test of the chip 300 to be tested is completed, the fool-proof member 45 may be directly pulled out from the opening 42 of the first mounting groove 415 and then directly inserted into the second mounting groove 416, so as to play a fool-proof role on the connector 201 rotating 180 °. Thus, the transition of the fool-proof member 45 between the first mounting groove 415 and the second mounting groove 416 is easier and more flexible, without loosening or dismantling the connection of the test base 4 to the test platform 1, and the operation is simpler.

As shown in fig. 7, during the test of the first channel of the chip 300 to be tested, the fool-proof member 45 is inserted into the first mounting groove 415, and when the connector 201 is plugged into the test base 4, the fool-proof member 45 plays a fool-proof role. As shown in fig. 8, in the second channel test of the chip 300 to be tested, the fool-proof member 45 is inserted into the second mounting groove 416, and when the connector 201 is inserted into the test base 4 after rotating 180 °, the fool-proof member 45 still can play a fool-proof role, so as to ensure that the connector can be quickly and correctly inserted into the test base 4 to be correspondingly connected with the test point on the test interface 3.

In summary, in the chip testing device of the embodiment of the disclosure, the chip interface 2 is directly disposed on the first surface 11 of the testing platform 1, the testing interface 3 is directly disposed on the second surface 12 of the testing platform 1 opposite to the first surface 11, and in the direction perpendicular to the testing platform 1, the testing interface 3 is disposed corresponding to the chip interface 2, and the electrical connection between the chip interface 2 and the testing interface 3 is implemented through the testing platform 1, so that the signal to be tested generated by the chip 300 to be tested can be directly transferred to the testing interface 3 through the testing platform 1, and then transferred to the analysis equipment 200 connected with the testing interface 3.

Referring to fig. 11, a graph of test results of signal loss at the chip interface 2 measured by setting the interposer on the test platform 1 and signal loss at the chip interface 2 of the embodiment of the present disclosure is shown, wherein the abscissa represents frequency (GHz, megahertz) and the ordinate represents amplitude (dB, decibel) of insertion loss. As can be seen from the figure, the signal loss at the chip interface 2 of the embodiment of the present disclosure is lower, so the chip test apparatus 100 of the embodiment of the present disclosure can improve the quality of the test signal and the signal to be tested. Referring to fig. 12, a graph of a test result of signal loss of the test interface 3 measured by the interposer and signal loss at the test interface 3 of the embodiment of the disclosure is shown on the test platform 1, it can be seen from the graph that the signal loss at the test interface 3 of the embodiment of the disclosure is lower, and quality of a signal to be tested transferred to the analysis device 200 can be improved, so that the chip test apparatus 100 of the embodiment of the disclosure can make a test result more accurate.

As shown in fig. 10, the embodiment of the present disclosure further provides a test system including an analysis device 200 and a chip test apparatus 100. Wherein the analysis device 200 comprises a connector 201, the connector 201 being electrically connected to the chip testing apparatus 100.

The chip testing apparatus 100 may include a test platform 1, a chip interface 2, a test interface 3, and a test base 4. Wherein the test platform 1 has a first surface 11 and a second surface 12 opposite to each other, and the test platform 1 is configured to provide a test signal. The chip interface 2 is arranged on the first surface 11 of the test platform 1 and is electrically connected with the test platform 1; the chip interface 2 is used for electrically connecting with the chip 300 to be tested, and transmitting the test signal to the chip 300 to be tested, so that the chip 300 to be tested generates the signal to be tested. The test interface 3 is disposed on the second surface 12 of the test platform 1 and is electrically connected to the chip interface 2. The test interface 3 is electrically connected to the connector 201 of the analysis device 200 to transfer the signal to be tested into the analysis device 200. In a direction perpendicular to the test platform 1, the test interface 3 is arranged corresponding to the chip interface 2. The test base 4 is arranged at the corresponding test interface 3 of the second surface 12 of the test platform 1 for fixing the connector 201 of the analysis device 200. The chip testing apparatus 100 in the embodiments of the present disclosure may be the chip testing apparatus 100 described in any of the above embodiments, and the specific structure thereof is not described herein.

In some embodiments, the analysis device 200 may include an analysis module (not shown in the figures) to which the signal under test can be transferred when the connector 201 is electrically connected to the test interface 3 of the chip test apparatus 100. The analysis module analyzes the signal to be measured, and can intuitively show the analysis result in the analysis device 200. In some embodiments, the analysis device 200 may be a logic analyzer.

In some embodiments, two opposite sides of the test interface 3 of the chip test device 100 are respectively provided with a plurality of first test points 31 and a plurality of second test points 32, and the plurality of first test points 31 on one side of the test interface 3 and the plurality of second test points 32 on the other side of the test interface 3 are distributed in a central symmetry manner; the plurality of second test points 32 located at one side of the test interface 3 and the plurality of first test points 31 located at the other side of the test interface 3 are distributed in a central symmetry manner. The chip 300 to be tested is a dual-channel chip, and the connector 201 is inserted into the test interface 3 and connected with the first test point 31 for testing the first channel of the chip 300 to be tested; the connector 201 is inserted into the test interface 3 after rotating 180 degrees, and is connected with the second test point 32, so as to test the second channel of the chip 300 to be tested.

In the embodiment of the disclosure, the test points located at two opposite sides of the test interface 3 are arranged to be distributed in a central symmetry manner, and for the chip 300 to be tested with two channels, after the first channel is tested, the connector 201 of the analysis device 200 is rotated 180 degrees, and the connector 201 can still be connected with each test point, so that the electrical connection between the connector 201 and the test interface 3 is ensured. Thus, the chip 300 to be tested with two channels can be tested by using only one connector 201, so that the cost is saved and the operation is flexible.

In some embodiments, the analysis device 200 further includes a test selection module for selecting a test item of the chip 300 under test, and after selecting the test item, the control connector 201 is electrically connected to a test point of a corresponding test item of the test interface 3.

Specifically, as shown in fig. 4, the test interface 3 of the chip test apparatus 100 has a plurality of test points, and the functions of the respective test points are different. For example, when testing the first channel of the chip 300 under test, after accessing A7 and A8 (accessing the clock signal), the test point corresponding to the test item may be selected to be electrically connected with the connector 201 according to the test item, so as to perform the test according to the requirement.

In some embodiments, the signal to be tested generated by the chip under test 300 may be a Command Address (CA) signal of the chip under test 300. That is, the test points of the test interface 3 are only used for testing the CA signal, so that the number of required test points is reduced, and thus in the embodiment of the present disclosure, only one test interface 3 may be provided, so that the test of the chip 300 to be tested having two channels may be completed using only one connector 201, saving cost and being flexible to operate.

In summary, in the test system of the embodiment of the disclosure, the chip interface 2 of the chip test device 100 is directly disposed on the first surface 11 of the test platform 1, the test interface 3 is directly disposed on the second surface 12 opposite to the first surface 11 of the test platform 1, in the direction perpendicular to the test platform 1, the test interface 3 is disposed corresponding to the chip interface 2, and the electrical connection between the chip interface 2 and the test interface 3 is implemented through the test platform 1, so that the signal to be tested generated by the chip 300 to be tested can be directly transmitted to the test interface 3 through the test platform 1, and then transmitted to the analysis device 200 connected with the test interface 3.

As shown in fig. 13, the embodiment of the present disclosure further includes a chip testing method, which may be applied to the testing system described in any of the above embodiments. The test method may include steps S131 to S133.

S131: test signals are provided by the test platform 1 and are transmitted to the chip 300 to be tested through the chip interface 2.

S132: the chip 300 to be tested generates a signal to be tested according to the test signal, and the signal to be tested is transmitted to the analysis device 200 through the test interface 3 and the connector 201 of the analysis device 200 in sequence.

S133: the signal to be measured is analyzed by the analyzing device 200.

The test method of the embodiment of the present disclosure is applied to the test system of any one of the embodiments, in which the chip test device 100 omits the adapter plate, shortens the routing length, further shortens the routing length and the signal transmission process between the chip interface 2 and the test interface 3 because the chip interface 2 and the test interface 3 are located on two opposite sides of the test platform 1, reduces the loss of signals, improves the quality of signals, and makes the test result more accurate.

In some embodiments, two opposite sides of the test interface 3 of the chip test device 100 in the test system are respectively provided with a plurality of first test points 31 and a plurality of second test points 32, and the plurality of first test points 31 on one side of the test interface 3 and the plurality of second test points 32 on the other side of the test interface 3 are distributed in a central symmetry manner; the plurality of second test points 32 located at one side of the test interface 3 and the plurality of first test points 31 located at the other side of the test interface 3 are distributed in a central symmetry manner. The chip 300 to be tested is a dual-channel chip, the first test point 31 is used for testing a first channel in the dual channels of the chip 300 to be tested, and the second test point 32 is used for testing a second channel in the dual channels of the chip 300 to be tested.

The method of the embodiment of the disclosure further comprises the following steps: inserting the connector 201 of the analysis device 200 into the test interface 3 to electrically connect with the first test point 31, and testing the first channel; the connector 201 of the analysis device 200 is rotated 180 degrees and then inserted into the test interface 3 to be electrically connected with the second test point 32, so as to test the second channel. Thus, the chip 300 to be tested with two channels can be tested by using only one connector 201, so that the cost is saved and the operation is flexible.

In some embodiments, the method further comprises: the test items of the chip 300 to be tested are selected in the analysis device 200, and after the test items are selected, the control connector 201 is electrically connected with the test points of the corresponding test items of the test interface 3. Thus, test points corresponding to test items may be selected for electrical connection with the connector 201 according to the test items to achieve testing as desired.

The embodiment of the disclosure also provides computer equipment. As shown in fig. 14, the computer device in embodiments of the present disclosure may include one or more processors 141, memory 142, and input-output interfaces 143. The processor 141 is connected to the memory 142 and the input/output interface 143, respectively, and as shown in fig. 14, the processor 141, the memory 142 and the input/output interface 143 are connected via a bus 144. The memory 142 is used for storing a computer program comprising program instructions, and the input output interface 143 is used for receiving data and outputting data, such as for data interaction between a host and a computer device, or for data interaction between respective virtual machines in a host; processor 141 is operative to execute program instructions stored in memory 142.

Wherein the processor 141 may perform the following operations: providing a test signal through the test platform 1, and transmitting the test signal to the chip 300 to be tested through the chip interface 2; generating a signal to be tested according to the test signal through the chip to be tested 300, and transmitting the signal to be tested to the analysis equipment 200 through the test interface 3 and the connector 201 of the analysis equipment 200 in sequence; the signal to be measured is analyzed by the analyzing device 200.

In some possible implementations, the processor 141 may be a central processing module (central processing unit, CPU), which may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate arrays (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 142 may include read only memory and random access memory, and provides instructions and data to the processor 141 and the input output interface 143. A portion of memory 142 may also include non-volatile random access memory. For example, the memory 142 may also store information of device type.

In a specific implementation, the computer device may execute, through each built-in functional module, an implementation manner provided by each step in any method embodiment described above, and specifically may refer to an implementation manner provided by each step in a diagram shown in the method embodiment described above, which is not described herein again.

Embodiments of the present disclosure perform the steps of the methods shown in any of the embodiments described above by providing a computer device comprising a processor 141, an input output interface 143, and a memory 142, the computer program in the memory 142 being retrieved by the processor 141.

The embodiment of the disclosure further provides a computer readable storage medium 150, as shown in fig. 15, where the computer readable storage medium 150 stores a computer program, and the computer program is adapted to be loaded and executed by the processor 141 to perform the chip testing method provided by each step in any of the foregoing embodiments, and specifically refer to the implementation manner provided by each step in any of the foregoing embodiments, which is not described herein again.

In addition, the description of the beneficial effects of the same method is omitted. For technical details not disclosed in the embodiments of the computer-readable storage medium 150 related to the present disclosure, please refer to the description of the embodiments of the method of the present disclosure. As an example, a computer program may be deployed to be executed on one computer device or on multiple computer devices at one site or distributed across multiple sites and interconnected by a communication network.

The computer readable storage medium 150 may be an internal storage unit of the computer device provided in any of the foregoing embodiments, for example, a hard disk or a memory of the computer device. The computer readable storage medium 150 may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), etc. that are provided on the computer device. Further, the computer-readable storage medium 150 may also include both internal storage units and external storage devices of the computer device. The computer-readable storage medium 150 is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium 150 may also be used to temporarily store data that has been output or is to be output.

The disclosed embodiments also provide a computer program product or computer program comprising computer instructions stored in the computer-readable storage medium 150. The computer instructions are read from the computer-readable storage medium 150 by a processor of a computer device, which executes the computer instructions, causing the computer device to perform the methods provided in the various alternatives in any of the embodiments described above.

The computer equipment, the computer readable storage medium and the computer program product or the computer program provided by the embodiment of the disclosure execute the test method applied to the test system in any of the embodiments, so that the loss of signals can be reduced, the quality of the signals can be improved, and the test result is more accurate.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the disclosure. The disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. Embodiments of the present disclosure describe the best mode known for carrying out the disclosure and will enable one skilled in the art to utilize the disclosure.

Claims

1. A chip testing apparatus for providing a signal to be tested of a chip to be tested to an analysis device, the chip testing apparatus comprising:

A test platform having opposite first and second surfaces, the test platform for providing a test signal;

the chip interface is arranged on the first surface of the test platform and is electrically connected with the test platform; the chip interface is used for being electrically connected with the chip to be tested, and transmitting the test signal from the test platform to the chip to be tested, so that the chip to be tested generates the signal to be tested;

the test interface is arranged on the second surface of the test platform and is electrically connected with the chip interface; the test interface is used for being electrically connected with a connector of the analysis equipment so as to transmit the signal to be tested to the analysis equipment; the test interface is correspondingly arranged with the chip interface in the direction perpendicular to the test platform;

and the test base is arranged at the position, corresponding to the test interface, of the second surface of the test platform and is used for fixing the joint of the analysis equipment during testing.

2. The device of claim 1, wherein the opposite sides of the test interface are respectively provided with a plurality of first test points and a plurality of second test points, and the plurality of first test points positioned on one side of the test interface and the plurality of second test points positioned on the other side of the test interface are distributed in a central symmetry manner; the plurality of second test points positioned on one side of the test interface and the plurality of first test points positioned on the other side of the test interface are distributed in a central symmetry manner.

3. The apparatus of claim 2, wherein the chip under test is a dual channel chip, the first test point is for testing a first channel of the dual channels of the chip under test, and the second test point is for testing a second channel of the dual channels of the chip under test;

when the first channel of the chip to be tested is tested, the connector of the analysis equipment is inserted into the test interface to be electrically connected with the first test point; and when the second channel of the chip to be tested is tested, the connector of the analysis equipment is inserted into the test interface to be electrically connected with the second test point after rotating 180 degrees.

4. A device according to claim 2 or 3, wherein the test base comprises:

a frame body surrounding an opening formed therethrough in a direction perpendicular to the test platform, one side of the frame body being connected to the second surface of the test platform, the frame body surrounding the test interface such that the test interface is exposed from the opening;

the plurality of connecting pieces are arranged on the frame body and comprise first connecting parts, and the first connecting parts extend from one side of the frame body to a direction away from the test platform and are used for being connected with the connectors of the analysis equipment;

The first connecting parts of the connecting pieces are distributed in a central symmetry mode, so that the connector of the analysis equipment can be connected with the first connecting parts after rotating 180 degrees.

5. The device of claim 4, wherein a first mounting groove and a second mounting groove which are distributed in a central symmetry manner are further formed on one side of the frame body, which is close to the test platform;

the test base further comprises a fool-proof piece, the fool-proof piece is detachably arranged in the first mounting groove or the second mounting groove, the top surface of the fool-proof piece is flush with the surface of the frame body, which is close to the test platform, and the fool-proof piece protrudes out of the inner wall of the frame body.

6. The device of claim 5, wherein the fool-proof member comprises a fixing portion and a fool-proof portion connected to each other, the fixing portion and the fool-proof portion each extend in a direction away from the test platform, the fixing portion is detachably mounted in the first mounting groove or the second mounting groove, a top surface of the fixing portion is flush with a surface of the frame body, which is close to the test platform, and the fool-proof portion protrudes from an inner wall of the frame body and is located in the opening.

7. The apparatus as recited in claim 1, further comprising:

the chip testing seat is detachably arranged on the chip interface and is electrically connected with the chip interface and used for being electrically connected with the chip to be tested.

8. A test system comprising an analysis device and a chip test apparatus; the analysis equipment comprises a connector which is electrically connected with the chip testing device;

the chip testing device comprises:

the chip interface is arranged on the first surface of the test platform and is electrically connected with the test platform; the chip interface is used for being electrically connected with a chip to be tested, and transmitting the test signal to the chip to be tested so that the chip to be tested generates a signal to be tested;

the test interface is arranged on the second surface of the test platform and is electrically connected with the chip interface; the test interface is electrically connected with the connector of the analysis equipment so as to transmit the signal to be tested to the analysis equipment;

the test interface is correspondingly arranged with the chip interface in the direction perpendicular to the test platform;

And the test base is arranged at the position, corresponding to the test interface, of the second surface of the test platform and is used for fixing the joint of the analysis equipment.

9. The system of claim 8, wherein the opposite sides of the test interface of the chip test device are respectively provided with a plurality of first test points and a plurality of second test points, and the plurality of first test points positioned on one side of the test interface and the plurality of second test points positioned on the other side of the test interface are distributed in a central symmetry manner; the plurality of second test points positioned on one side of the test interface and the plurality of first test points positioned on the other side of the test interface are distributed in a central symmetry manner;

the chip to be tested is a double-channel chip, and the connector is inserted into the test interface, connected with the first test point and used for testing a first channel of the chip to be tested; and the connector is inserted into the test interface after rotating 180 degrees, is connected with the second test point and is used for testing the second channel of the chip to be tested.

10. The system of claim 8, wherein the signal under test is an address command signal of the chip under test.