CN116320369A

CN116320369A - Double-deserializing circuit device based on FPGA

Info

Publication number: CN116320369A
Application number: CN202211094589.7A
Authority: CN
Inventors: 钟岳良; 林浩; 夏远洋; 李长水
Original assignee: Kunshan Ruanlongge Automation Technology Co ltd
Current assignee: Kunshan Ruanlongge Automation Technology Co ltd
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2023-06-23

Abstract

The invention discloses a circuit device of a base FPGA double-deserializing circuit, which can use two deserializing schemes of TI954 and MAX9296 which are mainstream in the current industry, and simultaneously comprises a storage and an FPGA processing chip; the FPGA processing chip comprises a USB3.0 transceiving module, a MIPI DPHY IP decoding module, a DDR3 storage read-write module, an I2C IP module, an image processing module, a power supply module, a current monitoring module and an FX3 module; the memory is used for storing the collected image information, the FX3 module is connected between the FPGA and the upper computer, and is used for transmitting the image information and the test information which are received and processed by the image data transmitted from the coaxial camera data to the upper computer through the USB3.0, and simultaneously, the USB3.0 is used for transmitting an I2C control signal, configuring the information of each path of voltage chip in the test device and remotely configuring the information of the image quality in the camera through the deserializing chip; the FPGA can also judge error frame information of image transmission, error rate conditions, power consumption and the like in real time and upload the error frame information to the PC.

Description

Double-deserializing circuit device based on FPGA

Technical Field

The invention relates to the field of vehicle-mounted camera testing, in particular to a vehicle-mounted double-deserializing-based testing device.

Background

With the development of communication technologies such as 5G, L2, L3 and L4 unmanned and auxiliary driving technologies become standard, and the application of the technology to vehicle-mounted cameras is more and more, such as face recognition in a vehicle, 360-degree panorama, blind area monitoring, fatigue recognition, emergency braking triggering, driver parking assistance and the like. However, the production of these front-loading vehicle-mounted cameras needs to meet the requirements of the vehicle-gauge level, and the cameras need to identify people, vehicles and objects, so the requirements on definition and pixels of the cameras are also increasing continuously, and therefore, the vehicle-mounted cameras transmit from the original analog transmission to the present digital coaxial transmission, and the data transmission of the camera Sensor also outputs from the original DVP to the present MIPI output. However, in many kinds of serialization chips, the most dominant serialization deserialization chip has TI and MAXIM, other families such as SONY and OV deserialization chips are gradually introduced, multiple serialization deserialization chips lead to repeated switching of test tools when producing cameras with different serialization deserialization, and particularly under the large background of core missing, terminal clients do not have to force the same chip provider to deserialize chips, and protocols among different deserialization chips are not compatible, and one serialization chip can only use the deserialization chip of the family to deserialize serial signals. Under such conditions we provide a deserializing circuit arrangement that can use multiple deserializing chips.

The circuit is suitable for serial deserialization of a single camera, is applied to AA, focusing and station position detection of the single camera, and can also be used in parallel for testing the aging test station positions of 16 cameras.

Disclosure of Invention

Aiming at the technical problems, the invention aims at: the circuit device of the double-deserializing circuit is convenient for a production line to avoid frequent switching, and is based on an FPGA (XC 7A 75T).

The technical solution of the invention is realized as follows: a double-deserializing circuit device based on an FPGA comprises an FPGA processing chip, an FX3 module and a double-chip serial decoding circuit module; the FPGA processing chip comprises a USB3.0 transceiving module, a MIPI DPHY IP decoding module, a DDR3 storage read-write module and an I2C IP module; the DDR3 storage read-write module is used for storing the acquired image information or calculation results; the I2C IP module carries out data configuration on the double-chip serial decoding circuit module, the double-chip serial decoding circuit module receives image information of a vehicle-mounted camera module on a vehicle, deserializes the image information into MIPI signals through the MIPI DPHY IP decoding module, and stores the MIPI signals into the DDR3 storage read-write module; and the FPGA processing chip uploads the image data in the DDR3 to the PC according to the transmission bandwidth of the FX3 module.

Preferably, the dual-chip serial decoding circuit module comprises two decoding chips TI954 and MAX 9296.

Preferably, the I2C IP module monitors the power supply current of the vehicle-mounted camera module in real time through the current monitoring module and reads the power consumption condition of the vehicle-mounted camera module; the I2C IP module respectively controls the voltage of the FPGA processing chip and the voltage of the vehicle-mounted camera module through the power supply module and the POC power supply circuit.

Preferably, the dual-chip serial decoding circuit module is connected to the vehicle-mounted camera module through a coaxial switch circuit, the vehicle-mounted camera module is powered by a POC power supply circuit, the POC power supply circuit supports 4.5V-18V voltage, and the 16W camera works normally; the POC power supply circuit is connected with the dual-chip serial decoding circuit module, and image signals of the vehicle-mounted camera shooting module are transmitted to the dual-chip serial decoding circuit module through the coaxial switch circuit.

Preferably, the coaxial switching circuit is connected with the vehicle-mounted camera module through a coaxial line and a coaxial interface, and the coaxial interface comprises a single coaxial POC (FAKRA) interface or a single STP (HSD) interface; the in-line switching circuit supports the acquisition of images in excess of 8m 30fps from time to time.

Preferably, the FPGA processing chip further comprises an error frame detection module, and the error frame detection module judges the error frame generation condition of the image in real time.

Preferably, the FPGA processing chip further comprises an image processing module and a non-processing transmitting module, and the image processing module and the non-processing transmitting module are respectively and electrically connected to the DDR3 memory read-write module; the image processing module uploads the image local data or the image after interlacing sampling to the PC, the non-processing transmitting module uploads the original image to the PC, and the image processing module and the non-processing transmitting module operate alternatively, so that the time for transmitting the image and the CPU occupation for displaying are reduced.

Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:

the double-deserializing circuit device based on the FPGA provides a method for transmitting image data to a PC memory in real time by a plurality of vehicle-mounted MIPI serial coaxial modules, supports deserializing of a plurality of decoding chips, and selects different deserializing chips through software. The PC acquires an effective frame picture (including a picture used by a RAW picture after interpolation or a local algorithm) or carries out partial operation to the FPGA, and the FPGA can be used for carrying out real-time monitoring and operation on synchronous data of a camera, frame synchronous level of the effective frame data, transmission error rate, code comparison, abrupt change of current and the like. The method greatly reduces the use of the CPU of the computer, greatly improves the speed of interpolation operation and effective data acquisition, and avoids the consumption of the CPU of the computer under the condition that an upper computer does not acquire effective frames, thereby reserving more operation time and bandwidth for the operation required by the PC CPU.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the description of the embodiments of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the contents of the embodiments of the present invention and these drawings without inventive effort for those skilled in the art.

FIG. 1 is a block diagram of an FPGA-based double deserializing circuit apparatus according to the present invention;

fig. 2 is a connection diagram of an FPGA of the FPGA-based double-deserializing circuit apparatus and a preferred embodiment of the double-deserializing chip of the present invention.

Fig. 3 is a POC power circuit diagram of an FPGA-based double deserializing circuit apparatus of a preferred embodiment of the present invention.

Fig. 4 is a connection diagram of DDR3 of the FPGA-based double deserializing circuit apparatus of the present invention and a preferred embodiment of the FPGA.

FIG. 5 is a diagram of the connection of an FPGA of the FPGA-based dual deserializing circuit apparatus of the present invention with a preferred embodiment of FX 3.

Fig. 6 is a connection diagram of a preferred embodiment of FPGA and deserializing chip MIPI of the FPGA-based double deserializing circuit apparatus of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, the invention discloses a circuit device of a double-deserializing circuit based on an FPGA, which comprises 2 pieces of DDR3 memories and an FPGA (XC 7a 75T) processing chip electrically connected with the memories, wherein the 2 pieces of DDR3 memories are mainly used for storing collected image information and processed image data or processing results.

Further, as shown in fig. 1, fig. 1 is a schematic structural diagram of the FPGA (XC 7a 75T) processing chip, and specifically, the FPGA (XC 7a 75T) processing chip includes a USB3.0 transceiver module, a no-processing transmitting module, an image processing module, an error frame detecting module, a DPHY IP decoding module (supporting dual camera transmission), and an I2C IP module; the 2 pieces of DDR3 storage are used for storing the collected image information, the image processing module is used for processing the image information in the DDR3 storage and sending an image processing result, image error frame detection information and image data to the PC through the USB3.0 according to a control command of the PC end.

The FPGA chip of the embodiment of the invention can be developed by adopting a conventional FPGA and using an FPGA program, is suitable for FPGA models such as XCZU4EG, XCZU4CG and the like, but is not limited to specific chip models.

In the present embodiment, the DDR4 memory may include DDR3 or the like, and the present invention is not limited thereto.

The double-deserializing circuit device based on the FPGA can test the integrity of frame synchronous signals and frame data through the FPGA. The FPGA provides TI954 and MAX9296 two deserializing chip decoding, the selection of TI954 and MAX9296 is carried out through software to select IO switching, and the high-speed switch chip selectively switches MIPI signals output by TI954 and MAX9296 to be connected with the FPGA through a MC20901 chip (converting MIPI into LVDS signals). The TI954 or the MAX9296 can be subjected to data configuration through the I2C, and eye pattern data can be monitored by reading an eye pattern register in a deserializing chip to detect the signal quality in the transmission process.

The I2C IP module can monitor the power supply current of the vehicle-mounted camera in real time through the current monitoring module and read the power consumption condition of the camera; and the voltage of the whole device and the POC power supply voltage are respectively controlled through the power supply module and the POC power supply circuit.

The scheme is not limited to two decoding chips of TI954 and MAX9296, is not limited to the chips of TI and MAXim, can also comprise decoding chips related to SONET, OV, even more manufacturers in future and the like, is not limited to support two different decoding chips, can be 3 or 4, and is switched by using software by using different decoding chips.

In one preferred embodiment, we provide a scheme that supports both POC power supply and double deserialization chip signal decoding, the decoded MIPI signal is converted into an LVDS signal by the MC20901 signal and received by the FPGA, and the MIPI IP check image data signal in the FPGA is decoded and stored in the DDR3 memory. The implementation mode not only supports the existing double decoding chips, but also supports most of the deserializing chips on the market, and the selection of the deserializing chips is determined according to the serial transmission chip of the tested camera. In this preferred embodiment: the serial deserializing module (LVDS coaxial-MIPI module) is electrically connected between the FPGA (XC 7A 75T) and 1 coaxial POC (FAKRA) interface or 1 STP (HSD) interface, and the chip for converting TI954 LVDS data into MIPI is used for serial transmission relative serial deserializing with camera end TI953 and the like in the design. Meanwhile, a chip for converting MAX9296 LVDS data into MIPI is also used, and the chip is subjected to serial deserialization relative to serial transmission of a camera head MAX9295 and the like.

In one preferred embodiment, the MIPI DPHY module supports simultaneous transmission of two camera data by one MIPI, and one of the camera data is transmitted through a MIPI virtual channel. In the decoding of the FPGA, the data of the two cameras are decoded separately.

In one preferred embodiment, the error frame detection module detects the integrity of the whole frame of the image data, the integrity of each line of data, the frame synchronization signal, the error data comparison and the like; the method and the device can meet the requirement that the client performs long-time reliability test on the camera shooting product, and ensure the safety of image identification of the product in the automobile driving process and under different climatic conditions. The current monitoring module is used for monitoring the current and the voltage of the camera in real time outside the FPGA (XC 7A 75T) module so as to ensure that the damage of high temperature, low temperature and the like can be used for monitoring the abnormal problems of the chip, welding and the like of the camera.

In one preferred embodiment, the FPGA uploads the image data to the PC via FX3 (cyclic ress 3014), while we can transmit related data instructions via USB3.0, configuring the voltage configuration of the device, chip initialization in the device, mode selection, image quality (noise, frame rate, color, etc.), deserializing chip initialization, etc. via the I2C/SPI protocol by the FPGA.

The DPHY IP core in the circuit device of the FPGA double-deserializing circuit supports decoding of multiple formats such as RAW8, RAW10, RAW12, YUV422, YUV420 and the like, and the IP core supports transmission of MIPI data channel single-camera image data and MIPI virtual channel image data. So that one MIPI channel supports simultaneous transmission by two cameras.

The circuit device of the FPGA double-deserializing circuit supports 4.5V-18V POC power supply software adjustable support. The POC voltage is remotely supplied to the in-vehicle camera module via a single on-axis POC (FAKRA) interface or a single STP (HSD) interface. The camera module uses different types of serial deserializing chips to be selectively connected into a deserializing circuit (TI 954 or MAX 9296) matched with the camera module through a capacitor (0.1 uf). The withstand voltage value of the capacitor is 25V, and the purpose is to isolate POC voltage breakdown deserializing chips.

The circuit device of the FPGA double-deserializing circuit is combined with fig. 2, and a connection diagram of two different decoding chips, namely TI954 and MAX9296, is provided, and the two decoding chips support 30fps image transmission of an 8M YUV camera, and can receive high-speed image data decoding of 6Gbps at maximum. Decoding chips corresponding to TI954 and MAX9296 are selected according to the requirement, MIPI signals input by TI954 and MAX9296 are accessed to a U39 switch chip, and the decoding chips are selected and output according to the switch chip and are connected with the FPGA through an MC20901 chip.

The circuit device of the FPGA double-deserializing circuit is combined with fig. 6, a connection diagram of the MC20901 chip and the FPGA is provided, and the FPGA (XC 7A 75T) cannot directly receive MIPI signals, wherein the MIPI signals are divided into signals in two modes of HS and LP, and the MC20901 is used for separating and converting data in the two different modes into corresponding LVDS signals and connecting the corresponding LVDS signals with the FPGA. However, in some high-end FPGAs, some FPGAs incorporate this function, and therefore, no external MC20901 chip is required.

The circuit device of the FPGA double-deserializing circuit is a connection diagram of an FPGA and 2 DDR3 chips, and the DDR3 is used for storing image data decoded by the MIPI IP core, and if DDR3 is not used as a cache because of different transmission rates of different cameras, the situation of frame loss or data error occurs when the image input rate of the cameras is higher than USB 3.0. The DDR3 buffer is also used to better improve the utilization of the USB3.0 channel.

The circuit device of the FPGA double-deserializing circuit is a connection diagram of the FPGA and FX3 and is used for usb3.0 transmission with a PC in combination with FIG. 5.

The circuit device of the FPGA double-deserializing circuit is combined with fig. 3, and a POC power supply circuit is provided, the circuit provides a larger voltage adjusting range from 4.5V to 18V, and meets the power supply requirements of different vehicle-mounted cameras on the market, wherein the voltage adjustment is controlled by the FPGA through I2C, and an I2C instruction of the FPGA is issued and adjustable by a PC end through USB 3.0.

The circuit device of the base FPGA double-deserializing circuit is applicable to support single-module detection and support the FPGA to carry out frame measurement on an error frame. The problem that the production line needs to use different types of deserializing plates when the production line is used for coping with different types of camera modules is avoided, the production line is frequently switched, the utilization rate of equipment is improved, and the investment cost of vehicle-mounted test equipment is reduced.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims

1. The utility model provides a two deserialization circuit arrangement based on FPGA which characterized in that: the device comprises an FPGA processing chip, an FX3 module and a dual-chip serial decoding circuit module; the FPGA processing chip comprises a USB3.0 transceiving module, a MIPIDPHY IP decoding module, a DDR3 storage read-write module and an I2C IP module; the DDR3 storage read-write module is used for storing the acquired image information or calculation results; the I2C IP module carries out data configuration on the double-chip serial decoding circuit module, the double-chip serial decoding circuit module receives image information of a vehicle-mounted camera module on a vehicle, deserializes the image information into MIPI signals through the MIPIDPHY IP decoding module, and stores the MIPI signals into the DDR3 storage read-write module; and the FPGA processing chip uploads the image data in the DDR3 to the PC according to the transmission bandwidth of the FX3 module.

2. The FPGA-based double deserializing circuit apparatus of claim 1, wherein: the dual-chip serial decoding circuit module comprises TI954 and MAX9296 decoding chips.

3. The FPGA-based double deserializing circuit apparatus of claim 1, wherein: the I2C IP module monitors the power supply current of the vehicle-mounted camera module in real time through the current monitoring module and reads the power consumption condition of the vehicle-mounted camera module; the I2C IP module respectively controls the voltage of the FPGA processing chip and the voltage of the vehicle-mounted camera module through the power supply module and the POC power supply circuit.

4. The FPGA-based double deserializing circuit apparatus of claim 3, wherein: the dual-chip serial decoding circuit module is connected to the vehicle-mounted camera module through the coaxial switch circuit, the vehicle-mounted camera module is powered by the POC power supply circuit, the POC power supply circuit supports 4.5V-18V voltage, and the 16W camera works normally; the POC power supply circuit is connected with the dual-chip serial decoding circuit module, and image signals of the vehicle-mounted camera shooting module are transmitted to the dual-chip serial decoding circuit module through the coaxial switch circuit.

5. The FPGA-based double deserializing circuit apparatus of claim 4, wherein: the coaxial switching circuit is connected with the vehicle-mounted camera module through a coaxial line and a coaxial interface, and the coaxial interface comprises a single coaxial POC (FAKRA) interface or a single STP (HSD) interface; the in-line switching circuit supports the acquisition of images in excess of 8m 30fps from time to time.

6. The FPGA-based double deserializing circuit apparatus of claim 1, wherein: the FPGA processing chip also comprises an error frame detection module, and the error frame detection module judges the generation condition of the error frame of the image in real time.

7. The FPGA-based double deserializing circuit apparatus of claim 1, wherein: the FPGA processing chip further comprises an image processing module and a non-processing sending module, and the image processing module and the non-processing sending module are respectively and electrically connected to the DDR3 storage read-write module; the image processing module uploads the image local data or the image after interlacing sampling to the PC, the non-processing transmitting module uploads the original image to the PC, and the image processing module and the non-processing transmitting module operate alternatively, so that the time for transmitting the image and the CPU occupation for displaying are reduced.