CN116318610B - Finite time secret communication method and system of variable fractional order chaotic system - Google Patents

Finite time secret communication method and system of variable fractional order chaotic system Download PDF

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CN116318610B
CN116318610B CN202310071949.XA CN202310071949A CN116318610B CN 116318610 B CN116318610 B CN 116318610B CN 202310071949 A CN202310071949 A CN 202310071949A CN 116318610 B CN116318610 B CN 116318610B
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variable fractional
variable
fractional order
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error
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CN116318610A (en
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李瑞鸿
甘勤涛
陈鹏
杨婧
孟明强
黄欣鑫
彭舒
毛琼
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Army Engineering University of PLA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
    • H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/088—Usage controlling of secret information, e.g. techniques for restricting cryptographic keys to pre-authorized uses, different access levels, validity of crypto-period, different key- or password length, or different strong and weak cryptographic algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application discloses a finite time secret communication method and a finite time secret communication system of a variable fractional order chaotic system, and relates to the field of secret communication. Constructing a variable fractional order driving system model and a variable fractional order response system model; setting an error function based on the variable fractional order driving system module and the variable fractional order response system model, and constructing a variable fractional order error system; constructing a finite time consistency controller according to the variable fractional order error system; estimating a stopping time under the finite time consistency controller; the dynamic behavior of the driving and responding systems is consistent during the rest time. The application can effectively encrypt the information with high complexity and freedom degree.

Description

Finite time secret communication method and system of variable fractional order chaotic system
Technical Field
The application relates to the field of secret communication, in particular to a finite time secret communication method and a finite time secret communication system of a variable fractional order chaotic system.
Background
The chaotic system is a nonlinear deterministic system which exhibits complex, broad-spectrum, noise-like and unpredictable behavior and is particularly suitable for the field of secret communication. The central idea is to encrypt the information signal by directly adding a chaotic signal to the driving system. After the response system receives the information-bearing signal and after some signal processing operations have been performed, decryption takes place. If the dynamic behavior of the drive and response systems are consistent, the original information signal will be restored.
It is noted that current research efforts have generally utilized constant fractional derivatives to provide more parameters for the security of information and correspondingly enhance the key space of encryption applications, but still fail to encrypt information with high complexity and freedom. Thus, a variable fractional derivative is introduced, whose order is a function of the dependent or independent variable. The degree of freedom of the order is increased, so that the variable-fraction order chaotic system further increases the safety of information signals, widens the key space and becomes a powerful tool for analyzing more complex information signals.
In practice, it is often required that the security system can encrypt and decode in a limited time. This requirement has led to the interest of students in studying the limited time stability of fractional order chaotic systems. At present, some achievements are achieved for research of limited time consistency of a fractional order chaotic system, but the research is mainly focused on a constant fractional order chaotic system. Because the order of the variable-fraction chaotic system is a function, the technical method for consistent dynamics in the finite time of the Chang Fenshu-order chaotic driving and responding system is not suitable for the variable-fraction chaotic system any more, the current research work generally provides more parameters for the safety of information by utilizing a constant fractional derivative, correspondingly enhances the key space of encryption application, but still cannot effectively encrypt the information with high complexity and freedom degree.
Disclosure of Invention
The application aims to provide a limited time secret communication method and a system of a variable fractional order chaotic system, which are used for solving the problem that information with high complexity and degree of freedom cannot be effectively encrypted.
In order to achieve the above object, the present application provides the following solutions:
a finite time secret communication method of a variable fractional order chaotic system comprises the following steps:
constructing a variable fractional order driving system model and a variable fractional order response system model;
setting an error function based on the variable fractional order driving system module and the variable fractional order response system model, and constructing a variable fractional order error system;
constructing a finite time consistency controller according to the variable fractional order error system;
estimating a stopping time under the finite time consistency controller; the dynamic behavior of the driving and responding systems is consistent during the rest time.
Optionally, the variable fractional order driving system model is:
wherein ,fractional derivative for generalized Caputo variation; alpha (t) is the derivative order; x is x 0 (t) is the state of the variable fractional drive system; p is p c A first constant with respect to capacitive resistance; x is x 01 (t) is the voltage of a first capacitor in the variable fractional drive system; x is x 02 (t) is the voltage of a second capacitor in the variable fractional drive system; g (x) 01 (t)) is a function of the capacitor voltage in the variable fractional drive system; x is x 03 (t) is the power-on in the variable fractional order drive systemA sensed current; q c Is a constant with respect to inductance; w (w) c Is a second constant with respect to resistance and inductance.
Optionally, the variable fractional order response system model is:
wherein ,xi (t) is the state of the variable fractional response system; x is x i1 (t) is the voltage of a first capacitor in the variable fractional order response system; x is x i2 (t) is the voltage of a second capacitor in the variable fractional order response system; g (x) i1 (t)) is a function of the capacitance voltage in the variable fractional response system; x is x i3 (t) is the current through the inductor in the variable fractional order response system; u (u) i (t) is a finite time coherence controller.
Optionally, the variable fractional order error system is:
wherein ,ei (t) is an error function; e, e i1 (t) is the voltage of a first capacitor in the variable fractional error system; e, e i2 (t) is the voltage of a second capacitor in the variable fractional error system; g (e) i1 (t)) is a function of the capacitance voltage in the variable fractional error system; e, e i3 (t) is the current through the inductance in the variable fractional error system.
Optionally, the finite time coherence controller is:
wherein ,a controller designed for a dynamic event triggering mechanism; />A controller to achieve a finite time agreement; i e i (t) || is e i 2 norms of (t).
Optionally, the rest time is
wherein ,is the rest time; lambda (lambda) 2 Is a third constant; alpha 1 Is the lower bound of α (t); alpha 2 Is the upper bound of α (t); b is Beta function; />Is a first constant; />Is a fourth constant; />Is Lyapunov function->A value at an initial time 0; and ψ is a second constant.
A finite time secure communication system of a variable fractional order chaotic system, comprising:
the driving system and response system module construction module is used for constructing a variable fractional order driving system model and a variable fractional order response system model;
the variable fractional order error system construction module is used for setting an error function based on the variable fractional order driving system module and the variable fractional order response system model to construct a variable fractional order error system;
the finite time consistency controller construction module is used for constructing a finite time consistency controller according to the variable fractional order error system;
the stopping time estimation module is used for estimating the stopping time under the finite time consistency controller; the dynamic behavior of the driving and responding systems is consistent during the rest time.
Optionally, the variable fractional order driving system model is:
wherein ,fractional derivative for generalized Caputo variation; alpha (t) is the derivative order; x is x 0 (t) is the state of the variable fractional drive system; p is p c A first constant with respect to capacitive resistance; x is x 01 (t) is the voltage of a first capacitor in the variable fractional drive system; x is x 02 (t) is the voltage of a second capacitor in the variable fractional drive system; g (x) 01 (t)) is a function of the capacitor voltage in the variable fractional drive system; x is x 03 (t) is the current through the inductor in the variable fractional order drive system; q c Is a constant with respect to inductance; w (w) c Is a second constant with respect to the inductance and resistance.
An electronic device comprising a memory for storing a computer program and a processor that runs the computer program to cause the electronic device to perform the finite time secure communication method of the variable fractional order chaotic system described above.
A computer readable storage medium storing a computer program which when executed by a processor implements the finite time secure communication method of a variable fractional order chaotic system described above.
According to the specific embodiment provided by the application, the application discloses the following technical effects: the application provides a finite time secret communication method and a finite time secret communication system of a variable fractional order chaotic system, wherein the order in the variable fractional order derivative is a function, signals generated by a variable fractional order driving system and a variable fractional order response system can change along with the change of time, the key space of the signals is increased, the encryption of signals with high degrees of freedom is more advantageous, the decryption difficulty of the signals is also increased, and the secret performance is improved. The application can further increase the safety of the information signal, widen the key space, and realize the encryption and decryption of the information signal in a limited time.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for secure communication over a finite time period of a variable fractional order chaotic system provided by the present application;
FIG. 2 is a schematic diagram of a dynamic event triggering mechanism according to the present application;
FIG. 3 is a schematic diagram of a transmission process according to the present application;
FIG. 4 is a circuit diagram of components of an error function provided by the present application;
FIG. 5 is a circuit diagram of a selection chain type fractional order unit with an original FC input of 1 according to the present application;
FIG. 6 is a circuit diagram of a selection chain type fractional order unit with an original FC input of 2 according to the present application;
FIG. 7 is a schematic circuit diagram of the error function signal under the variable fractional order operator provided by the present application;
FIG. 8 shows the E-type structure of the present application i (t)||，||e i (t)|| p Is a schematic diagram of the circuit;
FIG. 9 is a schematic diagram of a dynamic event trigger mechanism according to the present application;
FIG. 10 shows the present applicationIs a schematic diagram of the circuit;
FIG. 11 is a diagram of a control signal provided by the present applicationIs a schematic diagram of the circuit;
FIG. 12 is a diagram of a control signal provided by the present applicationIs a schematic diagram of the circuit;
FIG. 13 is a diagram illustrating a control protocol u according to the present application i A schematic circuit diagram of (t);
FIG. 14 is a graph of dynamic event trigger constants provided by the present application;
fig. 15 is a system state diagram provided by the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The application aims to provide a limited time secret communication method and a system of a variable fractional order chaotic system, which can effectively encrypt information with high complexity and degree of freedom.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
Example 1
Fig. 1 is a flowchart of a finite time secret communication method of a variable fractional order chaotic system provided by the application, and as shown in fig. 1, the application provides a finite time secret communication method of a variable fractional order chaotic system, which comprises the following steps:
step 101: and constructing a variable fractional order driving system model and a variable fractional order response system model.
In practical application, the variable fractional order driving system model is as follows:
wherein ,fractional derivative for generalized Caputo variation; beta (t) is the derivative order; x is x 0 (t) is the state of the variable fractional drive system; p is p c A first constant with respect to capacitive resistance; x is x 01 (t) is the voltage of a first capacitor in the variable fractional drive system; x is x 02 (t) is the voltage of a second capacitor in the variable fractional drive system; g (x) 01 (t)) is a function of the capacitor voltage in the variable fractional drive system; x is x 03 (t) is the current through the inductor in the variable fractional order drive system; q c Is a constant with respect to inductance; w (w) c Is a second constant with respect to the resistive inductance.
In practical application, the variable fractional order response system model is as follows:
wherein ,xi (t) is the state of the variable fractional response system; x is x i1 (t) is the voltage of a first capacitor in the variable fractional order response system; x is x i2 (t) is the voltage of a second capacitor in the variable fractional order response system; g (x) i1 (t)) is a function of the capacitance voltage in the variable fractional response system; x is x i3 (t) is the current through the inductor in the variable fractional order response system; u (u) i (t) is a finite time coherence controller.
g(x i1 (t))＝-ax i1 (t)+0.5(-b+a)(|x i1 (t)+1|-|x i1 (t) -1|), a, b are fixed parameters of Chua diode; r and R 0 Is a linear resistance which is a resistance of the resistor,R and R0 Is a linear resistance, g (x i1 (t))＝-ax i1 (t)+0.5(-b+a)(|x i1 (t)+1|-|x i1 (t)-1|)。
Step 102: and setting an error function based on the variable fractional order driving system module and the variable fractional order response system model, and constructing a variable fractional order error system.
In practical application, the variable fractional order error system is as follows:
wherein ,ei (t) is an error function; e, e i1 (t) is the voltage of a first capacitor in the variable fractional error system; e, e i2 (t) is the voltage of a second capacitor in the variable fractional error system; g (e) i1 (t)) is a function of the capacitance voltage in the variable fractional error system; e, e i3 (t) is the current through the inductor in the variable fractional error system; error function e i (t)＝x i (t)-x 0 (t)，g(e i1 (t))＝-ae i1 (t)+0.5(-b+a)(|e i1 (t)+1|-|e i1 (t)-1|)。
Step 103: and constructing a finite time consistency controller according to the variable fractional order error system.
In practical application, the finite time consistency controller is:
wherein ,a controller designed for a dynamic event triggering mechanism; />A controller to achieve a finite time agreement; i e i (t) || is e i 2 norms of (t).
In practical application, the error function difference is setIs a monotonically increasing time sequence representing the kth trigger time of node i, +.>Representing the state of the error at the kth trigger time; representing a function established according to a topological connection between nodes, a ij Is an element of the adjacency matrix->a ij >0 means that node i can obtain information from node j; otherwise a ij ＝0，/>Represents a set of nodes with topological connection to node i, < >>Is a control gain matrix; i e i (t) || represents e i 2 norms of (t) ||e i (t)|| p Representation e i (t) the power of p of 2 norms, ||e i (t)|| 1 Representation e i 1 norm of (t), sig representsA sign function.
For the followingThe dynamic event trigger mechanism is determined by the dynamic event trigger mechanism, and is constructed as follows:
the initialization trigger time isThe next trigger time is calculated by the following steps:
in the formula η i Is a constant to be designed, T is the current moment, T is the transposed matrix, and p is more than or equal to 2 and delta i (t) is an auxiliary internal dynamic variable introduced, ||delta i (t) || represents δ i 2 norms of (t) |delta i (t)|| p Representing delta i (t) the p-th power of 2 norms, delta i The dynamic equation of (t) is:
wherein ,θ i ，/>is positive constant, xi i (δ i (t)) is a description function delta i The nonlinear function of the dynamic behavior satisfies the following assumption:
for arbitrary constant u 1 ,u 2 There is a constant ρ 1i ，ρ 2i So that
Fig. 2 is a schematic diagram of a dynamic event triggering mechanism provided in the present application, as shown in fig. 2.
Step 104: estimating a stopping time under the finite time consistency controller; the dynamic behavior of the driving and responding systems is consistent during the rest time.
In practical application, under the proposed finite time coherence controller, if there is a constantSo that the inequality is
Is established inIs a lyapunov function, the variable fractional order chaotic error system can be consistent within a limited time. This means that in secure communication, decryption of the information signal can be achieved in a limited time.
The calculation method for the estimate of the rest time is:
setting auxiliary functionsThen the first time period of the first time period,
based on inequalityAnd to inequality ofTwo sides integrate simultaneously to get->
in the formula ,α1 and α2 Is the lower and upper bounds of alpha (t),Γ (t) is a gamma function. />Representation->A value at an initial time 0.
Order theThen->
in the formula ,representation->At the value of initial time 0, by solving the above equation, the rest time is:
similarly, toThe rest time is:
wherein ,λ2 Is a third constant; b is Beta function;is a first constant; />Is a fourth constant; />Is Lyapunov function->A value at an initial time 0; and ψ is a second constant.
Verifying the validity of the control protocol:
constructing a Lyapunov function:
using inequalityCalculating the derivative of the Lyapunov function, the following can be obtained:
is obtained after the enlarging and shrinking finishingThe validity of a limited time consistent distributed hybrid control protocol may be illustrated.
Ciphertext signal transmission process and simulation experiment:
in order to more intuitively show the effectiveness and applicability of the method provided by the application, a ciphertext transmission process and a computer simulation experiment are as follows:
1) Ciphertext signal transmission process principle: the ciphertext signal may be an image, sound, video, or the like. When the ciphertext signal is transmitted, the variable fractional order driving system outputs a chaotic driving signal, and the variable fractional order response system and the designed finite time consistency controller output a chaotic response signal. The chaotic driving signal generates an encryption function to mask an original information signal to generate a secret key, the secret key is transmitted to a decryption function generated by a response signal through a channel, the response output signal and the secret key are decrypted, and a decrypted information signal is generated, so that the encryption and decryption process of the ciphertext signal is realized within a limited time. Fig. 3 is a schematic diagram of a transmission process provided by the present application, as shown in fig. 3.
2) And (5) performing computer simulation experiments.
Consider a 3-dimensional variable fractional order chaotic system comprising 3 nodes. Fig. 4 is a circuit diagram of components of an error function provided by the present application, as shown in fig. 4. Since the order of the variable fractional order operator is a function of time, the application assumes that the function is bounded by a, with upper and lower bounds of α, respectively 1 ，α 2 . When (when)Then α (t) =α 1 Otherwise α (t) =α 2 . For the order value alpha 1 ，α 2 The selection chain type fractional order unit circuit of the application is shown in fig. 5-6.
Based on the above analysis, fig. 7 is a schematic circuit diagram of the error function signal under the variable fractional order operator provided by the present application, as shown in fig. 7. Note that in fig. 7, the original FC represents a fractional order integration operation on the error function, and inputs 1 and 2 thereof represent fig. 5 and 6, respectively.
The control protocol and the I E provided by the application i (t)||，||e i (t)|| p In relation, based on the error signal, ||e i (t)||，||e i (t)|| p The circuit schematic of (a) is shown in fig. 8, in which original M represents p i And (t) | performing p times of product operation.
For the designed dynamic event trigger mechanism, the schematic diagram is shown in FIG. 9, in which the element memory has the functions of storing and transmitting trigger dataThe resulting trigger moment can be transmitted to an error signal. After obtaining the error signal of the trigger time, obtaining a control signal through communication connection among nodesThe schematic diagram is shown in fig. 10. By a similar operation +.>And +.>The circuit implementation of which is shown in figures 11 and 12. Care of-> The circuit implementation principle of the control protocol ui (t) is thus shown in fig. 13 based on the above-described circuit implementation diagram.
Selecting parameter p c ＝10.763，q c ＝15.599811，w c ＝0.13，α i (t)＝0.97+0.02sin(t)，g(x i1 (t))＝-0.3559x i1 (t)+0.5(-1.2938+0.3559)(|x i1 (t)+1|-|x i1 (t) -1|). The initial value is selected as x 0 (0)＝(5.280，-4.896，-6.432) T ，x(t)＝(-7.96，6.9965，-3.4327，-5.2035，5.59048，7.32655，-3.812，-5.324，-3.195) T 。
For the controller, selecting trigger parametersη 1 ＝0.06，η 2 ＝0.08，η 3 ＝0.052，/>θ 1 ＝1.99，θ 2 ＝1.383，θ 1 ＝1.595， ξ 1 (δ 1 (t))＝sin(0.77δ 1 (t))，ξ 2 (δ 2 (t))＝cos(0.77δ 1 (t))，ξ 3 (δ 3 (t))＝0.77δ 1 (t) and gain matrix->
Under the above parameters, the rest time was calculated as 4.635. Fig. 14 is a dynamic event trigger constant chart provided by the present application, and fig. 15 is a system state chart provided by the present application, as shown in fig. 14-15.
Example two
In order to implement a corresponding method of the above embodiment to achieve the corresponding functions and technical effects, a finite time secure communication system of a variable fractional order chaotic system is provided below.
A finite time secure communication system of a variable fractional order chaotic system, comprising:
the driving system and response system module construction module is used for constructing a variable fractional order driving system model and a variable fractional order response system model.
In practical application, the variable fractional order driving system model is as follows:
wherein ,fractional derivative for generalized Caputo variation; alpha (t) is the derivative order; x is x 0 (t) becomesThe state of the fractional order drive system; p is p c A first constant with respect to capacitive resistance; x is x 01 (t) is the voltage of a first capacitor in the variable fractional drive system; x is x 02 (t) is the voltage of a second capacitor in the variable fractional drive system; g (x) 01 (t)) is a function of the capacitor voltage in the variable fractional drive system; x is x 03 (t) is the current through the inductor in the variable fractional order drive system; q c Is a constant with respect to inductance; w (w) c Is a second constant with respect to the resistive inductance.
And the variable fractional order error system construction module is used for setting an error function based on the variable fractional order driving system module and the variable fractional order response system model to construct a variable fractional order error system.
And the finite time consistency controller construction module is used for constructing a finite time consistency controller according to the variable fractional order error system.
The stopping time estimation module is used for estimating the stopping time under the finite time consistency controller; the dynamic behavior of the driving and responding systems is consistent during the rest time.
Example III
The embodiment of the application provides an electronic device which comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor runs the computer program to enable the electronic device to execute the finite-time secret communication method of the variable fractional order chaotic system provided in the embodiment I.
In practical applications, the electronic device may be a server.
In practical applications, the electronic device includes: at least one processor (processor), memory (memory), bus, and communication interface (Communications Interface).
Wherein: the processor, communication interface, and memory communicate with each other via a communication bus.
And the communication interface is used for communicating with other devices.
And a processor, configured to execute a program, and specifically may execute the method described in the foregoing embodiment.
In particular, the program may include program code including computer-operating instructions.
The processor may be a central processing unit, CPU, or specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present application. The one or more processors included in the electronic device may be the same type of processor, such as one or more CPUs; but may also be different types of processors such as one or more CPUs and one or more ASICs.
And the memory is used for storing programs. The memory may comprise high-speed RAM memory or may further comprise non-volatile memory, such as at least one disk memory.
Based on the description of the above embodiments, an embodiment of the present application provides a storage medium having stored thereon computer program instructions executable by a processor to implement the method of any embodiment
The finite time secret communication system of the variable fractional order chaotic system provided by the embodiment of the application exists in various forms, including but not limited to:
(1) A mobile communication device: such devices are characterized by mobile communication capabilities and are primarily aimed at providing voice, data communications. Such terminals include: smart phones (e.g., iPhone), multimedia phones, functional phones, and low-end phones, etc.
(2) Ultra mobile personal computer device: such devices are in the category of personal computers, having computing and processing functions, and generally having mobile internet access capabilities. Such terminals include: PDA, MID, and UMPC devices, etc., such as iPad.
(3) Portable entertainment device: such devices may display and play multimedia content. The device comprises: audio, video players (e.g., iPod), palm game consoles, electronic books, and smart toys and portable car navigation devices.
(4) Other electronic devices with data interaction functions.
Thus, particular embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in the same piece or pieces of software and/or hardware when implementing the present application. It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of a storage medium for a computer include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory or other memory technology, a compact disc read only memory (CD-ROM), a compact disc Read Only Memory (ROM),
Digital Versatile Disk (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices
Or any other non-transmission medium, may be used to store information that may be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular transactions or implement particular abstract data types. The application may also be practiced in distributed computing environments where transactions are performed by remote processing devices that are connected through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present application and the core ideas thereof; also, it is within the scope of the present application to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the application.

Claims (4)

1. A limited time secure communication method of a variable fractional order chaotic system, comprising the steps of:
constructing a variable fractional order driving system model and a variable fractional order response system model; the variable fractional order driving system model is as follows:
wherein ,fractional derivative for generalized Caputo variation; a (t) is the derivative order; x is x 0 (t) is the state of the variable fractional drive system model; p is p c A first constant with respect to capacitive resistance; x is x 01 (t) is the voltage of the first capacitor in the variable fractional drive system model; x is x 02 (t) is the voltage of the second capacitor in the variable fractional drive system model; g (x) 01 (t)) is a function of the capacitance voltage in the model of the variable fractional drive system; x is x 03 (t) is the current through the inductor in the variable fractional drive system model; q c Is a constant with respect to inductance; w (w) c A second constant with respect to the resistive inductance;
the variable fractional order response system model is as follows:
wherein ,xi (t) is the state of the variable fractional response system model; x is x i1 (t) is the voltage of the first capacitor in the variable fractional response system model; x is x i2 (t) is the voltage of the second capacitor in the variable fractional response system model; g (x) i1 (t)) is a function of the capacitance voltage in the model of the system in relation to the variable fractional response; x is x i3 (t) is the current through the inductor in the variable fractional order response system model; u (u) i (t) is a finite time coherence controller;
setting an error function based on the variable fractional order driving system model and the variable fractional order response system model, and constructing a variable fractional order error system;
the variable fractional order error system is as follows:
wherein ,ei (t) is an error function; e, e i1 (t) is the voltage of a first capacitor in the variable fractional error system; e, e i2 (t) is the voltage of a second capacitor in the variable fractional error system; g (e) i1 (t)) is a function of the capacitance voltage in the variable fractional error system; e, e i3 (t) is the current through the inductor in the variable fractional error system;
constructing a finite time consistency controller according to the variable fractional order error system;
the finite time consistency controller is:
wherein ,a controller designed for a dynamic event triggering mechanism; />A controller to achieve a finite time agreement; i e i (t) || is e i 2 norms of (t);
estimating a stopping time under the finite time consistency controller; the dynamic behaviors of the driving and responding systems are consistent in the rest time; the rest time is
wherein ,is the rest time; lambda (lambda) 2 Is a third constant; alpha 1 Is the lower bound of α (t); alpha 2 Is the upper bound of α (t); b is Beta function;is a first constant; />Is a fourth constant; />Is Lyapunov function->A value at an initial time 0; and ψ is a second constant.
2. A finite time secure communication system of a variable fractional order chaotic system, comprising:
the driving system and response system model construction module is used for constructing a variable fractional order driving system model and a variable fractional order response system model;
the variable fractional order driving system model is as follows:
wherein ,fractional derivative for generalized Caputo variation; alpha (t) is the derivative order; x is x 0 (t) is the state of the variable fractional drive system model; p is p c A first constant with respect to capacitive resistance; x is x 01 (t) is the voltage of the first capacitor in the variable fractional drive system model; x is x 02 (t) is the voltage of the second capacitor in the variable fractional drive system model; g (x) 01 (t)) is a function of the capacitance voltage in the model of the variable fractional drive system; x is x 03 (t) is the current through the inductor in the variable fractional drive system model; q c Is a constant with respect to inductance; w (w) c A second constant with respect to the resistive inductance;
the variable fractional order response system model is as follows:
wherein ,xi (t) is the state of the variable fractional response system model; x is x i1 (t) is the voltage of the first capacitor in the variable fractional response system model; x is x i2 (t) is the voltage of the second capacitor in the variable fractional response system model; g (x) i1 (t)) is a function of the capacitance voltage in the model of the system in relation to the variable fractional response; x is x i3 (t) is the current through the inductor in the variable fractional order response system model; u (u) i (t) is a finite time coherence controller;
the variable fractional order error system construction module is used for setting an error function based on the variable fractional order driving system model and the variable fractional order response system model to construct a variable fractional order error system;
the variable fractional order error system is as follows:
wherein ,ei (t) is an error function; e, e i1 (t) is the voltage of a first capacitor in the variable fractional error system; e, e i2 (t) is the voltage of a second capacitor in the variable fractional error system; g (e) i1 (t)) is a function of the capacitance voltage in the variable fractional error system; e, e i3 (t) is the current through the inductor in the variable fractional error system;
the finite time consistency controller construction module is used for constructing a finite time consistency controller according to the variable fractional order error system;
the finite time consistency controller is:
wherein ,a controller designed for a dynamic event triggering mechanism; />A controller to achieve a finite time agreement; i e i (t) || is e i 2 norms of (t);
the stopping time estimation module is used for estimating the stopping time under the finite time consistency controller; the dynamic behaviors of the driving and responding systems are consistent in the rest time; the rest time is
wherein ,is the rest time; lambda (lambda) 2 Is a third constant; alpha 1 Is the lower bound of α (t); alpha 2 Is the upper bound of α (t); b is Beta function;is a first constant; />Is a fourth constant; />Is Lyapunov function->A value at an initial time 0; and ψ is a second constant.
3. An electronic device comprising a memory for storing a computer program and a processor that runs the computer program to cause the electronic device to perform the limited-time secure communication method of the variable-fractional order chaotic system of claim 1.
4. A computer readable storage medium, characterized in that it stores a computer program which, when executed by a processor, implements the finite time secret communication method of the variable fractional order chaotic system of claim 1.
CN202310071949.XA 2023-02-07 2023-02-07 Finite time secret communication method and system of variable fractional order chaotic system Active CN116318610B (en)

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