CN116318363A - Universal reconfigurable inter-satellite link terminal intermediate frequency processor and reconstruction method - Google Patents

Abstract

The invention discloses a universal reconfigurable inter-satellite link terminal intermediate frequency processor, which comprises an SRAM type FPGA circuit, wherein the SRAM type FPGA circuit is used for physical layer signal processing and link layer management of an inter-satellite link forward return channel, so as to realize a beam control function; the anti-fuse FPGA circuit is used for completing the functions of loading, working state monitoring, automatic refreshing and reconstruction of the SRAM type FPGA main program; the DSP circuit is used for carrying out link layer data exchange with the SRAM type FPGA to complete the protocol processing function of a network layer, the pointing angle calculating function, the bus interface analyzing and controlling function and the self-reconstruction function; the A/D conversion circuit is used for carrying out A/D conversion on the intermediate frequency signal from the radio frequency transceiver module; the D/A conversion circuit is used for carrying out D/A conversion on the digital signal from the SRAM type FPGA; the RS422 interface circuit is used for realizing a serial port communication function; and the bus interface circuit is used for realizing a 1553B bus or CAN bus communication function. The universal hardware platform design has the on-orbit reconstruction capability and realizes the on-orbit performance optimization of the inter-satellite networking protocol.

Description

Universal reconfigurable inter-satellite link terminal intermediate frequency processor and reconstruction method

Technical Field

The invention belongs to the technical field of inter-space communication, and particularly relates to a universal reconfigurable inter-space link terminal intermediate frequency processor and a reconstruction method.

Background

The inter-satellite link terminal is used for establishing a communication link between the spacecrafts and completing data interaction, and is an essential component for realizing networking of the spacecrafts. Different types of spacecraft networking have inconsistent topology and node numbers, so that the requirements of the different types of spacecraft networking on the modulation mode, the communication system, the information rate and the like of the inter-satellite links are also different greatly. If the inter-satellite link terminal is customized according to different requirements, various costs generated by the new design are very high, the development period is greatly prolonged, and the method cannot adapt to the situation of intensive task and diversified requirements of the current model. Because the development period of the current model is shortened, the technical indexes are not sufficiently verified in the ground test, and the technical indexes are required to be corrected by the on-track reconstruction software.

The inter-satellite link terminal generally comprises a radio frequency transceiver module, an intermediate frequency processor, a secondary power supply and other main modules. The intermediate frequency processor mainly completes the baseband processing of the forward backward intermediate frequency signal, realizes the networking protocol, the A/D conversion of the received signal, the D/A conversion of the transmitted signal, the remote control telemetry interface processing and the like. The intermediate frequency processor is a core part of an inter-satellite link terminal, and the traditional intermediate frequency processor cannot adapt to different modulation modes, communication systems, coding modes, information rates and external interfaces, and does not have an on-orbit reconstruction function. Therefore, it is necessary to design a universal reconfigurable intermediate frequency processor, solidify hardware design, perform batch production on the intermediate frequency processor, define actual functions of intermediate frequency by designing different software, shorten development period, and meet the requirements of different models.

Disclosure of Invention

The invention aims to provide a universal reconfigurable inter-satellite link terminal intermediate frequency processor, which is provided with a universal hardware platform, meets different external interface requirements, adopts different software configurations, can realize various modulation modes, communication systems, coding modes, information rates and inter-satellite networking protocols, and meets various inter-satellite link design index requirements; the method has the on-orbit reconstruction capability and realizes the on-orbit performance optimization of the inter-satellite networking protocol.

The invention provides a universal reconfigurable inter-satellite link terminal intermediate frequency processor, which comprises:

SRAM type FPGA, anti-fuse FPGA, DSP circuit, A/D converting circuit, D/A converting circuit, RS422 interface circuit and bus interface circuit;

the SRAM type FPGA circuit is used for physical layer signal processing and link layer management of a forward return channel of an inter-satellite link and realizing a beam control function;

the anti-fuse FPGA circuit is used for completing the functions of loading, working state monitoring, automatic refreshing and reconstruction of the main program of the SRAM type FPGA circuit;

the DSP circuit is used for carrying out link layer data exchange with the SRAM type FPGA circuit to complete a protocol processing function of a network layer, a pointing angle calculating function, a bus interface analyzing and controlling function and a self-reconfiguration function;

the A/D conversion circuit is connected with the SRAM type FPGA circuit and is used for receiving the intermediate frequency signal sent by the radio frequency transceiver module and carrying out A/D conversion and sending the generated digital signal to the SRAM type FPGA circuit;

the D/A conversion circuit is connected with the SRAM type FPGA circuit and is used for receiving the digital signal sent by the SRAM type FPGA circuit, carrying out D/A conversion and sending the generated intermediate frequency signal to the radio frequency transceiver module;

the RS422 interface circuit is connected with the SRAM type FPGA circuit and is used for interacting network layer data with the satellite-borne router, receiving a second pulse signal from the measurement and control subsystem and sending wave control information to the inter-satellite phased array antenna; the anti-fuse FPGA circuit is connected with the anti-fuse FPGA circuit and is used for receiving the reconstruction program frame sent by the comprehensive electronic subsystem and sending the reconstruction feedback telemetry to the comprehensive electronic subsystem;

the bus interface circuit is connected with the DSP circuit and used for carrying out remote control and controlling the sending and receiving of telemetry signals between the DSP circuit and the comprehensive electronic subsystem.

Preferably, the SRAM type FPGA circuit includes a channel signal processing circuit, a link layer management circuit, and a control circuit; the channel signal processing circuit comprises a forward signal processing circuit and a backward signal processing circuit, wherein the forward signal processing circuit is used for receiving the inter-satellite forward signal after down-conversion, demodulating and decoding the forward signal to obtain baseband data, and sending the baseband data to the link layer management circuit; the backward signal processing circuit is used for receiving the baseband data sent by the link layer management circuit, coding and modulating the baseband data, generating a backward intermediate frequency signal and transmitting the backward intermediate frequency signal to the radio frequency receiving and transmitting module;

the link layer management circuit comprises a frame analysis module and a framing module, wherein the frame analysis module is used for receiving the baseband data processed by the forward signal processing circuit, carrying out frame analysis on the processed baseband data to obtain inter-satellite forward data, and sending the processed inter-satellite forward data to the DSP circuit; the framing module is used for receiving inter-satellite return network layer packet data sent by the DSP circuit, carrying out link layer framing on the return network layer packet data to obtain inter-satellite return data, and sending the inter-satellite return data after framing to the return signal processing circuit;

the control circuit is used for receiving the second pulse signal and the satellite time sent by the DSP circuit, correcting the time and outputting GPS synchronous time to the link layer management circuit so as to realize link layer GPS time synchronization.

Preferably, the control circuit is connected with the RS422 interface circuit and the DSP circuit respectively, and is configured to receive a network layer forward data packet of the spaceborne router, and forward the forward data packet to the DSP circuit; receiving a network layer return data packet sent by the DSP circuit, and forwarding the network layer return data packet to the satellite-borne router through the RS422 interface circuit; the wave control pointing angle control information sent by the DSP circuit is received and forwarded to an inter-satellite phased array antenna through the RS422 interface circuit; receiving a reset signal sent by the anti-fuse FPGA to reset the SRAM type FPGA; outputting an interrupt signal to the DSP circuit, and performing interrupt control with the DSP circuit; and sending the self working state telemetering to the DSP circuit and sending the self health state telemetering to the anti-fuse FPGA circuit.

Preferably, the anti-fuse FPGA circuit includes an anti-fuse FPGA, and an SPI FLASH group connected to the anti-fuse FPGA, where the SPI FLASH group includes a first SPI FLASH, a second SPI FLASH, and a third SPI FLASH, which are all used for storing an original instruction operation of the SRAM type FPGA, and a fourth SPI FLASH is used for storing a reconstructed instruction operation of the SRAM type FPGA.

Preferably, the antifuse FPGA is configured to perform a two-out-of-three process on the first SPI FLASH, the second SPI FLASH, and the third SPI FLASH; monitoring the working health state telemetry of the SRAM type FPGA circuit, and performing automatic refreshing treatment after abnormality is found; and receiving a reconstruction program frame sent by the comprehensive electronic subsystem from the RS422 interface circuit, analyzing a frame format and checking, and extracting a reconstruction program to be programmed into the fourth SPI FLASH to realize a power-on reset function.

Preferably, the DSP circuit includes a DSP chip, PROM, FLASH, SDRAM and MRAM connected to the DSP chip, and the PROM is used to store a start-up program of the DSP chip; the FLASH is used for storing a main program and a reconstruction program of the secondary starting of the DSP; the SDRAM is used for caching data generated when the DSP chip works; the MRAM is used for storing six-number information of the star track, and ensuring that the outage data is not lost.

Preferably, the RS422 interface circuit includes a first RS422 interface circuit, a second RS422 interface circuit and a third RS422 interface circuit,

the first RS422 interface circuit is connected with the SRAM type FPGA circuit and the satellite-borne router, is used for interacting network layer data with the satellite-borne router, is connected with the SRAM type FPGA and the measurement and control subsystem, and is used for receiving a second pulse signal from the measurement and control subsystem;

the second RS422 interface circuit is used for receiving the wave control information sent by the SRAM type FPGA circuit and transmitting the wave control information to the inter-satellite phased array antenna;

and the third RS422 interface circuit is connected with the anti-fuse FPGA circuit and the comprehensive electronic subsystem and is used for receiving the reconstructed program frame and sending the reconstructed feedback telemetry to the comprehensive electronic subsystem.

Preferably, the DSP chip is configured to receive six numbers of the own satellites and other satellites orbit acquired in the bus interface circuit, calculate a pointing angle of the phased array antenna, generate wave control information, and forward the wave control information to the SRAM type FPGA circuit; receiving a note number instruction sent by the bus interface circuit, and completing instruction analysis; and packaging the digital quantity telemetry of the SRAM type FPGA circuit and the antifuse type FPGA circuit, and sending the digital quantity telemetry to the comprehensive electronic subsystem through the bus interface circuit so as to realize a floating point calculation function.

Preferably, the modulation modes supported by the channel signal processing circuit comprise BPSK, DBPSK, QPSK and DQPSK, the communication modes comprise TDMA and FDMA, the coding modes comprise RS coding, convolutional coding and LDPC coding, and the channel rate is up to 60Mbps.

The invention provides a reconstruction method of a universal reconfigurable inter-satellite link terminal intermediate frequency processor, which is applied to the universal reconfigurable inter-satellite link terminal intermediate frequency processor according to the embodiment of the invention, and comprises the following steps:

acquiring a reconstruction request instruction;

receiving an erasing instruction according to the reconfiguration request instruction, and performing the erasing instruction in a preset FLASH storage area;

judging whether the erasure instruction is successful or not, if the erasure instruction is overtime, judging that the reconstruction fails, and sending a reconstruction failure telemetry signal;

when the erasing instruction is successful, receiving a reconstruction program frame, writing the reconstruction program frame into a preset FLASH storage area, checking, and reading and comparing the reconstruction program frame from the preset FLASH storage area;

if the comparison is wrong, repeating the previous step, and if the continuous preset times fail, considering the reconstruction to fail, sending a telemetry signal of the reconstruction failure, and stopping the reconstruction;

after all program frames are written in, filling a check instruction on the ground, taking out data in a preset FLASH storage area and performing CRC check;

if the verification result is wrong, a telemetry signal of the reconstruction failure is sent, and the reconstruction is stopped;

if the verification result is correct, loading a reconstruction program instruction on the ground, and reloading the reconstruction program;

judging whether feedback telemetry after reloading or telemetry after resetting is normal or not, and sending a telemetry signal of failure of the reconstruction when the telemetry is abnormal, and stopping the reconstruction;

and when the telemetry is normal, sending a reconstruction power telemetry signal.

Compared with the prior art, the invention has the beneficial effects that:

the universal reconfigurable inter-satellite link terminal intermediate frequency processor disclosed by the invention is provided with a universal hardware platform, is suitable for different external interface requirements, adopts different software configurations, can realize various modulation modes, communication systems, coding modes, information rates and inter-satellite networking protocols, and meets various inter-satellite link design index requirements; the 1553B bus interface or the CAN bus interface CAN be selected according to requirements, BPSK, DBPSK, QPSK and DBPSK modulation, TDMA and FDMA communication, RS coding, convolution coding and LDPC coding CAN be realized, and the following channel rate of 60Mbps CAN be configured.

The universal reconfigurable inter-satellite link terminal intermediate frequency processor disclosed by the invention is designed with different reconfiguration flows aiming at SRAM type FPGA and DSP chips respectively, can realize on-orbit reconfiguration of physical layer, link layer and network layer technical indexes in an inter-satellite networking protocol, and provides guarantee for on-orbit performance optimization of the inter-satellite networking protocol.

Drawings

FIG. 1 is a block diagram of a generalized reconfigurable inter-satellite link terminal intermediate frequency processor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an SRAM type FPGA in an embodiment of the present invention;

fig. 3 is a schematic diagram of a reconstruction flow of a generalized reconfigurable inter-satellite link terminal intermediate frequency processor according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention provides a universal reconfigurable inter-satellite link terminal intermediate frequency processor, which is shown in figure 1 and mainly comprises an SRAM type FPGA circuit, an anti-fuse type FPGA circuit, a DSP circuit, an A/D conversion circuit, a D/A conversion circuit, an RS422 interface circuit and a bus interface circuit, wherein:

the SRAM type FPGA circuit is used for physical layer signal processing and link layer management of an inter-satellite link forward return channel and realizing a beam control function;

the anti-fuse FPGA circuit is used for completing the functions of three-taking two-backup and configuration information loading, working state monitoring, automatic refreshing and reconstruction of an SRAM type FPGA main program;

the DSP circuit is used for carrying out link layer data exchange with the SRAM type FPGA to complete a protocol processing function of a network layer, a pointing angle calculating function, a 1553B bus or CAN bus interface analyzing and controlling function and a self-reconfiguration function;

the A/D conversion circuit is connected with the SRAM type FPGA and is used for carrying out A/D conversion on the intermediate frequency signal from the radio frequency transceiver module and sending the generated digital signal to the SRAM type FPGA;

the D/A conversion circuit is connected with the SRAM type FPGA and is used for carrying out D/A conversion on the digital signal from the SRAM type FPGA and sending the generated intermediate frequency signal to the radio frequency transceiver module;

the RS422 interface circuit comprises an RS422 interface circuit 1, an RS422 interface circuit 2 and an RS422 interface circuit 3, wherein the RS422 interface circuit 1 is used for interacting network layer data with a satellite-borne router and receiving a second pulse signal from a measurement and control subsystem; the RS422 interface circuit 2 is used for sending the wave control information to the inter-satellite phased array antenna; the RS422 interface circuit 3 is used for receiving the reconstruction program frame from the comprehensive electronic subsystem through the anti-fuse FPGA and sending the reconstruction feedback telemetry to the comprehensive electronic subsystem;

the bus interface circuit comprises a 1553B bus interface circuit or a CAN bus interface circuit, is compatible with two bus interfaces in hardware design, is connected with the DSP chip and is used for transmitting and receiving remote control and remote measurement signals with the comprehensive electronic subsystem.

The FPGA of the SRAM type FPGA circuit can be selected from Kintex-7 series FPGAs.

Referring to fig. 2, the program of the sram type FPGA includes a channel signal processing circuit, a link layer management circuit, and a control circuit. The channel signal processing circuit includes a forward signal processing circuit and a backward signal processing circuit. The forward signal processing circuit is used for demodulating and decoding the down-converted inter-satellite forward signals to obtain baseband data, and transmitting the baseband data to the link layer management circuit; the backward signal processing circuit is used for encoding and modulating the baseband data received from the link layer management circuit, generating a backward intermediate frequency signal and transmitting the backward intermediate frequency signal to the radio frequency transceiver module. The modulation modes supported by the channel signal processing circuit comprise BPSK, DBPSK, QPSK and DQPSK, the communication modes comprise TDMA and FDMA, the coding modes comprise RS coding, convolution coding and LDPC coding, and the channel rate is up to 60Mbps. The link layer management circuit acquires GPS synchronization time from the control circuit and performs link layer time synchronization; receiving baseband data processed by a forward signal processing circuit, carrying out frame analysis, and sending the processed inter-satellite forward data to a DSP chip; and meanwhile, receiving inter-satellite return network layer packet data from the DSP chip, carrying out link layer framing, and sending the inter-satellite return data after framing to a return signal processing circuit. The control circuit is used for receiving the pulse-per-second signal and the satellite time from the DSP chip, correcting the time and outputting the GPS synchronous time to the link layer management circuit; receiving a network layer forward data packet from the satellite-borne router through an RS422 interface, and forwarding the forward data packet to the DSP chip; receiving a network layer return data packet from a DSP chip and forwarding the network layer return data packet to the satellite-borne router through an RS422 interface; receiving wave control pointing angle control information from a DSP chip and forwarding the information through an RS422 interface; receiving a reset signal from the anti-fuse FPGA to reset the SRAM type FPGA; outputting a DSP chip interrupt signal and performing interrupt control with the DSP chip; and sending the self working state telemetering to the DSP chip and sending the self health state telemetering to the anti-fuse FPGA.

The anti-fuse FPGA circuit and the DSP circuit comprise a crystal oscillator connected with the anti-fuse FPGA and the DSP chip.

The anti-fuse FPGA circuit comprises an anti-fuse FPGA and 4 SPI FLASH connected with the anti-fuse FPGA, wherein the first SPI FLASH, the second SPI FLASH and the third SPI FLASH are used for storing original programs of the SRAM type FPGA, and the fourth SPI FLASH is used for storing reconstruction programs of the SRAM type FPGA.

The anti-fuse FPGA has a power-on reset function, and resets the SRAM type FPGA and the DSP chip during power-on; the method is used for performing three-in-two processing on the first SPI FLASH, the second SPI FLASH and the third SPI FLASH so as to solve the problem of single event upset when an original program is loaded; the method is used for monitoring the remote measurement of the working health state of the SRAM type FPGA, and carrying out automatic refreshing processing after abnormality is found so as to solve the problem of single event upset when the SRAM type FPGA works; and the system is used for receiving the reconstructed program frame from the comprehensive electronic subsystem from the RS422 interface, analyzing the frame format and checking, extracting the reconstructed program, and programming the reconstructed program to store the fourth SPI FLASH.

DSP circuitry, including a DSP chip, and its associated PROM, FLASH, SDRAM and MRAM. The PROM is used for storing a one-time starting program of the DSP and avoiding the problem of single event upset of the starting program. The FLASH is used for storing a main program and a reconstruction program of the secondary starting of the DSP. SDRAM is used to buffer the data generated during the operation of DSP chip. The MRAM is used for storing six-number information of the star track, and power-off data is not lost.

The DSP chip realizes PROM, FLASH, SDRAM, MRAM, SRAM type FPGA data communication connected with the DSP chip through an EMIF interface.

The DSP chip has floating point computing capability, receives six points of the satellite and the orbit of the satellite from a 1553B bus or a CAN bus interface, calculates the pointing angle of the phased array antenna, generates wave control information and transmits the wave control information to the SRAM type FPGA; receiving a note number instruction from a 1553B bus or a CAN bus interface, and completing instruction analysis; and packaging digital quantity telemetry from the SRAM type FPGA and the antifuse type FPGA, and sending out through a 1553B bus or CAN bus interface.

Referring to fig. 3, the reconstruction flow of the sram type FPGA is as follows:

s1: after receiving the erasing command from the DSP chip, the anti-fuse FPGA erases the program of the fourth SPI FLASH;

s2: after receiving the reconstructed program frame and checking, the anti-fuse FPGA writes the program into the corresponding position of the fourth SPI FLASH storage area, reads out and compares the program from the fourth SPI FLASH after writing;

s3: if the comparison is wrong, repeating the step S2, and if the comparison is wrong, continuously failing for three times, considering the reconstruction to fail, sending a telemetry signal of the reconstruction to fail, and stopping the reconstruction;

s4: after all program frames are written in, filling a check instruction on the ground, and taking out data in the fourth SPI FLASH by the anti-fuse FPGA and comparing CRC check results;

s5: if the comparison is wrong, a telemetry signal of the reconstruction failure is sent, and the reconstruction is stopped;

s6: after comparison, loading a reconstruction program instruction on the ground, and reloading the SRAM type FPGA by the antifuse FPGA by using the reconstruction program;

s7: if the health telemetry fed back to the anti-fuse FPGA after the SRAM type FPGA is overloaded is abnormal, a telemetry signal of the reconstruction failure is sent, and the reconstruction is stopped;

s8: if the health telemetry fed back to the anti-fuse FPGA after the SRAM type FPGA is overloaded is normal, the success of the reconstruction is indicated, and a reconstruction power telemetry signal is sent;

referring to fig. 3, the reconstruction flow of the dsp chip is as follows:

s1: after receiving the uploading erasing command from the bus interface, the DSP chip erases the FLASH reconstruction program area;

s2: after the DSP chip receives the upper reconstructed program frame and checks the upper reconstructed program frame, the DSP chip writes the program into the corresponding position of the FLASH reconstructed program area, reads out the program from the FLASH after the program is written, and compares the program with the FLASH;

s3: if the comparison is wrong, repeating the step S2, and if the comparison is wrong, continuously failing for three times, considering the reconstruction to fail, sending a telemetry signal of the reconstruction to fail, and stopping the reconstruction;

s4: after all programs are written, checking instructions are injected on the ground. The DSP chip takes out the data in FLASH and checks and compares the data;

s5: if the comparison is wrong, a telemetry signal of the reconstruction failure is sent, and the reconstruction is stopped;

s6: after comparison, loading a reconstruction program instruction on the ground, and modifying a reconstruction region program of the FLASH by the DSP chip;

s7: the anti-fuse FPGA sends a reset instruction of the DSP chip, and the reset instruction of the DSP chip loads a reconstruction program;

s8: if the telemetry is abnormal after the reset of the DSP chip, sending a telemetry signal of failure of the reconstruction, and stopping the reconstruction;

s9: if the telemetry is normal after the DSP chip is reset, the reconstruction is successful, and a reconstruction power telemetry signal is sent.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A generalized reconfigurable inter-satellite link terminal intermediate frequency processor, comprising:

SRAM type FPGA, anti-fuse FPGA, DSP circuit, A/D converting circuit, D/A converting circuit, RS422 interface circuit and bus interface circuit;

the SRAM type FPGA circuit is used for physical layer signal processing and link layer management of a forward return channel of an inter-satellite link and realizing a beam control function;

the anti-fuse FPGA circuit is used for completing the functions of loading, working state monitoring, automatic refreshing and reconstruction of the main program of the SRAM type FPGA circuit;

the DSP circuit is used for carrying out link layer data exchange with the SRAM type FPGA circuit to complete a protocol processing function of a network layer, a pointing angle calculating function, a bus interface analyzing and controlling function and a self-reconfiguration function;

the A/D conversion circuit is connected with the SRAM type FPGA circuit and is used for receiving the intermediate frequency signal sent by the radio frequency transceiver module and carrying out A/D conversion and sending the generated digital signal to the SRAM type FPGA circuit;

the D/A conversion circuit is connected with the SRAM type FPGA circuit and is used for receiving the digital signal sent by the SRAM type FPGA circuit, carrying out D/A conversion and sending the generated intermediate frequency signal to the radio frequency transceiver module;

the RS422 interface circuit is connected with the SRAM type FPGA circuit and is used for interacting network layer data with the satellite-borne router, receiving a second pulse signal from the measurement and control subsystem and sending wave control information to the inter-satellite phased array antenna; the anti-fuse FPGA circuit is connected with the anti-fuse FPGA circuit and is used for receiving the reconstruction program frame sent by the comprehensive electronic subsystem and sending the reconstruction feedback telemetry to the comprehensive electronic subsystem;

the bus interface circuit is connected with the DSP circuit and used for carrying out remote control and controlling the sending and receiving of telemetry signals between the DSP circuit and the comprehensive electronic subsystem.

2. The generalized reconfigurable inter-satellite link termination intermediate frequency processor of claim 1,

the SRAM type FPGA circuit comprises a channel signal processing circuit, a link layer management circuit and a control circuit; the channel signal processing circuit comprises a forward signal processing circuit and a backward signal processing circuit, wherein the forward signal processing circuit is used for receiving the inter-satellite forward signal after down-conversion, demodulating and decoding the forward signal to obtain baseband data, and sending the baseband data to the link layer management circuit; the backward signal processing circuit is used for receiving the baseband data sent by the link layer management circuit, coding and modulating the baseband data, generating a backward intermediate frequency signal and transmitting the backward intermediate frequency signal to the radio frequency receiving and transmitting module;

the link layer management circuit comprises a frame analysis module and a framing module, wherein the frame analysis module is used for receiving the baseband data processed by the forward signal processing circuit, carrying out frame analysis on the processed baseband data to obtain inter-satellite forward data, and sending the processed inter-satellite forward data to the DSP circuit; the framing module is used for receiving inter-satellite return network layer packet data sent by the DSP circuit, carrying out link layer framing on the return network layer packet data to obtain inter-satellite return data, and sending the inter-satellite return data after framing to the return signal processing circuit;

the control circuit is used for receiving the second pulse signal and the satellite time sent by the DSP circuit, correcting the time and outputting GPS synchronous time to the link layer management circuit so as to realize link layer GPS time synchronization.

3. The generalized reconfigurable inter-satellite link termination intermediate frequency processor of claim 2,

the control circuit is respectively connected with the RS422 interface circuit and the DSP circuit and is used for receiving the network layer forward data packet of the satellite-borne router and forwarding the forward data packet to the DSP circuit; receiving a network layer return data packet sent by the DSP circuit, and forwarding the network layer return data packet to the satellite-borne router through the RS422 interface circuit; the wave control pointing angle control information sent by the DSP circuit is received and forwarded to an inter-satellite phased array antenna through the RS422 interface circuit; receiving a reset signal sent by the anti-fuse FPGA to reset the SRAM type FPGA; outputting an interrupt signal to the DSP circuit, and performing interrupt control with the DSP circuit; and sending the self working state telemetering to the DSP circuit and sending the self health state telemetering to the anti-fuse FPGA circuit.

4. The generalized reconfigurable inter-star link terminal intermediate frequency processor of claim 1, wherein the antifuse FPGA circuit comprises an antifuse FPGA, and an SPI FLASH group connected to the antifuse FPGA, the SPI FLASH group comprising a first SPI FLASH, a second SPI FLASH, and a third SPI FLASH, all for storing original instruction operations of the SRAM type FPGA, and a fourth SPI FLASH for storing reconfiguration instruction operations of the SRAM type FPGA.

5. The generalized reconfigurable inter-star link terminal intermediate frequency processor of claim 4, wherein the antifuse FPGA is configured to perform a three-out-of-two process on the first, second, and third SPI FLASH; monitoring the working health state telemetry of the SRAM type FPGA circuit, and performing automatic refreshing treatment after abnormality is found; and receiving a reconstruction program frame sent by the comprehensive electronic subsystem from the RS422 interface circuit, analyzing a frame format and checking, and extracting a reconstruction program to be programmed into the fourth SPI FLASH to realize a power-on reset function.

6. The generalized reconfigurable inter-satellite link termination intermediate frequency processor of claim 1,

the DSP circuit comprises a DSP chip, PROM, FLASH, SDRAM and MRAM (magnetic random access memory) connected with the DSP chip, and the PROM is used for storing a one-time starting program of the DSP chip; the FLASH is used for storing a main program and a reconstruction program of the secondary starting of the DSP; the SDRAM is used for caching data generated when the DSP chip works; the MRAM is used for storing six-number information of the star track, and ensuring that the outage data is not lost.

7. The generalized reconfigurable inter-satellite link termination intermediate frequency processor of claim 1, wherein the RS422 interface circuit includes a first RS422 interface circuit, a second RS422 interface circuit, and a third RS422 interface circuit,

the first RS422 interface circuit is connected with the SRAM type FPGA circuit and the satellite-borne router, is used for interacting network layer data with the satellite-borne router, is connected with the SRAM type FPGA and the measurement and control subsystem, and is used for receiving a second pulse signal from the measurement and control subsystem;

the second RS422 interface circuit is used for receiving the wave control information sent by the SRAM type FPGA circuit and transmitting the wave control information to the inter-satellite phased array antenna;

and the third RS422 interface circuit is connected with the anti-fuse FPGA circuit and the comprehensive electronic subsystem and is used for receiving the reconstructed program frame and sending the reconstructed feedback telemetry to the comprehensive electronic subsystem.

8. The universal reconfigurable inter-satellite link terminal intermediate frequency processor of claim 6, wherein the DSP chip is configured to receive six numbers of own satellites and other satellites orbits acquired in the bus interface circuit, calculate a pointing angle of a phased array antenna, generate wave control information, and forward the wave control information to the SRAM type FPGA circuit; receiving a note number instruction sent by the bus interface circuit, and completing instruction analysis; and packaging the digital quantity telemetry of the SRAM type FPGA circuit and the antifuse type FPGA circuit, and sending the digital quantity telemetry to the comprehensive electronic subsystem through the bus interface circuit so as to realize a floating point calculation function.

9. A generalized reconfigurable inter-satellite link termination intermediate frequency processor of claim 2, wherein the modulation schemes supported by the channel signal processing circuitry include BPSK, DBPSK, QPSK and DQPSK, the communication schemes include TDMA and FDMA, the coding schemes include RS coding, convolutional coding and LDPC coding, and the channel rates are up to 60Mbps.

10. A reconstruction method of a generalized reconfigurable inter-satellite link terminal intermediate frequency processor, applied to the generalized reconfigurable inter-satellite link terminal intermediate frequency processor according to any one of claims 1 to 9, comprising:

acquiring a reconstruction request instruction;

receiving an erasing instruction according to the reconfiguration request instruction, and performing the erasing instruction in a preset FLASH storage area;

judging whether the erasure instruction is successful or not, if the erasure instruction is overtime, judging that the reconstruction fails, and sending a reconstruction failure telemetry signal;

when the erasing instruction is successful, receiving a reconstruction program frame, writing the reconstruction program frame into a preset FLASH storage area, checking, and reading and comparing the reconstruction program frame from the preset FLASH storage area;

if the comparison is wrong, repeating the previous step, and if the continuous preset times fail, considering the reconstruction to fail, sending a telemetry signal of the reconstruction failure, and stopping the reconstruction;

after all program frames are written in, filling a check instruction on the ground, taking out data in a preset FLASH storage area and performing CRC check;

if the verification result is wrong, a telemetry signal of the reconstruction failure is sent, and the reconstruction is stopped;

if the verification result is correct, loading a reconstruction program instruction on the ground, and reloading the reconstruction program;

judging whether feedback telemetry after reloading or telemetry after resetting is normal or not, and sending a telemetry signal of failure of the reconstruction when the telemetry is abnormal, and stopping the reconstruction;

and when the telemetry is normal, sending a reconstruction power telemetry signal.

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