CN116318073A

CN116318073A - Frequency dividing circuit, time-to-digital converter, detection device and detection system

Info

Publication number: CN116318073A
Application number: CN202310282600.0A
Authority: CN
Inventors: 雷述宇
Original assignee: Ningbo Abax Sensing Electronic Technology Co Ltd
Current assignee: Ningbo Abax Sensing Electronic Technology Co Ltd
Priority date: 2023-03-22
Filing date: 2023-03-22
Publication date: 2023-06-23

Abstract

The application discloses a frequency dividing circuit, a time-to-digital converter, a detection device and a detection system, wherein the frequency dividing circuit comprises at least one master frequency divider and at least one slave frequency divider; at least one of the main frequency dividers includes: a first master frequency divider, at least one of said slave frequency dividers comprising: a first slave frequency divider, the first master frequency divider being connected with the first slave frequency divider; the first main frequency divider is used for dividing the frequency of the received first clock signal to obtain a first delay signal, and the frequency of the first delay signal is half of the frequency of the first clock signal; the first slave frequency divider is used for adjusting the first delay signal according to the first clock signal to obtain a second clock signal, so that the second clock signal is aligned with the first clock signal; by the design, the range of the time-to-digital converter can be enlarged, and meanwhile, the range measurement precision can be ensured.

Description

Frequency dividing circuit, time-to-digital converter, detection device and detection system

Technical Field

The application relates to the technical field of laser radar ranging, in particular to a frequency dividing circuit, a time-to-digital converter, detection equipment and a detection system.

Background

The time-of-flight ranging method (Time of flight TOF) is based on the principle of continuously transmitting light pulses to a target, then receiving light returned from the object with a sensor, and obtaining the target distance by detecting the flight (round trip) time of the light pulses. The direct time-of-flight detection (Direct Time of flight DTOF) is used as one of TOF, and the DTOF technology directly obtains the target distance by calculating the transmitting and receiving time of the light pulse, so that the method has the advantages of simple principle, good signal-to-noise ratio, high sensitivity, high accuracy and the like, and is receiving more and more attention. That is to say direct time-of-flight detection determines the distance to an object by directly measuring the length of time between the emission of radiation and the detection of radiation after reflection from the object or other object.

In some applications, a sensing avalanche diode (SPAD) array of reflected radiation may be performed using a photodetector array including a single photon detector (e.g., single photon). One or more photodetectors may define detector pixels of the array. SPAD arrays may be used as solid state photodetectors in imaging applications where high sensitivity and timing resolution may be desirable. SPADs are based on semiconductor junctions (e.g., p-n junctions) that can detect incident photons, for example, when biased outside of their breakdown region by or in response to a gating signal having a desired pulse width. The high reverse bias voltage will generate an electric field of sufficient magnitude that the unidirectional bias voltage introduced into the device depletion layer will generate an electric field of sufficient magnitude that individual charge carriers introduced into the device depletion layer can cause self-sustaining avalanche by impact ionization and individual charge carriers can cause self-sustaining avalanche by impact ionization. The avalanche can be quenched either actively (e.g., by reducing the bias voltage) or passively (e.g., by using the voltage drop across the series resistance) by a quenching circuit to "reset" the device to further detect photons. The initial charge carriers may be photo-generated by a single incident photon striking a high electric field region. It is this function that has led to the name "single photon avalanche diode". This single photon detection mode of operation is commonly referred to as a "geiger mode".

To count photons incident on the S PAD array, some ToF pixel methods may use a digital or analog counter to indicate the detection and arrival time of the photons, also known as a timestamp. Digital counters may be easier to implement and expand, but may be more expensive in terms of area (e.g., relative to the physical size of the array). Analog counters may be more compact but may be limited by photon counting depth (bit depth), noise and or uniformity issues.

To time stamp the incident photons, some SPAD array-based ToF pixel methods use time-to-digital converters (TDCs). TDC can be used in time-of-flight imaging applications to improve the timing resolution of a single clock cycle. Some advantages of such digital methods may include that the size of the TDC tends to spread with technology nodes, and that the stored values may be more robust to leakage.

To achieve high accuracy, a long range ranging TDC clock needs to compromise a large scale time range with high accuracy, where the frequency of the clock is in inverse relationship with the measurable time period, e.g., the measurable time period of a clock having a frequency of 832M is 1.2ns. How to simultaneously consider the large-scale time range and high precision of the TDC clock is a technical problem to be solved.

The description of the background art is only for the purpose of facilitating an understanding of the relevant art and is not to be taken as an admission of prior art.

Disclosure of Invention

Accordingly, embodiments of the present invention are directed to providing a time-to-digital converter that ensures ranging accuracy while expanding the range of the time-to-digital converter.

In a first aspect, an embodiment of the present invention provides a frequency dividing circuit, wherein the frequency dividing circuit includes at least one master frequency divider and at least one slave frequency divider;

at least one of the main frequency dividers includes: a first master frequency divider, at least one of said slave frequency dividers comprising: a first slave frequency divider, the first master frequency divider being connected with the first slave frequency divider;

the first main frequency divider is used for dividing the frequency of the received first clock signal to obtain a first delay signal, and the frequency of the first delay signal is half of the frequency of the first clock signal;

the first slave frequency divider is used for adjusting the first delay signal according to the first clock signal to obtain a second clock signal, so that the second clock signal is aligned with the first clock signal.

Optionally, the first input end of the first master frequency divider and the first input end of the first slave frequency divider are both connected with an oscillator, and the first master frequency divider and the first slave frequency divider receive the first clock signal sent by the oscillator;

the first output end of the first master frequency divider is connected with the second input end of the first slave frequency divider, and the first master frequency divider sends the first delay signal to the second input end of the first slave frequency divider through the first output end;

the second output end of the first main frequency divider is connected with the second input end of the first main frequency divider, and the first main frequency divider divides the frequency of the first clock signal through a first temporary signal output by the second output end to obtain the first delay signal.

Optionally, at least one of the main frequency dividers further comprises: a second master frequency divider, at least one of the slave frequency dividers further comprising: a second slave frequency divider;

the second master frequency divider is connected with the first master frequency divider, and the second slave frequency divider is connected with the second master frequency divider;

the second main frequency divider is used for dividing the frequency of the first temporary signal output by the first main frequency divider and outputting a second delay signal, and the frequency of the second delay signal is half of the frequency of the first temporary signal;

the second slave frequency divider is used for adjusting the second delay signal according to the first clock signal to obtain a third clock signal, so that the third clock signal is aligned with the first clock signal.

Optionally, a first input end of the second main frequency divider is connected with a second output end of the first main frequency divider, and the second main frequency divider obtains the first temporary signal output by the second output end of the first main frequency divider through the first input end;

the first output end of the second master frequency divider is connected with the second input end of the second slave frequency divider, and the second master frequency divider sends the second delay signal to the second input end of the second slave frequency divider through the first output end;

the second output end of the second main frequency divider is connected with the second input end of the second main frequency divider, and the second main frequency divider divides the frequency of the second temporary signal through a third temporary signal output by the second output end to obtain the second delay signal;

the first input end of the second slave frequency divider is connected with the oscillator, and the second slave frequency divider receives the first clock signal sent by the oscillator through the first input end.

Optionally, the first master frequency divider and the first slave frequency divider are D flip-flops.

Optionally, the first clock signal is a binary signal.

Optionally, the first bit clock output signal, the second bit clock output signal, the third bit clock output signal and the fourth bit clock output signal are converted into binary codes according to a preset rule.

In a second aspect, an embodiment of the present invention provides a time-to-digital converter, including: voltage controlled oscillator, and frequency dividing circuit as claimed in any one of claims 1 to 6.

In a third aspect, an embodiment of the present invention provides a detection apparatus, which is characterized in that it includes: a pulsed light source, a detector array and a processing module, and a time-to-digital converter as claimed in claim 7.

In a fourth aspect, an embodiment of the invention provides a detection system characterized by comprising a detection device as claimed in claim 8.

Additional optional features and technical effects of embodiments of the invention are described in part below and in part will be apparent from reading the disclosure herein.

Drawings

Embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, wherein like or similar reference numerals denote like or similar elements, and wherein:

FIG. 1 shows a functional block diagram of a detection device in which embodiments of the invention may be implemented;

FIG. 2 illustrates a schematic diagram of a voltage controlled oscillator in which an embodiment of the invention may be implemented;

FIG. 3 illustrates a schematic diagram of a cascade of four voltage controlled oscillators in which embodiments of the invention may be implemented;

FIG. 3a illustrates a schematic diagram of a state of a first voltage controlled oscillator in a cascade of four voltage controlled oscillators in which embodiments of the present invention may be implemented;

FIG. 3b illustrates a schematic diagram of a state of a second voltage controlled oscillator in a cascade of four voltage controlled oscillators in which embodiments of the present invention may be implemented;

FIG. 3c illustrates a schematic diagram of a third voltage controlled oscillator in a cascade of four voltage controlled oscillators in which embodiments of the present invention may be implemented;

FIG. 3d illustrates a schematic diagram of a fourth voltage controlled oscillator in a cascade of four voltage controlled oscillators in which embodiments of the invention may be implemented;

FIG. 3e illustrates another state diagram of a first voltage controlled oscillator in a cascade of four voltage controlled oscillators in which embodiments of the invention may be implemented;

FIG. 4 illustrates a schematic diagram of a TDC clock in which an embodiment of the present invention may be implemented;

FIG. 5 illustrates a schematic diagram of a TDC clock that may be used to expand the TDC range in which embodiments of the present invention may be implemented;

FIG. 6 illustrates a schematic diagram of a TDC clock frequency division that expands the TDC range in which an embodiment of the present invention may be implemented;

FIG. 7 is a schematic diagram of a TDC clock with an increased TDC range that may implement an embodiment of the present invention to produce an unknown time delay;

FIG. 8 illustrates a schematic diagram of a timing error due to an unknown time delay in which an embodiment of the present invention may be implemented;

FIG. 9 illustrates a schematic diagram of TDC clock frequency division in which an embodiment of the present invention may be implemented;

FIG. 10 illustrates a sampled binary counter waveform diagram in which an embodiment of the present invention may be implemented.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. The exemplary embodiments of the present invention and the descriptions thereof are used herein to explain the present invention, but are not intended to limit the invention.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Fig. 1 shows a functional block diagram of a detection device in which an embodiment of the invention may be implemented. The detecting device as shown in fig. 1 includes: a pulsed light source 101, an object to be measured 102, a detector array 103, and a processing module 104.

The pulse light source 101 is configured to emit a detection pulse to the object to be detected 102, and the pulse light source of the reflection portion of the object to be detected 102 is directed to the detector array 103. The detection array 103 may be a SPAD array, and the detection array 103 receives reflected photons, and when the reflected photons strike a high electric field region, the photons photoelectrically generate avalanche causing SAPD. Each picture element of the SPA D array detects the photon-induced avalanche time of arrival during a certain window detection period, deems an event detected when photon-induced avalanche is detected during a certain detection window period, and marks the event detected during that detection window period. The manner of marking may be cumulative plus 1 or other indicia without limitation in embodiments of the present invention.

Processing module 103 may determine during which detection window the reflected photon is based on the counted detection events identified during each detection window. Determining the arrival time range of the reflected photons may further detect the arrival time of the emitted photons within the time range. The TDC module may be used when further detecting the arrival time of the reflected photons. The TDC module generates a time code according to the arrival time of the reflected photon, the processing module can generate a histogram according to the time code, and finally the accurate arrival time of the reflected photon is obtained according to the histogram.

After the arrival time of the reflected photon is obtained, the distance of the object to be detected can be detected according to the arrival time of the photon. The distance D can be calculated by the following formula:

d=c·t/2 (1), where c is the speed of light.

Fig. 2 shows a schematic diagram of a voltage controlled oscillator in which an embodiment of the invention may be implemented, as shown in fig. 2, namely, a voltage controlled oscillator VCO (Voltage Controlled Oscillator) comprising: the first NMOS tube M1, the second NMOS tube M2, the third PMOS tube M3, the fourth PMOS tube M4, the fifth PMOS tube M5, the sixth PMOS tube M6, the seventh PMOS tube M7 and the eighth PMOS tube M8. Wherein the gate voltage of the first NMOS tube M1 is Vin1+ (the positive electrode of the first input voltage), the gate voltage of the second NMOS tube M2 is Vin1- (the negative electrode of the first input voltage), and the gate voltage of the third PMOS tube M3 is V _cp (adjustable input voltage), the grid voltage of the sixth PMOS tube M6 is V _cp The gate voltage of the seventh PMOS transistor M7 is Vin2- (the second input voltage negative electrode), and the gate voltage of the eighth PMOS transistor M8 is Vin2+ (the second input voltage positive electrode). In the embodiment shown in fig. 2, the drain of the first NMOS transistor M1 is connected to the drain of the third PMOS transistor M3 and the drain of the fourth PMOS transistor M4, the drain terminal voltage of the first NMOS transistor M1 is Vout- (negative output voltage), the drain of the second NMOS transistor M2 is connected to the drain of the fifth PMOS transistor M5 and the drain of the sixth PMOS transistor M6, and the drain terminal voltage of the second NMOS transistor M2 is vout+ (positive output voltage)). In the VCO shown in fig. 2, the power supply voltage is avdd, and the ground terminal is avss. In the embodiment shown in FIG. 2V _cp The voltage value can be any one of 0-1.8V, and is used for controlling the current of the third PMOS tube M3 and the sixth PMOS tube M6. Wherein the Vin1+ voltage may be 1.8V or 0V. The above voltage values are only for illustration and are not particularly limiting of the present application. In the embodiment shown in fig. 2, when vjn1+ is 1.8V, vout-is 0V, and the fifth PMOS transistor M5 is turned on to pull vout+ high to 1.8V; when Vin 1-is 1.8V, vout+ is 0V, and the fourth PMOS tube M4 is turned on to pull Vout-high to 1.8V.

Fig. 3 shows a schematic diagram of a cascade of four voltage controlled oscillators that may implement an embodiment of the invention, including a first VCO 301, a second VCO 302, a third VCO303, and a fourth VCO 304 as shown in fig. 3. The first VCO 301, the second VCO 302, the third VCO303, and the fourth VCO 304 are similar to the embodiment shown in fig. 2, and will not be described herein.

In the embodiment illustrated in FIG. 3, vout+ (vop_1) of the first VCO 301 is interconnected with Vin 1-of the second VCO 302, vout- (von_1) of the first VCO 301 is interconnected with Vin1+ of the second VCO 302, vin1+ of the first VCO 301 is interconnected with Vin2+ of the second VCO 302, vin1-of the first VCO 301 is interconnected with Vin2-of the second VCO 302; vout+ (vop_2) of the second VCO 302 is interconnected with Vin 1-of the third VCO303, vout- (von_2) of the second VCO 302 is interconnected with Vin1+ of the third VCO303, vin1+ of the second VCO 302 is interconnected with Vin2+ of the third VCO303, vin1-of the second VCO 302 is interconnected with Vin2-of the third VCO 303; vout+ (vop_3) of the third VCO303 is interconnected with Vin 1-of the fourth VCO 304, vout- (von_3) of the third VCO303 is interconnected with Vin1+ of the fourth VCO 304, vin1+ of the third VCO 302 is interconnected with Vin2+ of the fourth VCO 304, vin1-of the third VCO303 is interconnected with Vin2-of the fourth VCO 304; vout+ (vop_4) of the fourth VCO 304 is interconnected with Vin 1-of the first VCO 301, vout- (von_4) of the fourth VCO 304 is interconnected with Vin1+ of the first VCO 301, vin1+ of the fourth VCO 304 is connected with Vin2+ of the first VCO 301, vin1-of the fourth VCO303 is connected with Vin2-of the first VCO 301.

Fig. 3a shows a schematic state diagram of a first voltage controlled oscillator in a cascade of four voltage controlled oscillators in which an embodiment of the invention may be implemented. The structure of the first vco shown in fig. 3a is similar to that of the vco of the embodiment shown in fig. 2, and will not be described here again, in fig. 3a, von_1 (vout+) may be set to 1.8v, von_1 (vout-) may be set to 0v, and m5 is turned on.

Fig. 3b shows a schematic diagram of the state of a second voltage controlled oscillator in a cascade of four voltage controlled oscillators in which an embodiment of the invention may be implemented. The structure of the second vco shown in fig. 3b is similar to that of the vco of the embodiment shown in fig. 2, and will not be described again here. Von_1 (vout+) is 1.8V in the embodiment shown in fig. 3a, and von_1 (vout-) is 0V in the embodiment of fig. 3b, von_2=0v, and vop2=1.8v.

Fig. 3c shows a schematic state diagram of a third voltage controlled oscillator in a cascade of four voltage controlled oscillators in which an embodiment of the invention may be implemented. The structure of the third vco shown in fig. 3c is similar to that of the vco of the embodiment shown in fig. 2, and will not be described again here. Von_2=0v in the embodiment shown in fig. 3b, von_2=1.8v corresponds to von_3=1.8v in the embodiment of fig. 3c, and vop3=0v.

Fig. 3d shows a schematic state diagram of a fourth voltage controlled oscillator in a cascade of four voltage controlled oscillators in which an embodiment of the invention may be implemented. The structure of the fourth vco shown in fig. 3d is similar to that of the vco of the embodiment shown in fig. 2, and will not be described again here. Von_3=1.8v in the embodiment shown in fig. 3c, von_4=0v in the embodiment of fig. 3d, and vop4=1.8v corresponding to von_3=0v.

Fig. 3e shows another state diagram of a first voltage controlled oscillator in a cascade of four voltage controlled oscillators in which an embodiment of the invention may be implemented. The structure of the first vco shown in fig. 3e is similar to that of the vco of the embodiment shown in fig. 2, and will not be described again here. In the embodiment shown in fig. 3d, von_4=0v and vop_4=1.8v, the signal is returned to von_1=0v and vop_1=1.8v in the embodiment shown in fig. 3e corresponding to the first voltage-controlled oscillator, and the signal starts to oscillate, i.e. is flipped at a certain frequency between 0 and 1.8V, i.e. is the voltage-controlled oscillator, contrary to the values von_1 and vop_1 in the first voltage-controlled oscillator in the embodiment shown in fig. 3 a. The Vcp voltage controls the oscillation frequency, the larger the Vcp, the smaller the current flowing through the M3 and M6 tubes, the slower the signal charges, and the lower the switching frequency. Conversely, the smaller the Vcp, the greater the charging current and the faster the slew rate. The Vcp may control the time range of one cycle of the clock. In the embodiment of the present application, a clock period of 1.2ns is taken as an example for illustration, but the clock period is not particularly limited, and the clock frequency corresponding to the clock period of 1.2ns is 832M.

Fig. 4 illustrates a schematic diagram of a TDC clock in which an embodiment of the present invention may be implemented. The TDC clock includes, as shown in fig. 4: a first bit clock (CLK 832 m_1), a second bit clock (CLK 832 m_2), a third bit clock (CLK 832 m_3), and a fourth bit clock (CLK 832 m_4). The voltage controlled oscillator in the above embodiment completes one cycle of oscillation after 8 clock moments. The embodiment shown in fig. 4 is a schematic waveform diagram of the outputs of four voltage-controlled oscillators in cascade in the above embodiment at 8 times when one cycle oscillation is completed. In the embodiment shown in fig. 4, the first bit clock (CLK 832 m_1) corresponds to the output of the first voltage controlled oscillator, the second bit clock (CLK 832 m_2) corresponds to the output of the second voltage controlled oscillator, the third bit clock (CLK 832 m_3) corresponds to the output of the third voltage controlled oscillator, and the fourth bit clock (CLK 832 m_4) corresponds to the output of the fourth voltage controlled oscillator. The output of the four cascade-controlled oscillators at time t1 in fig. 4 is 1000; the output of the four cascade control oscillators at the time t2 is 1100; the outputs of the four cascade control oscillators at time t3 are 1110; the output of the four cascade control oscillators at the time t4 is 1111; the output of the four cascade control oscillators at the time t5 is 0111; the output of the four cascade control oscillators at the time t6 is 0011; the output of the four cascade control oscillators at the time t7 is 0001; the outputs of the four cascade-controlled oscillators at time t8 are 0000. The accuracy of the TDC clock in the embodiment shown in fig. 4 is 150ps.

In the embodiment shown in fig. 4, the output from time t1 to time t8 is converted into a binary code according to a certain rule. For example, the first bit in the output may be inverted and then used as the first bit of the binary code; performing exclusive nor logic on the first bit and the third bit in the output to obtain a second bit of the binary code; when the first bit of the binary code is 0 and the second bit of the binary code is 0, taking the second bit of the output code as the third bit of the binary code; when the first bit of the binary code is 0 and the second bit of the binary code is 1, the fourth bit of the output code is taken as the third bit of the binary code; when the first bit of the binary code is 1 and the second bit of the binary code is 0, inverting the second bit of the output code to be used as the third bit of the binary code; when the first bit of the binary code is 0 and the second bit of the binary code is 1, the fourth bit of the output code is inverted to be the third bit of the binary code.

Sampling this output signal with the stop signal in the embodiment of fig. 4 results in a TDC of 150ps accuracy. But only a 832M clock is used to obtain a TDC in the range of 1.2ns. The extended range requires a low frequency clock as a counter.

Fig. 5 illustrates a schematic diagram of a TDC clock that may be used to expand the range of a TDC in which embodiments of the present invention may be implemented. As shown in fig. 5, the first clock (CLK 832 m_1) 501, the second clock (CLK 832 m_2) 502, the third clock (CLK 832 m_3) 503, the fourth clock (CLK 832 m_4) 504, the second clock (CLK 416M) 505, the third clock (CLK 208M) 506, the fourth clock (CLK 104M) 507, the fifth clock (CLK 52M) 508, and the stop signal 509. As shown in FIG. 5, stop signal 509 has an upper bit of 1000 and a lower bit of 1100. In the embodiment shown in fig. 5, if the 832M TDC clock span is 1.2ns, then the 52M TDC clock span is 19.2ns. The corresponding TDC test time for stop signal 509 is 8×1.2+150×2=9.9 ns. This enlarges the TDC range and can ensure the TDC accuracy of 150ps.

Fig. 6 illustrates a schematic diagram of TDC clock frequency division to expand the range of a TDC in which an embodiment of the present invention may be implemented. As shown in fig. 6, includes a frequency Divider (DFF) 601, a frequency divider 602, a frequency divider 603, a frequency divider 604, and a frequency divider 605. The divider shown in fig. 6 is implemented by a D flip-flop having two inputs, a Clock (CLK) input and a data (D) input. In addition, the D flip-flop also has two outputs, one being the main output denoted Q and the other being the complement of Q denoted QN'. Wherein the input frequency of CLK terminal 601 is 832M, the D terminal and QN terminal of 601 are connected with CLK terminal 602, and the output frequency of Q terminal of divider 601 is 416M. Divider 602, divider 603, divider 604, and divider 605 are similar to divider 601 in principle and will not be described again here. As shown in fig. 6, the Q-terminal output frequency of the frequency divider 602 is 208M, the Q-terminal output frequency of the frequency divider 603 is 104M, the Q-terminal output frequency of the frequency divider 604 is 52M, and the Q-terminal output frequency of the frequency divider 605 is 26M. The range of the TDC can be enlarged by the embodiment shown in fig. 6.

Fig. 7 is a schematic diagram of a TDC clock with an unknown time delay that may be used to expand the TDC range in which embodiments of the present invention may be implemented. As shown in fig. 7, includes: a first clock (CLK 832 m_1) 701, a second clock (CLK 416M) 702, a third clock (CLK 208M) 703, a fourth clock (CLK 104M) 704, a fifth clock (CLK 52M) 705, a sixth clock (CLK 26M) 706, and a clock (t_delay) 707. As can be seen in fig. 7, there is an unknown delay between the first clock 701 and the second clock 702, between the second clock 702 and the third clock 703, between the third clock 703 and the fourth clock 704, between the fourth clock 704 and the fifth clock 705, and between the fifth clock 705 and the sixth clock 706, due to the delay introduced by the D flip-flop. When the stop signal is within a certain t_delay, an error code is caused, and a ranging error is caused.

FIG. 8 illustrates a schematic diagram of timing errors due to unknown time delays in which an embodiment of the present invention may be implemented, including, as shown in FIG. 8: a first clock (CLK 832 m_1) 801, a second clock (CLK 416M) 802, a third clock (CLK 208M) 803, a fourth clock (CLK 104M) 804, a fifth clock (CLK 52M) 805, a sixth clock (CLK 26M) 806, and a stop signal 807. The high order bits sampled if there is no unknown delay stop signal 807 as shown in fig. 8 should be 0010, but because there is an unknown delay, the actual samples become 0000. Resulting in a measurement error of 1.2ns.

Fig. 9 shows a schematic diagram of frequency division of a TDC clock in which an embodiment of the invention may be implemented, including, as shown in fig. 9: frequency Divider (DFF) 901, frequency divider 902, frequency divider 903, frequency divider 904, and frequency divider 905. The divider shown in fig. 9 is implemented by a D flip-flop having two inputs, a Clock (CLK) input and a data (D) input.

In addition, the D flip-flop also has two outputs, one being the main output denoted Q and the other being the complement of Q denoted QN'. The CLK terminal of the divider 901 has an input frequency of 832M, the d terminal has an input frequency of 416M, and the 416M signal is the signal output from the Q terminal 601 in the embodiment shown in fig. 6, and the Q terminal of the divider 901 has an output frequency of 416M. The CLK terminal of the frequency divider 902 has an input frequency of 832M, the d terminal inputs a 208M signal, the 208M signal is the Q terminal output signal of 602 in the embodiment shown in fig. 6, and the Q terminal of the frequency divider 902 has an output frequency of 208M. The CLK terminal of the frequency divider 903 has an input frequency of 832M, the d terminal inputs a signal of 104M, and the signal of 104M is a signal output from the Q terminal 603 in the embodiment shown in fig. 6, and the output frequency of the Q terminal of the frequency divider 903 is 104M. The CLK terminal of the frequency divider 904 has an input frequency of 832M, the d terminal has a signal of 52M, and the 52M signal is the signal output from the Q terminal 604 in the embodiment shown in fig. 6, and the Q terminal of the frequency divider 904 has an output frequency of 52M. The CLK terminal of the frequency divider 905 has an input frequency of 522M, the d terminal has an input of 26M, and the 26M signal is the signal output from the Q terminal 605 in the embodiment shown in fig. 6, and the Q terminal of the frequency divider 905 has an output frequency of 26M.

In the embodiment shown in fig. 9, each count signal is sampled by clk_832m_1, and is delayed by t_delay from clk_832m_1. But have no delay effect with respect to each other. At this time, when only the low order bits are to be decoded, 1100 is decoded as the start data to 001. Therefore, in time measurement, the error of logic gate delay to the high-precision TDC is eliminated, and the ranging precision can be improved. The embodiment shown in fig. 9 ensures the range of the TDC and the ranging accuracy.

FIG. 10 illustrates a sampled binary counter waveform diagram in which an embodiment of the present invention may be implemented. As shown in fig. 10, includes: a first clock (CLK 832 m_1) 1001, a second clock (CLK 416M) 1002, a third clock (CLK 208M) 1003, a fourth clock (CLK 104M) 1004, a fifth clock (CLK 52M) 1005, a sixth clock (CLK 26M) 1006, and a stop signal 1007. The embodiment shown in fig. 10 shows that in time measurement, the error of logic gate delay to high-precision TDC is eliminated, and the ranging precision is improved.

Various embodiments of the invention are described herein, but for brevity, description of each embodiment is not exhaustive and features or parts of the same or similar between each embodiment may be omitted. Herein, "one embodiment," "some embodiments," "example," "specific example," or "some examples" means that it is applicable to at least one embodiment or example, but not all embodiments, according to the present invention. The above terms are not necessarily meant to refer to the same embodiment or example. Those skilled in the art may combine and combine the features of the different embodiments or examples described in this specification and of the different embodiments or examples without contradiction.

The exemplary systems and methods of the present invention have been particularly shown and described with reference to the foregoing embodiments, which are merely examples of the best modes for carrying out the systems and methods. It will be appreciated by those skilled in the art that various changes may be made to the embodiments of the systems and methods described herein in practicing the systems and/or methods without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A frequency dividing circuit comprising at least one master frequency divider and at least one slave frequency divider;

2. The frequency divider circuit of claim 1, wherein a first input of the first master frequency divider and a first input of the first slave frequency divider are each coupled to an oscillator, the first master frequency divider and the first slave frequency divider receiving the first clock signal transmitted by the oscillator;

3. The frequency divider circuit of claim 1, wherein at least one of the master frequency dividers further comprises: a second master frequency divider, at least one of the slave frequency dividers further comprising: a second slave frequency divider;

4. The frequency divider circuit of claim 3, wherein a first input of the second main frequency divider is connected to a second output of the first main frequency divider, and the second main frequency divider obtains the first temporary signal output by the second output of the first main frequency divider through the first input;

5. The frequency divider circuit of any one of claims 1 to 4, wherein the first master frequency divider and the first slave frequency divider are D flip-flops.

6. The frequency divider circuit according to any one of claims 1 to 4, wherein the first clock signal is a binary signal.

7. A time-to-digital converter, comprising: voltage controlled oscillator, and frequency dividing circuit as claimed in any one of claims 1 to 6.

8. A detection apparatus, characterized by comprising: a pulsed light source, a detector array and a processing module, and a time-to-digital converter as claimed in claim 7.

9. A detection system comprising a detection device according to claim 8.