CN116317621A

CN116317621A - Power supply circuit and electronic equipment

Info

Publication number: CN116317621A
Application number: CN202310275363.5A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Zheng Ruji
Current assignee: Zheng Ruji
Priority date: 2023-03-20
Filing date: 2023-03-20
Publication date: 2023-06-23

Abstract

The invention discloses a power supply circuit and an electronic device, wherein the power supply circuit comprises: the driving circuit comprises a driving chip, a transformer, a first power switch, a second power switch and an output capacitor; the transformer has a primary winding and an auxiliary winding; the main-stage winding and the auxiliary winding have homonymous ends at the same position; the driving chip controls the switching time sequence of the first power switch and the second power switch, so that the power circuit has lower switching loss.

Description

Power supply circuit and electronic equipment

Technical Field

The invention relates to the technical field of power supply conversion, in particular to a power supply circuit and electronic equipment.

Background

The prior art power supply circuit includes a buck power supply circuit, a boost power supply circuit, and a buck-boost power supply circuit, as shown in fig. 1a, a first prior art power supply circuit 11, including an EMI filter rectifying module 110, an input capacitor CIN, an inductor L1, a first prior art driver chip 121, a current detection resistor Rcs, a freewheeling diode D1, an output capacitor CO, and a load.

The second existing power supply circuit 12 shown in fig. 1b includes an EMI filter rectifying module 110, an input capacitor CIN, an inductor L1, a second existing driver chip 122, a current detection resistor Rcs, a freewheeling diode D1, an output capacitor CO, and a load.

The third prior art power supply circuit 13 shown in fig. 1c includes an EMI filter rectifying module 110, an input capacitor CIN, an inductance L1, a third prior art driver chip 123, a current detection resistor Rcs, a freewheeling diode D1, an output capacitor CO, and a load.

The power supply circuit in the prior art mainly adopts a working mode of critical conduction of an inductor L1, as shown in a part of working waveforms of the prior power supply circuit in fig. 3, when a pulse width modulation signal PWM in a driving chip is at a high level, a power switch in the driving chip is conducted, the voltage of a switch node SW becomes a low level, the inductor L1 is charged, and the inductor current I1 is linearly increased; when the pulse width modulation signal PWM in the driving chip is at a low level, a power switch in the driving chip is cut off, the voltage of a switch node SW becomes a high level, the inductor L1 discharges, and the inductor current I1 linearly decreases; when the inductor current I1 discharges to zero, LC resonance occurs between the inductor L1 and the parasitic capacitance Coss of the switch node SW, and when the voltage of the switch node SW resonates to the valley, the driving chip turns on the power switch in the driving chip again to enter the next switching period.

However, even if the voltage of the switching node SW is switched to the next period after resonating to the lowest point, the voltage of the node SW still has a voltage Vds across the power switch with a very high absolute value in most cases, so the power switch still generates a very large switching loss ploss=0.5×coss×vds 2×f, where coss=cds+cgd is the parasitic capacitance of the node SW, and f is the operating frequency of the power switch. Especially when the power switch is operated at high input voltage and high frequency, the switching loss is a main source of the total loss. The disadvantages of the prior art power supply circuit are: the switching loss is large, resulting in reduced efficiency and poor EMI.

Disclosure of Invention

The embodiment of the invention provides a power supply circuit and electronic equipment.

In a first aspect, an embodiment of the present invention provides a power supply circuit including:

the driving circuit comprises a driving chip, a transformer, a first power switch, a second power switch and an output capacitor;

the transformer has a primary winding and an auxiliary winding;

the main-stage winding and the auxiliary winding have homonymous ends at the same position;

the first end of the main stage winding is coupled with the input voltage or coupled with the input voltage after passing through the output capacitor, and the second end of the main stage winding is coupled with the first end of the first power switch;

the first end of the auxiliary winding is coupled with the input voltage or coupled with the input voltage after passing through the output capacitor, and the second end of the auxiliary winding is coupled with the first end of the second power switch;

the driving chip controls the switching time sequence of the first power switch and the second power switch, so that the power circuit has lower switching loss.

Preferably, before the first power switch is controlled to switch from the off state to the on state, the second power switch is controlled to be turned on for a pulse time, so that current flows through the auxiliary winding and the second power switch to the ground, the current flowing through the auxiliary winding is coupled to the primary winding of the transformer through the coupling action of the transformer, the voltage across the two ends of the first power switch is reduced from the initial first potential to the lower second potential, and then the power circuit is controlled to switch from the off state to the on state, so that the switching loss of the power circuit is lower.

Preferably, before the first power switch is controlled to be switched from the off state to the on state, the second power switch is controlled to be turned on for a pulse time, so that the current flowing through the auxiliary winding and the second power switch charges the power supply capacitor, the current flowing through the auxiliary winding is coupled to the main-stage winding of the transformer through the coupling action of the transformer, the voltage across the two ends of the first power switch is reduced from the initial first potential to the lower second potential, and then the power circuit is controlled to be switched from the off state to the on state, so that the switching loss of the power circuit is lower.

Preferably, the driving chip is provided with at least 4 pins;

the 1 st pin is coupled with the control end of the second power switch;

the 2 nd pin is coupled with the control end of the first power switch;

the 3 rd pin is coupled with the second end of the first power switch;

the 4 th pin is coupled to ground.

Preferably, the driving chip integrates a second power switch, and the driving chip is provided with at least 4 pins;

the 1 st pin is coupled with a first end of a second power switch in the chip and a second end of the auxiliary winding;

the 2 nd pin is coupled with the control end of the first power switch;

the 3 rd pin is coupled with the second end of the first power switch;

the 4 th pin is coupled to ground.

Preferably, the driving chip is integrated with a first power switch, and the driving chip is provided with at least 3 pins;

the 1 st pin is coupled with the control end of the second power switch;

the 2 nd pin is coupled with a first end of a first power switch in the chip and a second end of the main-stage winding;

the 3 rd pin is coupled to ground.

Preferably, the driving chip integrates a first power switch and a second power switch, and the driving chip is provided with at least 4 pins;

the 3 rd pin is coupled with the second end of the first power switch in the chip and the current detection resistor;

the 4 th pin is coupled to ground.

Preferably, the driving chip integrates a first power switch and a second power switch, and the driving chip is provided with at least 3 pins;

the 3 rd pin is coupled to ground.

Preferably, the main winding, the first power switch and the freewheeling diode of the power circuit may be combined to form at least one of a buck power circuit structure, a boost power circuit structure and a boost power circuit structure.

In a second aspect, an embodiment of the present invention provides an electronic device, including the power supply circuit according to any one of the first aspects.

The technology of the invention has the following advantages:

according to the power supply circuit provided by the embodiment of the invention, the switching loss of the power supply circuit can be effectively reduced, the efficiency of the power supply circuit is improved, and the cost is reduced.

Drawings

FIGS. 1 a-1 c are prior art power supply circuits;

FIGS. 2a to 2h illustrate a power circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a partial node waveform of a prior art power circuit;

FIG. 4 is a schematic diagram of a partial node waveform of an embodiment of the present invention.

Various features and elements are not drawn to scale in accordance with conventional practice in the drawings in order to best illustrate the specific features and elements associated with the invention. In addition, like elements/components are referred to by the same or similar reference numerals among the different drawings.

[ reference numerals description ]

11 to 13: first to third existing power supply circuits

110: EMI filtering rectification module

121 to 123: first to third existing driving chips

21 to 28: first to eighth power supply circuits

221 to 227: first to eighth driving chips

[ symbolic description ]

MP: first power switch

MA: second power switch

Vds: cross-over pressure

Coss: parasitic capacitance

TB transformer

Npa: turns ratio

Lp: main-stage winding

La: auxiliary winding

Ip: main stage winding current

Ia: auxiliary winding current

Rcs: current detection resistor

CP: power supply capacitor

CIN: input capacitance

CO: output capacitor

VIN: input voltage

VO: output voltage

D1: flywheel diode

T1-T3: time point

T12: during a first period

T23: second period

T13: pulse time.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In a first aspect, the present invention provides a power supply circuit. The first power supply circuit 21 shown in fig. 2a includes an EMI filter rectifying module 110, an input capacitor CIN, a first driving chip 221, a first power switch MP, a second power switch MA, a power supply capacitor CP, and a current detection resistor Rcs; the input end of the EMI filtering rectifying module 110 is coupled to an ac power supply, and outputs a dc input voltage VIN after EMI filtering and rectification; the input capacitor CIN is used for filtering high-frequency noise of the input voltage VIN; the transformer TB has a main winding Lp and an auxiliary winding La, the main winding Lp and the auxiliary winding La have identical-name ends at identical positions, (for the sake of more concise description of the working principle of the invention, it is assumed that the auxiliary winding La and the main winding Lp have identical winding turns, the turns ratio npa=1; a first end of the auxiliary winding La is coupled to the input voltage VIN, and a second end of the auxiliary winding La is coupled to a first end of the second power switch MA; the first driving chip 221 is coupled to the control terminals of the first power switch MP and the second power switch MA, and the first power circuit 21 controls the switching timing of the first power switch MP and the second power switch MA through the first driving chip 221, so that the first power circuit 21 has lower switching loss.

In one embodiment, the first power switch MP and the second power switch MA may use a power triode BJT or a power metal semiconductor field effect transistor MOSFET, or output a higher power IGBT or a gallium nitride power tube GaN.

The homonymous ends of the two windings of the transformer are defined as follows: when current flows into (or out of) two windings simultaneously from one end of each winding respectively, if magnetic fluxes generated by the two windings are aided, the two ends are called as homonymous ends of the transformer winding, and black dots "·" or asterisks are used for marking. The positions of the homonymous terminals can be defined by themselves, the inflow terminals can be called homonymous terminals, and the outflow terminals can be called homonymous terminals.

In one embodiment, as shown in fig. 2a, the driving chip 221 in the first power circuit 21 has 5 pins; the 1 st pin GA is coupled with the control end of the second power switch MA; the 2 nd pin GP is coupled with the control end of the first power switch MP; the 3 rd pin CS is coupled to the second end of the first power switch MP and the current detection resistor Rcs; the 4 th pin GND is coupled to the ground; the 5 th pin VCC is coupled to the power supply capacitor CP. (it should be noted that the names of the pins of all chips are only examples, so that the technology of the present invention is easy to understand, but not limited to, and the scope of the present invention is defined by the claims of the present invention

When the 2 nd pin GP of the first driving chip 221 outputs a high level to the control terminal of the first power switch MP, the first power switch MP is turned on, the input voltage VIN charges the main winding Lp of the transformer TB through the output capacitor CO and the load, the first power switch MP and the current detection resistor Rcs, the voltage drop on the main winding Lp is approximately VIN-VO (neglecting the conduction voltage drop of the first power switch MP), since the auxiliary winding La and the main winding Lp have the same-named terminals at the same position, when the auxiliary winding La and the main winding Lp have the same winding turns, the voltage drop on the auxiliary winding La with the turns ratio npa=1 (assuming but not limited to) is also approximately VIN-VO, the potential on the first terminal of the auxiliary winding La is the input voltage VIN, and the potential on the second terminal of the auxiliary winding La is VIN- (VO) =vo during the charging of the main winding Lp; after the 2 nd pin GP of the first driving chip 221 changes from high level to low level, the first power switch MP is turned off, the main winding Lp of the transformer TB starts to discharge, and during the discharging period, the main winding Lp discharges approximately with the output voltage VO (ignoring the on-voltage drop of the freewheeling diode), so the voltage drop on the main winding Lp is approximately-VO, and the voltage drop on the auxiliary winding La is also-VO; during the discharge of the main stage winding Lp, the potential at the second end of the main stage winding Lp is VIN, and the potential at the second end of the auxiliary winding La is vin+vo.

In one embodiment, the second terminal of the second power switch MA is coupled to ground, and the working principle of the present invention can be further clarified by combining the first power circuit 21 of fig. 2a with the partial node waveform schematic diagram of fig. 4. Before the 2 nd pin GP of the first driving chip 221 outputs a high level to control the first power switch MP to switch from an off state to an on state, the 1 st pin GA outputs a high level to lead the second power switch MA to be led for a pulse time T13, so that current flows through the auxiliary winding La and the second power switch MA to the ground, the auxiliary winding current Ia flowing through the auxiliary winding La is coupled to the main winding Lp of the transformer TB to form a main winding current Ip with opposite current directions through the coupling action of the transformer TB, the main winding current Ip transfers energy on the parasitic capacitance Coss of the first end of the first power switch MP to the main winding Lp, after the voltage across Vds of both ends of the first power switch MP is reduced from the initial first potential VIN to a lower second potential, the 2 nd pin GP of the first driving chip 221 outputs a high level to control the first power switch MP to switch from the off state to the on state, and the switching loss of the first power circuit 21 is lower. In one embodiment, the second potential across the voltage Vds across the first power switch MP is zero or approximately zero. Since the primary winding current Ip transfers energy from the parasitic capacitance Coss at the first end of the first power switch MP to the primary winding Lp, the voltage drop Vds across the first power switch MP decreases from VIN to zero, resulting in an increase in the voltage drop across the primary winding Lp from initial-VO to VIN-VO, increasing VIN, and the voltage drop across the auxiliary winding La also increases VIN through the coupling of the transformer TB, so the second end potential of the auxiliary winding La decreases to VO, and during the conduction of the first power switch MP the second end potential of the auxiliary winding La remains VO.

Since the auxiliary winding current Ia and the main winding current Ip are opposite in direction, the first power switch MP and the second power switch MA are prevented from being simultaneously turned on.

Therefore, the invention realizes that the power supply circuit works in a Zero Voltage Switching (ZVS) state, has lower switching loss, higher conversion efficiency and lower EMI interference.

In one embodiment, the second terminal of the second power switch MA is coupled to the power supply capacitor CP, and the working principle of the present invention can be further clarified by combining the first power circuit 21 of fig. 2a with the partial node waveform schematic diagram of fig. 4. Before the 2 nd pin GP of the first driving chip 221 outputs a high level to control the first power switch MP to switch from an off state to an on state, the 1 st pin GA outputs a high level to lead the second power switch MA to be led for a pulse time T13, so that the current flowing through the auxiliary winding La and the second power switch MA charges the power supply capacitor CP, the auxiliary winding current Ia flowing through the auxiliary winding La is coupled to the main winding Lp of the transformer TB to form a main winding current Ip with opposite current directions through the coupling action of the transformer TB, the main winding current Ip transfers the energy on the parasitic capacitor Coss at the first end of the first power switch MP to the main winding Lp, after the voltage across Vds at both ends of the first power switch MP is reduced from the initial first potential vin+vo to a lower second potential, the 2 nd pin GP of the first driving chip 221 outputs a high level to control the first power switch MP to switch from the off state to the on state, so that the switching loss of the first power circuit 21 is lower. The power supply capacitor CP recovers the auxiliary winding current Ia to supply power to the driving chip, and further improves the efficiency of the power supply circuit. In one embodiment, the second potential is zero or approximately zero. Since the primary winding current Ip transfers energy from the parasitic capacitance Coss at the first end of the first power switch MP to the primary winding Lp, the voltage drop Vds across the first power switch MP decreases from VIN to zero, resulting in an increase in the voltage drop across the primary winding Lp from initial-VO to VIN-VO, increasing VIN, and the voltage drop across the auxiliary winding La also increases VIN through the coupling of the transformer TB, so the second end potential of the auxiliary winding La decreases to VO, and during the conduction of the first power switch MP the second end potential of the auxiliary winding La remains VO.

In the waveform diagram shown in fig. 4, the time point T1 corresponds to a time point when the second power switch MA is turned on prior to the first power switch MP, and in one embodiment, the time point T1 is generated in response to the demagnetization end signal of the transformer TB; in one embodiment, the T1 time point is generated in response to one trough of the voltage across Vds of the first power switch MP (or the first trough or the nth trough), and after the demagnetization of the transformer TB is finished, LC resonance occurs between the main winding Lp and the parasitic capacitance Coss of the first end of the first power switch MP, and a plurality of troughs are generated on the voltage across Vds of the first power switch MP; in one embodiment, the T1 time point is generated in response to a pulse width modulated signal (PWM signal) of the power supply circuit.

In the waveform diagram shown in fig. 4, the time point T3 corresponds to the on time point of the first power switch MP, the period between the time point T1 and the time point T3 is the pulse time T13 for the second power switch MA to be turned on, the length of the pulse time T13 and the magnitude of the auxiliary winding current Ia flowing through the auxiliary winding La determine the magnitude of the voltage across Vds across the first power switch MP from the initial first potential VIN to the lower second potential, and in one embodiment, the first power switch MP is turned on again after the second potential approaches zero potential by optimizing the width of the pulse time T13 and the magnitude of the auxiliary winding current Ia, so as to realize the switching of the first power switch MP in the zero voltage state or the state with lower switching loss.

In the waveform diagram shown in fig. 4, the time point T3 is the off time point of the second power switch MA and is also the on time point of the first power switch MP, and in one embodiment, the off time point of the second power switch MA is a time point T2 between the time point T1 and the time point T3, which corresponds to that the second power switch MA is not turned on during the whole pulse time T13, but is turned on only during the first period T12 of the pulse time T13, and is turned off during the second period T23, which corresponds to that T23 is the dead time of the first power switch MP and the second power switch MA.

In one embodiment, as shown in fig. 2b for the second power circuit 22, the second power circuit 22 further comprises a second driver chip 222, in which the second power switch MA is integrated and has 5 pins; pin 1 DA is coupled to a first end of a second power switch MA within the chip and to a second end of the auxiliary winding La; the 2 nd pin GP is coupled with the control end of the first power switch MP; the 3 rd pin CS is coupled to the second end of the first power switch MP and the current detection resistor Rcs; the 4 th pin GND is coupled to the ground; the 5 th pin VCC is coupled to the power supply capacitor CP. The second power supply circuit 22 and the first power supply circuit 21 control the switching time sequence of the first power switch MP and the second power switch MA in the same control manner, and the switching loss of the power supply circuits is reduced by using the same working principle, and the difference between the two is that the second driving chip 222 in the second power supply circuit 22 integrates the second power switch MA into a chip.

In one embodiment, as shown in the third power circuit 23 of fig. 2c, the third power circuit 23 further comprises a third driving chip 223, wherein the driving chip is integrated with the first power switch MP and has 4 pins; the 1 st pin GA is coupled with the control end of the second power switch MA; the 2 nd pin DP is coupled to the first end of the first power switch MP and the second end of the main winding Lp; the 3 rd pin GND is coupled to ground; the 4 th pin VCC is coupled to the power supply capacitor CP. The third power supply circuit 23 and the first power supply circuit 21 control the switching time sequence of the first power switch MP and the second power switch MA in the same control manner, and the switching loss of the power supply circuits is reduced by using the same working principle, and the difference between the two is that the third driving chip 223 in the third power supply circuit 23 integrates the first power switch MP and the current detection resistor Rcs into a chip.

In one embodiment, as shown in the fourth power circuit 24 of fig. 2d, the fourth power circuit 24 further includes a fourth driving chip 224, in which the first power switch MP and the second power switch MA are integrated and have 5 pins; pin 1 DA is coupled to a first end of a second power switch MA within the chip and to a second end of the auxiliary winding La; the 2 nd pin DP is coupled to the first end of the first power switch MP and the second end of the main winding Lp; the 3 rd pin CS is coupled to the second end of the first power switch MP and the current detection resistor Rcs in the chip; the 4 th pin GND is coupled to the ground; the 5 th pin VCC is coupled to the power supply capacitor CP. The fourth power supply circuit 24 and the first power supply circuit 21 control the switching time sequences of the first power switch MP and the second power switch MA in the same control manner, and the switching loss of the power supply circuits is reduced by using the same working principle, and the difference between the two is that the fourth driving chip 224 in the fourth power supply circuit 24 integrates the first power switch MP and the second power switch MA into a chip.

In one embodiment, as shown in the fifth power circuit 25 in fig. 2e, the fifth power circuit 25 further includes a fifth driving chip 225, and the driving chip has a first power switch MP, a second power switch MA, a current detection resistor Rcs, and a power supply capacitor CP integrated therein and has 3 pins; pin 1 DA is coupled to a first end of a second power switch MA within the chip and to a second end of the auxiliary winding La; the 2 nd pin DP is coupled to the first end of the first power switch MP and the second end of the main winding Lp; the 3 rd pin GND is coupled to ground. The fifth power supply circuit 25 and the first power supply circuit 21 control the switching time sequences of the first power switch MP and the second power switch MA in the same control manner, and reduce the switching loss of the power supply circuit by using the same operating principle, which is different in that the fifth driving chip 225 in the fifth power supply circuit 25 integrates the first power switch MP, the second power switch MA, the current detection resistor Rcs and the power supply capacitor CP into a chip.

In one embodiment, as shown in the sixth power circuit 26 of fig. 2f, the sixth power circuit 26 further includes a sixth driver chip 226, in which the second power switch MA is integrated and has 5 pins; pin 1 DA is coupled to a first end of a second power switch MA within the chip and to a second end of the auxiliary winding La; the 2 nd pin GP is coupled with the control end of the first power switch MP; the 3 rd pin CS is coupled to the second end of the first power switch MP and the current detection resistor Rcs; the 4 th pin GND is coupled to the ground; the 5 th pin VCC is coupled to the power supply capacitor CP. The sixth power supply circuit 26 and the second power supply circuit 22 control the switching time sequences of the first power switch MP and the second power switch MA in the same control manner, and reduce the switching loss of the power supply circuits by using the same operating principle, and the difference between the two is that the first end of the auxiliary winding La in the sixth power supply circuit 26 is coupled to the second end of the output capacitor CO and the first end of the main winding Lp, which can also be said to be coupled to the input voltage VIN through the output capacitor CO.

In one embodiment, as shown in the seventh power circuit 27 of fig. 2g, the seventh power circuit 27 further includes a seventh driving chip 227, in which the second power switch MA is integrated and has 5 pins; pin 1 DA is coupled to a first end of a second power switch MA within the chip and to a second end of the auxiliary winding La; the 2 nd pin GP is coupled with the control end of the first power switch MP; the 3 rd pin CS is coupled to the second end of the first power switch MP and the current detection resistor Rcs; the 4 th pin GND is coupled to the ground; the 5 th pin VCC is coupled to the power supply capacitor CP. The seventh power supply circuit 27 and the second power supply circuit 22 adopt the same control mode to control the switching time sequence of the first power switch MP and the second power switch MA, and the switching loss of the power supply circuits is reduced by utilizing the same working principle, and the difference between the seventh power supply circuit 27 and the second power supply circuit 22 is that the seventh power supply circuit 27 belongs to a buck-boost power supply circuit structure, and the second power supply circuit 22 belongs to a buck power supply circuit structure; the first end of the main winding Lp of the seventh power circuit 27 is coupled to the input voltage VIN, the second end is coupled to the anode of the freewheeling diode D1, the cathode of the freewheeling diode D1 is coupled to the first end of the output capacitor CO, and the second end of the output capacitor CO is coupled to the input voltage VIN.

In one embodiment, as shown in the eighth power circuit 28 of fig. 2h, the eighth power circuit 28 further comprises an eighth driving chip 228, wherein the driving chip has the second power switch MA integrated therein and has 5 pins; pin 1 DA is coupled to a first end of a second power switch MA within the chip and to a second end of the auxiliary winding La; the 2 nd pin GP is coupled with the control end of the first power switch MP; the 3 rd pin CS is coupled to the second end of the first power switch MP and the current detection resistor Rcs; the 4 th pin GND is coupled to the ground; the 5 th pin VCC is coupled to the power supply capacitor CP. The eighth power supply circuit 28 and the second power supply circuit 22 adopt the same control mode to control the switching time sequence of the first power switch MP and the second power switch MA, and the switching loss of the power supply circuits is reduced by utilizing the same working principle, and the difference between the eighth power supply circuit 28 and the second power supply circuit 22 is that the eighth power supply circuit 28 belongs to a boosting power supply circuit structure and the second power supply circuit 22 belongs to a step-down power supply circuit structure; the first end of the main winding Lp of the eighth power circuit 28 is coupled to the input voltage VIN, the second end is coupled to the anode of the freewheeling diode D1, the cathode of the freewheeling diode D1 is coupled to the first end of the output capacitor CO, and the second end of the output capacitor CO is coupled to ground.

The seventh power supply circuit 27 and the eighth power supply circuit 28 may also be integrated into the driver chip simultaneously or partly with the first power switch MP, the second power switch MA, the current sense resistor Rcs and the supply capacitor CP, like the buck power supply circuit, which will not be repeated here.

From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

1) The power supply circuit and the electronic equipment reduce the switching loss of the power supply circuit, improve the conversion efficiency and reduce the EMI interference of the power supply circuit.

It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

It should also be noted that, in this document, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Moreover, relational terms such as "first" and "second" may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions, or order, and without necessarily being construed as indicating or implying any relative importance. "and/or" means either or both of which may be selected. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device comprising the element.

The foregoing has outlined rather broadly the more detailed description of the invention in order that the detailed description of the invention that follows may be better understood, and in order that the present contribution to the art may be better appreciated. While various modifications of the embodiments and applications of the invention will occur to those skilled in the art, it is not necessary and not intended to be exhaustive of all embodiments, and obvious modifications or variations of the invention are within the scope of the invention.

Claims

1. A power supply circuit, the power supply circuit comprising:

the transformer has a primary winding and an auxiliary winding;

2. The power circuit of claim 1, wherein the power circuit controls the second power switch to be turned on for a pulse time before the first power switch is controlled to be turned on from the off state, so that current flows through the auxiliary winding and the second power switch to the ground, the current flowing through the auxiliary winding is coupled to the primary winding of the transformer through the coupling action of the transformer, so that the voltage across the first power switch is reduced from the initial first potential to the lower second potential, and the power circuit controls the first power switch to be turned on from the off state again, so that the switching loss of the power circuit is lower.

3. The power circuit of claim 1, wherein the power circuit controls the second power switch to be turned on for a pulse time before the first power switch is controlled to be turned on from the off state, so that the current flowing through the auxiliary winding and the second power switch charges the power supply capacitor, the current flowing through the auxiliary winding is coupled to the primary winding of the transformer through the coupling action of the transformer, so that the voltage across the first power switch is reduced from the initial first potential to the lower second potential, and the power circuit controls the first power switch to be turned on from the off state again, so that the switching loss of the power circuit is lower.

4. A power supply circuit according to any one of claims 1 to 3, wherein the driver chip has at least 4 pins;

the 1 st pin is coupled with the control end of the second power switch;

the 2 nd pin is coupled with the control end of the first power switch;

the 3 rd pin is coupled with the second end of the first power switch;

the 4 th pin is coupled to ground.

5. A power supply circuit according to any one of claims 1 to 3, wherein the driver chip integrates a second power switch, the driver chip having at least 4 pins;

the 2 nd pin is coupled with the control end of the first power switch;

the 3 rd pin is coupled with the second end of the first power switch;

the 4 th pin is coupled to ground.

6. A power supply circuit according to any one of claims 1 to 3, wherein the driver chip integrates a first power switch, the driver chip having at least 3 pins;

the 1 st pin is coupled with the control end of the second power switch;

the 3 rd pin is coupled to ground.

7. A power supply circuit according to any one of claims 1 to 3, wherein the driver chip integrates a first power switch and a second power switch, the driver chip having at least 4 pins;

the 4 th pin is coupled to ground.

8. A power supply circuit according to any one of claims 1 to 3, wherein the driver chip integrates a first power switch and a second power switch, the driver chip having at least 3 pins;

the 3 rd pin is coupled to ground.

9. A power supply circuit according to any one of claims 1 to 3, wherein the main stage winding, the first power switch and the freewheeling diode of the power supply circuit are combinable to form at least one of a buck power supply circuit configuration, a boost power supply circuit configuration and a buck-boost power supply circuit configuration.

10. An electronic device comprising the power supply circuit of any one of claims 1 to 9.