CN116317547B - Step-down circuit with through mode - Google Patents
Step-down circuit with through mode Download PDFInfo
- Publication number
- CN116317547B CN116317547B CN202310205442.9A CN202310205442A CN116317547B CN 116317547 B CN116317547 B CN 116317547B CN 202310205442 A CN202310205442 A CN 202310205442A CN 116317547 B CN116317547 B CN 116317547B
- Authority
- CN
- China
- Prior art keywords
- circuit
- resistor
- signal
- voltage
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 claims description 12
- MZAGXDHQGXUDDX-JSRXJHBZSA-N (e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/C(N)=O MZAGXDHQGXUDDX-JSRXJHBZSA-N 0.000 claims description 12
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 claims description 12
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 claims description 12
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 claims description 12
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 claims description 12
- 101150070189 CIN3 gene Proteins 0.000 claims description 9
- 101150110971 CIN7 gene Proteins 0.000 claims description 9
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 9
- 101100508840 Daucus carota INV3 gene Proteins 0.000 claims description 9
- 101150110298 INV1 gene Proteins 0.000 claims description 9
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 9
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims description 4
- 230000001960 triggered effect Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000002035 prolonged effect Effects 0.000 description 4
- 238000013459 approach Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/125—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M3/135—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
- H02M3/137—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to a power supply voltage conversion circuit, in particular to a voltage reduction circuit with a through mode. It comprises a driving circuit 5, an acquisition circuit, a first comparison circuit, a second comparison circuit, a timer 6 and a logic circuit 4. The logic circuit comprises a delay unit, wherein the delay unit is internally provided with a minimum turn-off time MIN_TOFF of the upper power tube MP, and when the input voltage VIN is slightly larger than the output voltage VOUT, the upper power tube MP is turned on after waiting the minimum turn-off time MIN_TOFF after the input signal PWM becomes high level. When the signal PWM is at a high level, the logic circuit controls the driving signal hsd_gt generated by the driving circuit to be at a high level, and then the pass-through is realized when the input voltage VIN of the voltage-reducing circuit is equal to or lower than the output voltage VOUT. The voltage-reducing circuit has low cost and small design difficulty.
Description
Technical Field
The invention relates to a power supply voltage conversion circuit, in particular to a voltage reduction circuit with a through mode.
Background
In a dc switch-mode buck circuit of a conventional structure, when the input voltage is very close to or lower than the set output voltage value, a low dropout regulator (i.e. LDO) is usually added to supply the output voltage. When the input voltage rises and is larger than a certain output value, the LDO is turned off, and the circuit is enabled to work in a switch step-down mode again. Thus, when the input voltage is low, the output reaches the set value as much as possible, and the output voltage is ensured not to exceed the set value. However, this solution requires an addition of one LDO, resulting in a higher cost of the entire step-down circuit, while also increasing the complexity of the design.
Disclosure of Invention
The invention aims to provide a voltage reduction circuit with a through mode, which has low cost and low design difficulty.
In order to solve the problems, the following technical scheme is provided:
the step-down circuit with the through mode of the invention is characterized by comprising:
the driving circuit is used for generating a driving signal HSD_GT for driving the switching state of the power tube MP on the voltage reducing circuit and a driving signal LSD_GT for driving the switching state of the power tube MN under the voltage reducing circuit.
And the acquisition circuit is used for acquiring the voltage signal of the step-down circuit SW point and outputting a RAMP signal SW_RAMP.
And a first comparison circuit including an error amplifier for comparing the feedback voltage FB of the step-down circuit with the reference voltage signal VREF and outputting a signal ea_out according to the comparison result.
The second comparison circuit includes a comparator for comparing the RAMP signal sw_ramp with the signal ea_out and outputting the signal PWM according to the comparison result.
The timer is used for calculating the on time of the upper power tube MP and outputting a signal TON_END.
The logic circuit is used for controlling the types of the driving signals HSD_GT and the driving signals LSD_GT generated by the driving circuit according to the signals TON_END and the signals PWM, and further controlling the switching states of the upper power tube MP and the lower power tube MN. The logic circuit comprises a delay unit, wherein the delay unit is internally provided with a minimum turn-off time MIN_TOFF of the upper power tube MP, and when the input voltage VIN is slightly larger than the output voltage VOUT, the upper power tube MP is turned on after waiting the minimum turn-off time MIN_TOFF after the input signal PWM becomes high level. When the signal PWM is at a high level, the logic circuit controls the driving signal hsd_gt generated by the driving circuit to be at a high level, and then the pass-through is realized when the input voltage VIN of the voltage-reducing circuit is equal to or lower than the output voltage VOUT.
Wherein the logic circuit comprises an input port R, an input port S, an output port HSD_ON and an output port LSD_ON; the output end of the comparator is connected with the input port R of the logic circuit and is used for inputting a signal PWM to the logic circuit; the timer is connected with the input port S of the logic circuit and is used for inputting a signal TON_END to the logic circuit; the output port HSD_ON and the output port LSD_ON of the logic circuit are connected with the driving circuit.
The logic circuit comprises an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3, a NAND gate NAND and a D flip-flop; and the CLK end of the D trigger is triggered by a rising edge, and when the input signal of the R end of the D trigger is 0, the Q end of the D trigger is output as 0. The input end of the inverter INV1 is the input port S, the output end of the inverter INV1 is connected with one input end of the NOR gate NOR1, the other input end of the NOR gate NOR1 is the input port R, the output end of the NOR gate NOR1 is connected with one input end of the NOR gate NOR2, the other input end of the NOR gate NOR2 is connected with the output end of the NOR gate NOR3, the output end of the NOR gate NOR2 is connected with one input end of the NOR gate NOR3, the input end of the NOR gate NOR3 is connected with the other input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3 and one input end of the NAND gate NAND respectively, the output end of the inverter INV5 is connected with a delay unit and the other input end of the NAND gate NAND respectively, the delay unit is connected with the R end of the D trigger, the input voltage is connected with the D end of the D trigger INV, the Q end of the D trigger is connected with the input end of the inverter INV5, the output end of the inverter INV3 is the output end of the LSON trigger; the NAND output end of the NAND gate is connected with the input end of the inverter INV4, and the output end of the inverter INV4 is the output port HSD_ON.
The acquisition circuit comprises a resistor R1 and a resistor R2, one end of the resistor R1 is connected with the SW point of the voltage reduction circuit, the other end of the resistor R1 is connected with one end of the resistor R2, the other end of the resistor R2 is grounded, and the two ends of the resistor R2 are connected with a capacitor C1 in parallel. One end of a resistor R1 connected with the resistor R2 is connected with the reverse input end of the comparator, and one end of the resistor R1 connected with the resistor R2 forms the RAMP signal SW_RAMP.
The first comparison circuit comprises a resistor RF1 and a resistor RF2, the output voltage VOUT is connected with one end of the resistor RF1, the other end of the resistor RF1 is connected with one end of the resistor RF2, and the other end of the resistor RF2 is grounded; one end of a resistor RF1 connected with the resistor RF2 is connected with the inverting input end of the error amplifier, and one end of the resistor RF1 connected with the resistor RF2 forms the feedback voltage FB. The reference voltage signal VREF is connected with the non-inverting input end of the error amplifier, and the output end of the error amplifier is connected with the non-inverting input end of the comparator.
By adopting the scheme, the method has the following advantages:
because the logic circuit of the voltage reduction circuit with the through mode comprises the delay unit, the minimum turn-off time MIN_TOFF of the upper power tube MP is arranged in the delay unit, when the input voltage VIN is slightly larger than the output voltage VOUT, after the input signal PWM becomes high level, the upper power tube MP is started after waiting for the minimum turn-off time MIN_TOFF, thereby realizing the self-adaptive extension of the turn-on time. When the signal PWM is at a high level, the logic circuit controls the driving signal hsd_gt generated by the driving circuit to be at a high level, and then when the input voltage VIN of the voltage-reducing circuit is equal to or lower than the output voltage VOUT, the pass-through is realized. Thus, the step-down circuit of the present invention maintains the output voltage at the set value as much as possible when the input approaches the output voltage. When the input voltage is equal to or lower than the output voltage, the step-down circuit of the invention always turns on the upper power tube MP, so that the output voltage is as close to the input voltage as possible. Compared with the traditional direct current switch type voltage reduction circuit, the low-dropout linear voltage regulator does not need to be used, the cost is reduced, and the design is simplified.
Drawings
Fig. 1 is a schematic diagram of a buck circuit with a pass-through mode of the present invention;
FIG. 2 is a schematic diagram of a logic circuit in a buck circuit with a pass-through mode according to the present invention;
FIG. 3 is a diagram showing the related signal waveforms of the voltage step-down circuit with the pass-through mode when the voltage difference between the input voltage VIN and the output voltage VOUT is large enough;
FIG. 4 is a diagram showing the waveforms of the related signals of the voltage step-down circuit with the pass-through mode according to the present invention when the input voltage VIN is slightly larger than the output voltage VOUT;
fig. 5 is a waveform of related signals of the voltage step-down circuit with the pass-through mode according to the present invention when the input voltage VIN is equal to or less than the output voltage VOUT.
Detailed Description
The invention is described in further detail below with reference to figures 1, 2 and examples.
As shown in fig. 1, the voltage reducing circuit with the through mode of the present invention includes an upper power transistor MP, a lower power transistor MN, a driving circuit 5, an acquisition circuit, a first comparison circuit, a second comparison circuit, a timer 6, and a logic circuit 4.
The upper power tube MP is a PMOS tube, and the lower power tube MN is an NMOS tube. The source electrode of the upper power tube MP is connected with the input voltage VIN, the drain electrode of the upper power tube MP is respectively connected with one end of the inductor L and the drain electrode of the lower power tube MN, the drain electrode of the upper power tube MP is the SW point of the voltage reducing circuit, the source electrode of the lower power tube MN is grounded, the other end of the inductor L outputs the voltage VOUT, and the end of the inductor L is respectively connected with the resistor R O And capacitor C O Is connected to one end of resistor R O And capacitor C O The other ends of the two are grounded.
The driving circuit 5 is connected to the gates of the upper power transistor MP and the lower power transistor MN, respectively.
The driving circuit 5 is used for generating a driving signal hsd_gt for driving the switching state of the upper power tube MP and a driving signal lsd_gt for driving the switching state of the lower power tube MN.
The acquisition circuit comprises a resistor R1 and a resistor R2, one end of the resistor R1 is connected with the SW point, the other end of the resistor R1 is connected with one end of the resistor R2, the other end of the resistor R2 is grounded, and the two ends of the resistor R2 are connected with a capacitor C1 in parallel. One end of a resistor R1 connected with the resistor R2 forms a RAMP signal SW_RAMP.
The acquisition circuit is used for acquiring a voltage signal of the SW point of the voltage reduction circuit and outputting a RAMP signal SW_RAMP.
The first comparison circuit comprises a resistor RF1, a resistor RF2 and an error amplifier 2, wherein the output voltage VOUT is connected with one end of the resistor RF1, the other end of the resistor RF1 is connected with one end of the resistor RF2, and the other end of the resistor RF2 is grounded. One end of a resistor RF1 connected with the resistor RF2 is connected with the inverting input terminal of the error amplifier 2, and one end of the resistor RF1 connected with the resistor RF2 forms the feedback voltage FB. The reference voltage signal VREF is connected to the non-inverting input of the error amplifier 2. The output of the error amplifier 2 outputs a signal ea_out. In this embodiment, the reference voltage signal VREF is generated by a reference voltage circuit, which is a prior art and will not be described herein.
The first comparison circuit is used for comparing the feedback voltage FB of the voltage reduction circuit with a reference voltage signal VREF and outputting a signal EA_OUT according to a comparison result.
The second comparison circuit comprises a comparator 3, which comparator 3 is a PWM comparator 3. One end of a resistor R1 connected with the resistor R2 is connected with the reverse input end of the comparator 3, the output end of the error amplifier 2 is connected with the non-inverting input end of the comparator 3, and the output end of the comparator 3 is connected with the logic circuit 4.
The second comparing circuit is used for comparing the RAMP signal sw_ramp with the signal ea_out and outputting the signal PWM to the logic circuit 4 according to the comparison result.
A timer 6 is connected to the logic circuit 4.
The timer 6 is used for calculating the on time of the upper power transistor MP and outputting a signal ton_end.
As shown in fig. 2, the logic circuit 4 includes an input port R, an input port S, an output port hsd_on, and an output port lsd_on. The output terminal of the comparator 3 is connected to the input port R of the logic circuit 4 for inputting the signal PWM to the logic circuit 4. The timer 6 is connected to the input port S of the logic circuit 4 for inputting the signal ton_end to the logic circuit 4. The output port hsd_on and the output port lsd_on of the logic circuit 4 are connected to the driving circuit 5. The logic circuit 4 includes an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3, a NAND gate NAND, a D flip-flop 7, and a delay unit 8. CLK of the D flip-flop 7 is a rising edge trigger, and when the input signal of the R end of the D flip-flop 7 is 0, the Q end of the D flip-flop 7 outputs 0. The input end of the inverter INV1 is the input port S, the output end of the inverter INV1 is connected with one input end of the NOR gate NOR1, the other input end of the NOR gate NOR1 is the input port R, the output end of the NOR gate NOR1 is connected with one input end of the NOR gate NOR2, the other input end of the NOR gate NOR2 is connected with the output end of the NOR gate NOR2, the output end of the NOR gate NOR2 is connected with one input end of the NOR gate NOR3, the input port R is connected with the other input end of the NOR gate NOR3, the output end of the NOR gate NOR3 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3 and one input end of the NAND gate NAND respectively, the output end of the inverter INV5 is connected with the delay unit 8 and the other input end of the NAND gate NAND respectively, the delay unit 8 is connected with the R end of the D flip-flop 7, the input voltage VIN is connected with the D end of the D flip-flop 7, the Q end of the D flip-flop 7 is connected with the output end of the inverter INV3, namely the output end of the inverter INV3 is connected with the output end of the delay unit; the NAND output end of the NAND gate is connected with the input end of the inverter INV4, and the output end of the inverter INV4 is the output port HSD_ON. The delay unit 8 is a prior art, and will not be described herein.
The logic circuit 4 is configured to control types of the driving signal hsd_gt and the driving signal lsd_gt generated by the driving circuit 5 according to the signal ton_end and the signal PWM, so as to control the switching states of the upper power transistor MP and the lower power transistor MN. The logic circuit 4 includes a delay unit 8, in which a minimum off time min_toff of the upper power transistor MP is set, and when the input voltage VIN is slightly greater than the output voltage VOUT, the upper power transistor MP is turned on after waiting for the minimum off time min_toff after the input signal PWM becomes high level. When the signal PWM is at a high level, the logic circuit 4 controls the driving signal hsd_gt generated by the driving circuit 5 to be at a high level, and thus, the pass-through is realized when the input voltage VIN is equal to or lower than the output voltage VOUT.
When the ON time of the upper power transistor reaches the set value under the condition that the input voltage VIN is sufficiently larger than the output voltage VOUT, the signal ton_end is at a high level, the output port hsd_on of the logic circuit 4 outputs a low level, and the output port lsd_on of the logic circuit 4 outputs a high level, that is, the upper power transistor MP is turned off by the driving circuit 5, and the lower power transistor MN is turned ON. Further, when the slope signal sw_ramp starts to fall and is lower than the signal ea_out, the comparator 3 outputs the signal PWM to a high level, i.e. turns off the lower power transistor MN and turns on the upper power transistor MP. And the operation mode of the step-down circuit is a normal pulse width modulation mode. In this mode of operation, the waveforms of the signal SW, the slope signal SW_RAMP, the signal EA_OUT, the signal TON_END and the signal PWM are shown in FIG. 3.
When the input voltage VIN is slightly greater than the output voltage VOUT, in order to ensure that the output voltage is still at the set value, the on-time of the upper power transistor MP must be adaptively prolonged in each period. Because the error amplifier 2 has a large gain, the signal ea_out voltage rises by a sufficiently large voltage value even if the feedback voltage FB is very small compared to the reference voltage VREF. In the ON phase of the upper power transistor MP, even if the output signal ton_end of the timer 6 becomes high, the signal ea_out is still greater than the RAMP signal ramp_sw, the output signal PWM of the comparator 3 is high, the R input terminal of the logic circuit 4 is high, and therefore the output signal hsd_on of the output port hsd_on of the logic circuit 4 is still high, and the upper power transistor MP is still in the ON state. The RAMP signal ramp_sw is still in a rising state, and when the RAMP signal ramp_sw reaches the signal ea_out, the signal PWM outputs a low level. At this time, the signal ton_end is already at a high level, so the output port hsd_on of the logic circuit 4 becomes a low level, and the output port lsd_on becomes a high level, that is, the upper power transistor MP is turned off, and the lower power transistor MN is turned ON. Since the minimum off time min_toff is set in the logic circuit 4, the upper power transistor MP will not be turned on immediately after the signal PWM becomes high. The upper power transistor MP is turned on only after the minimum off time min_toff elapses. In this mode of operation, the waveforms of the signal SW, the slope signal SW_RAMP, the signal EA_OUT, the signal TON_END and the signal PWM are shown in FIG. 4. The on-time of the upper power tube MP in this state is already determined not by the timer 6 but by the output signal PWM of the comparator 3. When the output voltage VOUT is slightly lower than the set value, the time when the signal PWM is high is adaptively prolonged, so that the on time of the upper power tube MP is also prolonged, and the output voltage VOUT is ensured to reach the set value as much as possible.
When the input voltage VIN is equal to or less than the set value of the output voltage VOUT, the actual output voltage is already lower than the set value. At this time, the feedback voltage FB is smaller than the reference voltage VREF, so the voltage of the signal ea_out increases and is larger than the voltage of the slope signal ramp_sw, so the signal PWM is at a high level, the R terminal input of the logic circuit 4 is at a high level, i.e. one input terminal of the NAND gate NAND is at a high level, and the output port hsd_on signal of the logic circuit 4 is at a high level according to the characteristics of the NAND gate NAND. That is, the upper power tube MP is always conducted, and the voltage reducing circuit enters a through mode. In this mode of operation, the waveforms of the signal SW, the slope signal SW_RAMP, the signal EA_OUT, the signal TON_END and the signal PWM are shown in FIG. 5.
In the direct current switch type voltage reducing circuit with the through mode, when the input voltage VIN is close to the output voltage VOUT, the conduction time of the upper power tube can be adaptively prolonged, so that the output voltage VOUT is maintained at a set value as much as possible. When the input voltage VIN is equal to or lower than the output voltage set value, the upper power transistor MP is turned on all the time, so that the actual output voltage is as close to the input voltage VIN as possible. Compared with the traditional direct current switch type voltage reduction circuit, the invention omits the low-dropout linear voltage regulator, reduces the cost and simplifies the design.
Claims (3)
1. A voltage step-down circuit having a through mode, comprising:
the driving circuit (5) is used for generating a driving signal HSD_GT for driving the switching state of the power tube MP on the voltage reduction circuit and a driving signal LSD_GT for driving the switching state of the power tube MN under the voltage reduction circuit;
the acquisition circuit is used for acquiring a voltage signal of the SW point of the voltage reduction circuit and outputting a RAMP signal SW_RAMP;
a first comparison circuit including an error amplifier (2) for comparing a feedback voltage FB of the step-down circuit with a reference voltage signal VREF and outputting a signal EA_OUT according to the comparison result;
a second comparing circuit including a comparator (3) for comparing the RAMP signal sw_ramp with the signal ea_out and outputting a signal PWM according to the comparison result;
a timer (6) for calculating the on time of the upper power tube MP and outputting a signal TON_END;
the logic circuit (4) is used for controlling the types of the driving signals HSD_GT and the driving signals LSD_GT generated by the driving circuit (5) according to the signals TON_END and the signals PWM, and further controlling the switching states of the upper power tube MP and the lower power tube MN; the logic circuit (4) comprises a delay unit (8), wherein the delay unit is internally provided with a minimum turn-off time MIN_TOFF of the upper power tube MP, when the input voltage VIN is slightly larger than the output voltage VOUT, the signal PWM becomes high level, and the upper power tube MP is started after waiting for the minimum turn-off time MIN_TOFF; when the input voltage VIN of the voltage reduction circuit is equal to or lower than the output voltage VOUT, the signal PWM is in a high level, and the logic circuit (4) controls the driving circuit (5) to generate a driving signal HSD_GT so as to realize straight-through;
the logic circuit (4) comprises an input port R, an input port S, an output port HSD_ON and an output port LSD_ON; the output end of the comparator (3) is connected with the input port R of the logic circuit (4) and is used for inputting a signal PWM to the logic circuit (4); the timer (6) is connected with the input port S of the logic circuit (4) and is used for inputting a signal TON_END to the logic circuit (4); the output port HSD_ON and the output port LSD_ON of the logic circuit (4) are connected with the driving circuit (5); the logic circuit (4) comprises an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3, a NAND gate NAND and a D flip-flop (7); the CLK end of the D trigger (7) is triggered by a rising edge, and when the input signal of the R end of the D trigger (7) is 0, the Q end of the D trigger (7) outputs 0; the input end of the inverter INV1 is the input port S, the output end of the inverter INV1 is connected with one input end of the NOR gate NOR1, the other input end of the NOR gate NOR1 is the input port R, the output end of the NOR gate NOR1 is connected with one input end of the NOR gate NOR2, the other input end of the NOR gate NOR2 is connected with the output end of the NOR gate NOR3, the output end of the NOR gate NOR2 is connected with the other input end of the NOR gate NOR3, the output end of the NOR gate NOR3 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3 and one input end of the NAND gate NAND respectively, the output end of the inverter INV5 is connected with the delay unit (8) and the other input end of the NAND gate NAND respectively, the delay unit (8) is connected with the R end of the D trigger (7), the input voltage is connected with the D end of the D trigger (7), the output end of the D trigger (7) is connected with the output end of the inverter INV5, namely the output end of the D trigger (7) is connected with the output end of the inverter INV 3; the NAND output end of the NAND gate is connected with the input end of the inverter INV4, and the output end of the inverter INV4 is the output port HSD_ON.
2. The voltage dropping circuit with the through mode as set forth in claim 1, wherein the acquisition circuit comprises a resistor R1 and a resistor R2, one end of the resistor R1 is connected with the SW point of the voltage dropping circuit, the other end of the resistor R1 is connected with one end of the resistor R2, the other end of the resistor R2 is grounded, and the two ends of the resistor R2 are connected with a capacitor C1 in parallel; one end of a resistor R1 connected with the resistor R2 is connected with the reverse input end of the comparator (3), and one end of the resistor R1 connected with the resistor R2 forms the RAMP signal SW_RAMP.
3. The voltage reduction circuit with through mode according to claim 1 or2, wherein the first comparison circuit comprises a resistor RF1 and a resistor RF2, the output voltage VOUT is connected to one end of the resistor RF1, the other end of the resistor RF1 is connected to one end of the resistor RF2, and the other end of the resistor RF2 is grounded; one end of a resistor RF1 connected with the resistor RF2 is connected with the inverting input end of the error amplifier (2), and one end of the resistor RF1 connected with the resistor RF2 forms the feedback voltage FB; the reference voltage signal VREF is connected with the non-inverting input end of the error amplifier (2), and the output end of the error amplifier (2) is connected with the non-inverting input end of the comparator (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310205442.9A CN116317547B (en) | 2023-03-06 | 2023-03-06 | Step-down circuit with through mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310205442.9A CN116317547B (en) | 2023-03-06 | 2023-03-06 | Step-down circuit with through mode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116317547A CN116317547A (en) | 2023-06-23 |
| CN116317547B true CN116317547B (en) | 2023-11-03 |
Family
ID=86788213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310205442.9A Active CN116317547B (en) | 2023-03-06 | 2023-03-06 | Step-down circuit with through mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116317547B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783586A (en) * | 2009-01-19 | 2010-07-21 | 成都芯源系统有限公司 | Control circuit for constant on-time converting circuit and method thereof |
| CN103023326A (en) * | 2012-12-11 | 2013-04-03 | 矽力杰半导体技术(杭州)有限公司 | Constant time control method, control circuit and switching regulator using same |
| CN103997194A (en) * | 2014-04-21 | 2014-08-20 | 杰华特微电子（杭州）有限公司 | Method for driving switch tube in BUCK circuit |
| CN204046418U (en) * | 2014-07-18 | 2014-12-24 | 北京云迹科技有限公司 | A kind of power supply power consumption control module |
| CN110071630A (en) * | 2019-05-30 | 2019-07-30 | 上海南芯半导体科技有限公司 | A kind of conversion circuit and implementation method of seamless switching decompression and straight-through operating mode |
| US11095221B1 (en) * | 2020-04-16 | 2021-08-17 | Elite Semiconductor Memory Technology Inc. | Constant on-time controller and buck regulator device using the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10644600B2 (en) * | 2018-03-25 | 2020-05-05 | Richtek Technology Corporation | Constant-time buck-boost switching regulator and control circuit and control method thereof |
-
2023
- 2023-03-06 CN CN202310205442.9A patent/CN116317547B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783586A (en) * | 2009-01-19 | 2010-07-21 | 成都芯源系统有限公司 | Control circuit for constant on-time converting circuit and method thereof |
| CN103023326A (en) * | 2012-12-11 | 2013-04-03 | 矽力杰半导体技术(杭州)有限公司 | Constant time control method, control circuit and switching regulator using same |
| CN103997194A (en) * | 2014-04-21 | 2014-08-20 | 杰华特微电子（杭州）有限公司 | Method for driving switch tube in BUCK circuit |
| CN204046418U (en) * | 2014-07-18 | 2014-12-24 | 北京云迹科技有限公司 | A kind of power supply power consumption control module |
| CN110071630A (en) * | 2019-05-30 | 2019-07-30 | 上海南芯半导体科技有限公司 | A kind of conversion circuit and implementation method of seamless switching decompression and straight-through operating mode |
| US11095221B1 (en) * | 2020-04-16 | 2021-08-17 | Elite Semiconductor Memory Technology Inc. | Constant on-time controller and buck regulator device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116317547A (en) | 2023-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7411316B2 (en) | Dual-input power converter and control methods thereof | |
| US7714546B2 (en) | Step-up regulator with multiple power sources for the controller | |
| US5568044A (en) | Voltage regulator that operates in either PWM or PFM mode | |
| US8222879B2 (en) | Method and apparatus for synchronous buck with active negative current modulation | |
| US20110101946A1 (en) | Voltage converters | |
| US7145316B1 (en) | Control circuit for monitoring and maintaining a bootstrap voltage in an N-channel buck regulator | |
| US9831780B2 (en) | Buck-boost converter and method for controlling buck-boost converter | |
| US7453287B2 (en) | Switching power-supply circuit and semiconductor integrated circuit | |
| US6130526A (en) | Voltage regulator with wide control bandwidth | |
| US8836294B2 (en) | Switching regulator and control circuit and method therefor | |
| US20110241642A1 (en) | Voltage converter | |
| CN108512538B (en) | Power converter and control circuit and control method thereof | |
| US10594218B1 (en) | Hysteresis timing scheme for mode transition in a buck boost converter | |
| KR20080075496A (en) | Switching regulator duty cycle control in a fixed frequency operation | |
| US20120043951A1 (en) | Switching Regulator and Constant On-time Module | |
| KR101919625B1 (en) | Current controlling mode DC-DC Converter | |
| JP4498851B2 (en) | Power supply | |
| JP2006014559A (en) | Dc/dc converter | |
| CN115498861A (en) | Power supply control circuit based on peak-valley current mode | |
| CN116317547B (en) | Step-down circuit with through mode | |
| JP2010158116A (en) | Dc-dc converter | |
| JP5199019B2 (en) | Buck-boost DC-DC converter | |
| CN110391735B (en) | PWM mode boost switching regulator with programmable pulse hopping mode | |
| JPH07222439A (en) | Dc-dc converter | |
| CN110098736B (en) | Self-adaptive wide-range input constant current output circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |