CN116317517A

CN116317517A - Soft start circuit, switching power supply, chip and electronic equipment

Info

Publication number: CN116317517A
Application number: CN202310118505.7A
Authority: CN
Inventors: 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2023-02-03
Filing date: 2023-02-03
Publication date: 2023-06-23

Abstract

The application relates to the technical field of circuits and discloses a soft start circuit, which comprises: the device comprises a first capacitor, a second capacitor, a first comparison circuit, a second comparison circuit and a charge-discharge circuit. The first comparison circuit is used for comparing the voltage value of the second capacitor with a preset reference voltage, and outputting a first signal according to a first comparison result. The second comparison circuit is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result. The charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage. In this way, the first capacitor and the second capacitor are repeatedly charged and discharged according to the first signal and the second signal, so that the voltage of the second capacitor can slowly reach the specified voltage value, and the surge current can be reduced. The application also discloses a switching power supply, a chip and electronic equipment.

Description

Soft start circuit, switching power supply, chip and electronic equipment

Technical Field

The present application relates to the field of circuit technology, for example, to a soft start circuit, a switching power supply, a chip, and an electronic device.

Background

At present, in the starting process of the switching power supply, a large surge current may exist to damage a chip. Fig. 1 is a schematic diagram of a DC-DC converter controlled by voltage PWM (Pulse Width Modulation, pulse width modulation technique). As shown in fig. 1, the voltage type PWM controlled DC-DC converter includes: eighth MOS transistor 17, ninth MOS transistor 18, third capacitor 19, inductor 20, third comparator 21, error amplifier 22, first resistor 23, second resistor 24, third resistor 25, fourth resistor 26, and driving circuit 27. The drain electrode of the eighth MOS tube 17 is used for receiving the input Vin; the grid electrode of the eighth MOS tube 17 is connected with the grid electrode of the ninth MOS tube 18 and the driving circuit; the drain electrode of the ninth MOS tube 18 is connected with the source electrode of the eighth MOS tube 17 and one end of the inductor 20, and the source electrode of the ninth MOS tube 18 is grounded. The other end of the inductor 20 is connected to one end of the third resistor 25, and the other end of the third resistor 25 is connected to one end of the third capacitor 19, one end of the first resistor 23 and the output port Vout. The other end of the third capacitor 19 is connected to one end of the fourth resistor 26, and the other end of the fourth resistor 26 is grounded. The other end of the first resistor 23 is connected with one end of the second resistor 24 and the first input port of the error amplifier 22; the other end of the second resistor 24 is grounded. A second input port of error amplifier 22 receives the system reference voltage. The output port of the error amplifier 22 is connected to the first input port of the third comparator 21, and the second input port of the third comparator 21 is used for receiving a preset sawtooth wave; the output port of the third comparator 21 is connected to a drive circuit 27. Wherein the voltage of the first input port of the error amplifier is taken as the feedback voltage Vfb. After the output voltage of the power supply is sampled, the difference between the feedback voltage Vfb and the system reference voltage Vref_x is amplified through an error amplifier, the amplified difference is compared with a sawtooth wave signal, and a square wave signal with fixed frequency and adjustable duty ratio is output for controlling the working states of an eighth MOS tube and a ninth MOS tube of the power switch, so that the output voltage of the switching power supply is adjusted. In the system start-up phase, the output of the power supply is small, and the system reference voltage can reach the designated voltage value rapidly. At this time, the error amplifier will output a very large voltage value, which causes the power switch to operate in the maximum duty cycle state, thereby generating an inrush current. Since the surge current is liable to damage the chip, how to reduce the surge current is needed to be solved.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. The summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

Embodiments of the present disclosure provide a soft start circuit, a switching power supply, a chip, and an electronic device to enable reduction of an inrush current.

In some embodiments, the soft start circuit comprises: one end of the first capacitor is connected with the second comparison circuit and the charge-discharge circuit, and the other end of the first capacitor is grounded; one end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded; the first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result; the second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result; the charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage; the voltage of the second capacitor is the system reference voltage.

In some embodiments, the first comparison circuit comprises: a first comparator and a first inverter; the first input end of the first comparator is used for receiving a preset reference voltage, and the second input end of the first comparator is connected with the second capacitor; the output end of the first comparator is connected with the input end of the first inverter; the output end of the first inverter is connected with the charge-discharge circuit.

In some embodiments, the second comparison circuit comprises: a second comparator and a second inverter; the first input end of the second comparator is used for receiving a preset reference voltage; the second input end of the second comparator is connected with the first capacitor and the charge-discharge circuit; the output end of the second comparator is connected with the charge-discharge circuit and the input end of the second inverter, and the output end of the second inverter is connected with the charge-discharge circuit.

In some embodiments, the charge-discharge circuit includes: the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor; the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the first comparison circuit; the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube and the power supply; the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube, the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube; the source electrode of the fifth MOS tube is connected with the source electrode of the sixth MOS tube, the source electrode of the seventh MOS tube and the ground; the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube, the drain electrode of the seventh MOS tube, the first capacitor and the second comparison circuit; the grid electrode of the seventh MOS tube is connected with the second comparison circuit; the source electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube; and the grid electrode of the fourth MOS tube is connected with the second comparison circuit, and the source electrode of the fourth MOS tube is connected with the first comparison circuit and the second capacitor.

In some embodiments, the first capacitor is in a charged state with the first signal low and the second signal low.

In some embodiments, the first capacitor is in a discharge state and the second capacitor is in a charge state with the first signal being low and the second signal being high.

In some embodiments, the first capacitor and the second capacitor are stopped from charging and discharging when the first signal is high.

In some embodiments, the switching power supply includes the soft start circuit described above.

In some embodiments, the chip includes the switching power supply described above.

In some embodiments, the electronic device comprises a chip as described above.

The soft start circuit, the switching power supply, the chip and the electronic equipment provided by the embodiment of the disclosure can realize the following technical effects: one end of the first capacitor is connected with the second comparison circuit and the charge-discharge circuit, and the other end of the first capacitor is grounded. One end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded. The first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result. The second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result. The charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage. Therefore, the voltage of the second capacitor is used as the system reference voltage, and the first capacitor and the second capacitor are repeatedly charged and discharged according to the first signal and the second signal, so that the voltage of the second capacitor can slowly reach a specified voltage value, surge current can be reduced, and damage of the surge current to the chip is reduced.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

fig. 1 is a schematic diagram of a DC-DC converter of a voltage type PWM control according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a soft start circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a first comparison circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a second comparison circuit provided in an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a charge-discharge circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another soft start circuit provided by an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of the voltage of a second capacitor and the reference voltage over time according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a change of an output voltage of a switching power supply system with time according to an embodiment of the disclosure.

Reference numerals:

1: a first capacitor; 2: a second capacitor; 3: a first comparison circuit; 4: a second comparison circuit; 5: a charge-discharge circuit; 6: a first comparator; 7: a first inverter; 8: a second comparator; 9: a second inverter; 10: a first MOS tube; 11: a second MOS tube; 12: a third MOS tube; 13: a fourth MOS transistor; 14: a fifth MOS transistor; 15: a sixth MOS transistor; 16: a seventh MOS transistor; 17: an eighth MOS transistor; 18: a ninth MOS transistor; 19: a third capacitor; 20: an inductance; 21: a third comparator; 22: an error amplifier; 23: a first resistor; 24: a second resistor; 25: a third resistor; 26: a fourth resistor; 27: and a driving circuit.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are used primarily to better describe embodiments of the present disclosure and embodiments thereof and are not intended to limit the indicated device, element, or component to a particular orientation or to be constructed and operated in a particular orientation. Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the embodiments of the present disclosure will be understood by those of ordinary skill in the art in view of the specific circumstances.

In addition, the terms "disposed," "connected," "secured" and "affixed" are to be construed broadly. For example, "connected" may be in a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

As shown in connection with fig. 2, an embodiment of the present disclosure provides a soft start circuit, including: a first capacitor 1, a second capacitor 2, a first comparison circuit 3, a second comparison circuit 4 and a charge-discharge circuit 5. One end of the first capacitor is connected with the second comparison circuit and the charge-discharge circuit, and the other end of the first capacitor is grounded; one end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded; the first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result; the second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result; the charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage; the voltage of the second capacitor is the system reference voltage. The first comparison result is the voltage value of the second capacitor and the voltage value of the preset reference voltage. For example: the voltage value of the second capacitor is larger than a preset reference voltage. The second comparison result is the voltage value of the first capacitor and the voltage value of the preset reference voltage. For example: the voltage value of the first capacitor is smaller than a preset reference voltage.

By adopting the soft start circuit provided by the embodiment of the disclosure, one end of the first capacitor is connected with the second comparison circuit and the charge-discharge circuit, and the other end of the first capacitor is grounded. One end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded. The first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result. The second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result. The charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage. Therefore, the voltage of the second capacitor is used as the system reference voltage, and the first capacitor and the second capacitor are repeatedly charged and discharged according to the first signal and the second signal, so that the voltage of the second capacitor can slowly reach a specified voltage value, surge current can be reduced, and damage of the surge current to the chip is reduced.

In some embodiments, the voltage of the second capacitor is an output signal of the soft start circuit for use as a system reference voltage in a switching power supply system.

As shown in connection with fig. 3, optionally, the first comparison circuit comprises: a first comparator 6 and a first inverter 7; the first input end of the first comparator 6 is used for receiving a preset reference voltage, and the second input end of the first comparator 6 is connected with the second capacitor and the charge-discharge circuit; the output end of the first comparator 6 is connected with the input end of the first inverter 7; the output end of the first inverter 7 is connected with a charge-discharge circuit.

As shown in connection with fig. 4, optionally, the second comparing circuit includes: a second comparator 8 and a second inverter 9; the first input end of the second comparator 8 is used for receiving a preset reference voltage; the second input end of the second comparator 8 is connected with the first capacitor and the charge-discharge circuit; the output end of the second comparator 8 is connected with the charge-discharge circuit and the input end of the second inverter 9, and the output end of the second inverter 9 is connected with the charge-discharge circuit.

As shown in conjunction with fig. 5, the charge-discharge circuit may alternatively include: a first MOS transistor 10, a second MOS transistor 11, a third MOS transistor 12, a fourth MOS transistor 13, a fifth MOS transistor 14, a sixth MOS transistor 15, and a seventh MOS transistor 16; the grid electrode of the first MOS tube 10 is connected with the grid electrode of the second MOS tube 11, the grid electrode of the third MOS tube 12 and the first comparison circuit; the drain electrode of the first MOS tube 10 is connected with the drain electrode of the second MOS tube 11, the drain electrode of the third MOS tube 12 and a power supply; the source electrode of the first MOS tube 10 is connected with the drain electrode of the fifth MOS tube 14, the grid electrode of the fifth MOS tube 14 and the grid electrode of the sixth MOS tube 15; the source electrode of the fifth MOS tube 14 is connected with the source electrode of the sixth MOS tube 15, the source electrode of the seventh MOS tube 16 and the ground; the source electrode of the second MOS tube 11 is connected with the drain electrode of the sixth MOS tube 15, the drain electrode of the seventh MOS tube 16, the first capacitor and the second comparison circuit; the grid electrode of the seventh MOS tube 16 is connected with the second comparison circuit; the source electrode of the third MOS tube 12 is connected with the drain electrode of the fourth MOS tube 13; the grid electrode of the fourth MOS tube 13 is connected with the second comparison circuit, and the source electrode of the fourth MOS tube 13 is connected with the first comparison circuit and the second capacitor.

Optionally, in a case where the first signal is low and the second signal is low, the first capacitor is in a charged state.

Optionally, in a case that the first signal is at a low level and the second signal is at a high level, the first capacitor is in a discharging state, and the second capacitor is in a charging state.

Alternatively, in the case where the first signal is at a high level, the first capacitor and the second capacitor are stopped from being charged and discharged.

Optionally, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the seventh MOS transistor are PMOS transistors. The sixth MOS transistor is an NMOS transistor.

In some embodiments, as shown in fig. 6, the second input end of the first comparator 6 of the first comparison circuit is connected to the non-grounded end of the second capacitor 2 and the source of the fourth MOS transistor 13. The output end of the first inverter 7 of the first comparison circuit is connected with the grid electrode of the first MOS tube 10 of the charge-discharge circuit. The output end of the second comparator 8 of the second comparison circuit is connected with the grid electrode of the fourth MOS tube 13 of the charge-discharge circuit. The second input end of the second comparator 8 of the second comparison circuit is connected with the drain electrode of the seventh MOS tube 16 of the charge-discharge circuit and one end of the first capacitor 1 which is not grounded. The reference voltage is Vref, vramp is the voltage of the first capacitor, and Vref_ss is the voltage of the second capacitor.

In some embodiments, with the soft start circuit of the present application, the preset reference voltage Vref is 1.2V assuming the power supply voltage VDD is 1.8V. In the starting process, the voltage Vramp of the first capacitor and the voltage Vref_ss of the second capacitor are 0, and Vref rapidly reaches 1.2V. At this time, the first comparator outputs a high level, and the first comparator converts to a low level after passing through the first inverter, and the second comparator outputs a high level, and the second comparator converts to a low level after passing through the second inverter. The first MOS tube, the second MOS tube and the third MOS tube are conducted, the fourth MOS tube and the seventh MOS tube are turned off, and the first capacitor starts to charge. When the voltage value of the first capacitor exceeds Vref, the second comparator outputs a low level, and the voltage value is converted into a high level after passing through the second inverter. The fourth MOS tube and the seventh MOS tube are conducted, the first capacitor starts to discharge, and the second capacitor starts to charge. When the voltage on the first capacitor is lower than Vref, the above charging process is repeated. And when the voltage Vref_ss on the second capacitor is higher than Vref, the first comparator outputs a low level and changes into a high level after passing through the first inverter. The first MOS tube, the second MOS tube and the third MOS tube are turned off, and the soft start process is completed. Fig. 7 is a schematic diagram showing the voltage of the second capacitor and the reference voltage with time, as shown in fig. 7, the abscissa is time T, and the ordinate is voltage V. The voltage rising speed of the preset reference voltage is faster than that of the second capacitor. Referring to fig. 8, fig. 8 is a schematic diagram showing the change of the output voltage of the switching power supply system with time, and as shown in fig. 8, the abscissa indicates time T and the ordinate indicates voltage V. Where Vout is the output voltage of the system without the use of a soft start circuit. Vout_ss is the output voltage of the system in the case of using a soft start circuit. The output voltage of a system using a soft start circuit is gentler than that of a system not using a soft start circuit. In this way, by reasonably designing the sizes of the first MOS tube, the second MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube and the turnover threshold value of the second comparator, the first capacitor can be charged by a current I3 with a very small current value and a very small variation range, wherein the current value of the current I3 is equal to the current difference value between the current I1 and the current I2. The current I1 is the current flowing through the second MOS tube, and the current I2 is the current flowing through the sixth MOS tube. Since the current charging the first capacitor is small, the soft start circuit of the present application can use smaller first and second capacitors. Therefore, the volume of the capacitor of the soft start circuit can be reduced while the surge current is reduced, and the size of the soft start circuit is reduced.

The embodiment of the disclosure provides a switching power supply, which comprises the soft start circuit.

By adopting the switching power supply provided by the embodiment of the disclosure, the soft start circuit is arranged in the switching power supply, one end of the soft start circuit, which passes through the first capacitor, is connected with the second comparison circuit and the charge-discharge circuit, and the other end of the soft start circuit is grounded. One end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded. The first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result. The second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result. The charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage. Therefore, the voltage of the second capacitor is used as the system reference voltage of the switching power supply, and the first capacitor and the second capacitor are repeatedly charged and discharged according to the first signal and the second signal, so that the voltage of the second capacitor can slowly reach a specified voltage value, surge current can be reduced, damage of the surge current to the switching power supply is further reduced, and damage of the surge current to the chip is further reduced.

The embodiment of the disclosure provides a chip, which comprises the switching power supply.

By adopting the chip provided by the embodiment of the disclosure, the switch power supply is arranged in the chip, the soft start circuit is arranged in the switch power supply, one end of the soft start circuit through the first capacitor is connected with the second comparison circuit and the charge-discharge circuit, and the other end of the soft start circuit is grounded. One end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded. The first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result. The second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result. The charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage. Therefore, the voltage of the second capacitor is used as the system reference voltage, and the first capacitor and the second capacitor are repeatedly charged and discharged according to the first signal and the second signal, so that the voltage of the second capacitor can slowly reach a specified voltage value, surge current can be reduced, damage of the surge current to the switching power supply is further reduced, and damage of the surge current to the chip is further reduced.

The embodiment of the disclosure provides an electronic device, which comprises the chip.

By adopting the electronic equipment provided by the embodiment of the disclosure, the chip is arranged in the electronic equipment, the switch power supply is arranged in the chip, the soft start circuit is arranged in the switch power supply, one end of the soft start circuit, which is connected with the second comparison circuit and the charge-discharge circuit through the first capacitor, is grounded at the other end. One end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded. The first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result. The second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result. The charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage. In this way, the voltage of the second capacitor is used as the system reference voltage, and the first capacitor and the second capacitor are repeatedly charged and discharged according to the first signal and the second signal, so that the voltage of the second capacitor can slowly reach the specified voltage value, the surge current can be reduced, the damage of the surge current to the switching power supply is further reduced, the damage of the surge current to the chip is further reduced, and the damage of the surge current to the electronic equipment comprising the chip is reduced.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may include structural and other modifications. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A soft start circuit, comprising:

one end of the first capacitor is connected with the second comparison circuit and the charge-discharge circuit, and the other end of the first capacitor is grounded;

one end of the second capacitor is connected with the first comparison circuit and the charge-discharge circuit, and the other end of the second capacitor is grounded;

the first comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the second capacitor with a preset reference voltage and outputting a first signal according to a first comparison result;

the second comparison circuit is connected with the charge-discharge circuit and is used for comparing the voltage value of the first capacitor with a preset reference voltage and outputting a second signal according to a second comparison result;

the charge-discharge circuit charges and discharges the first capacitor and the second capacitor according to the first signal and the second signal until the voltage of the second capacitor rises to a set voltage; the voltage of the second capacitor is the system reference voltage.

2. The soft start circuit of claim 1, wherein the first comparison circuit comprises: a first comparator and a first inverter; the first input end of the first comparator is used for receiving a preset reference voltage, and the second input end of the first comparator is connected with the second capacitor; the output end of the first comparator is connected with the input end of the first inverter; the output end of the first inverter is connected with the charge-discharge circuit.

3. The soft start circuit of claim 1, wherein the second comparison circuit comprises: a second comparator and a second inverter; the first input end of the second comparator is used for receiving a preset reference voltage; the second input end of the second comparator is connected with the first capacitor and the charge-discharge circuit; the output end of the second comparator is connected with the charge-discharge circuit and the input end of the second inverter, and the output end of the second inverter is connected with the charge-discharge circuit.

4. The soft start circuit of claim 1, wherein the charge-discharge circuit comprises: the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor; the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the first comparison circuit; the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube and the power supply; the source electrode of the first MOS tube is connected with the drain electrode of the fifth MOS tube, the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube; the source electrode of the fifth MOS tube is connected with the source electrode of the sixth MOS tube, the source electrode of the seventh MOS tube and the ground; the source electrode of the second MOS tube is connected with the drain electrode of the sixth MOS tube, the drain electrode of the seventh MOS tube, the first capacitor and the second comparison circuit; the grid electrode of the seventh MOS tube is connected with the second comparison circuit; the source electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube; and the grid electrode of the fourth MOS tube is connected with the second comparison circuit, and the source electrode of the fourth MOS tube is connected with the first comparison circuit and the second capacitor.

5. The soft start circuit of any one of claims 1 to 4, wherein the first capacitor is in a charged state when the first signal is low and the second signal is low.

6. The soft start circuit of any one of claims 1 to 4, wherein the first capacitor is in a discharge state and the second capacitor is in a charge state when the first signal is low and the second signal is high.

7. The soft start circuit according to any one of claims 1 to 4, wherein the first capacitor and the second capacitor are stopped from being charged and discharged when the first signal is at a high level.

8. A switching power supply comprising a soft start circuit as claimed in any one of claims 1 to 7.

9. A chip comprising the switching power supply of claim 8.

10. An electronic device comprising the chip of claim 9.