CN116314332A - Super-junction trench gate MOSFET layout structure and preparation method thereof - Google Patents

Super-junction trench gate MOSFET layout structure and preparation method thereof Download PDF

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Publication number
CN116314332A
CN116314332A CN202310203962.6A CN202310203962A CN116314332A CN 116314332 A CN116314332 A CN 116314332A CN 202310203962 A CN202310203962 A CN 202310203962A CN 116314332 A CN116314332 A CN 116314332A
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gate
region
conductive
conductive plug
auxiliary
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许昭昭
田甜
朱丽霞
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H01L29/42356—Disposition, e.g. buried gate electrode
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Abstract

The invention provides a super-junction trench gate MOSFET layout structure and a preparation method thereof, wherein the layout structure comprises the following components: the semiconductor device comprises a substrate, a gate dielectric layer, a main gate, a first auxiliary gate, a second auxiliary gate which is annular, a dummy gate which is annular, a body region, a source doping region, an interlayer dielectric layer, a first conductive plug, a second conductive plug, a third conductive plug, a fourth conductive plug, a deep injection region, a first conductive layer and a second conductive layer. The deep injection region is designed at the bottoms of the first to fourth conductive plugs, so that the deep injection region can be injected by using the photomask for preparing all the contact holes, the photomask is saved, the preparation process is simplified, and the manufacturing cost is reduced. Furthermore, the dummy gate and the fourth conductive plug in the peripheral terminal area, and the second auxiliary gate and the third conductive plug in the gate terminal lead-out area are all arranged to be of continuous annular structures, so that the problem that the charge balance of the device is deviated is avoided, and the breakdown voltage of the device is improved.

Description

Super-junction trench gate MOSFET layout structure and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a super-junction trench gate MOSFET layout structure and a preparation method thereof.
Background
Trench gate MOSFET devices are widely used in power conversion circuits, and are commonly used in power switching devices. The on-resistance (Rsp) and Breakdown Voltage (BV) of the trench gate are one of important parameter indexes, and obtaining higher breakdown voltage and lower on-resistance can improve the competitiveness of the product. In order to improve the on-resistance of a trench gate MOSFET at medium-high voltage (50-200V), a super junction-trench gate concept realized by implantation is proposed.
Taking an N-channel trench gate as an example, to improve the characteristics of a superjunction-trench gate device, the bottom end of a P-deep implant (PPL) region used to assist in N-drift region depletion would be as close as possible to the highly doped substrate to make the depletable N-type drift region long.
However, in the current ion implantation step of the deep implantation region, a layer is additionally introduced to be used as PPL implantation, and it is also understood that the current ion implantation of the deep implantation region requires a separate mask layer and a mask to be used as the implantation of the deep implantation region, but the implantation of the additional layer increases the manufacturing cost of the process, so that the advantage of superjunction is reduced. In addition, the existing super junction-trench gate device also has the problems of insufficient Breakdown Voltage (BV), large occupied chip area and the like.
Disclosure of Invention
The invention provides a super-junction trench gate MOSFET layout structure and a preparation method thereof, which can solve at least one of the problems of higher manufacturing cost, complex manufacturing process flow, insufficient Breakdown Voltage (BV), larger occupied chip area and the like of a super-junction trench gate device.
In one aspect, an embodiment of the present application provides a super-junction trench gate MOSFET layout structure, including:
a substrate, the front side of the substrate being formed with an epitaxial layer, wherein the epitaxial layer comprises: a source terminal extraction region, a gate terminal extraction region disposed around the source terminal extraction region, and a peripheral terminal region disposed around the gate terminal extraction region;
a plurality of trenches in the epitaxial layer;
the gate dielectric layer covers the bottom wall and the side wall of the groove;
the main grid electrodes cover the grid dielectric layer of the source end leading-out area and fill the corresponding grooves, the main grid electrodes are arranged at intervals along a first direction and are parallel to a second direction, and the first direction and the second direction are mutually perpendicular;
the first auxiliary grid electrode covers part of the grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the first auxiliary grid electrode is positioned at one side of the source end leading-out area along the first direction;
The second auxiliary grid electrode covers the residual grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the second auxiliary grid electrode is arranged at intervals around the grid end leading-out area, wherein the main grid electrode, the first auxiliary grid electrode and the second auxiliary grid electrode are interconnected through the groove;
the dummy gates cover the gate dielectric layer of the peripheral terminal area and fill the corresponding grooves, and the dummy gates are arranged at intervals around the center of the substrate;
the body region is positioned in the epitaxial layer between the grooves and is close to the surface of the epitaxial layer;
the source doping region is positioned on the surface of the body region at the side of the main grid electrode;
the interlayer dielectric layer covers the epitaxial layer, the main grid electrode, the first auxiliary grid electrode, the second auxiliary grid electrode and the pseudo grid electrode;
a plurality of first conductive plugs located in body regions between the main gates;
a plurality of second conductive plugs located in the first subsidiary gates and in body regions between the first subsidiary gates;
a plurality of annular third conductive plugs, wherein the third conductive plugs are positioned in the second auxiliary grid electrode;
A plurality of annular fourth conductive plugs, wherein the fourth conductive plugs are respectively positioned in the body region of each pseudo gate side;
the deep injection region is positioned in the epitaxial layers at the bottoms of the first conductive plug, the second conductive plug and the fourth conductive plug;
a first conductive layer covering a portion of the first conductive plug of the source terminal extraction region to extract the source doped region;
and the second conductive layer covers part of the second conductive plug and part of the third conductive plug of the gate end extraction region so as to extract the main gate of the source end extraction region.
Optionally, in the super-junction trench gate MOSFET layout structure, an outer edge of the second conductive layer is located at a middle position of a region between the third conductive plug in the second auxiliary gate and the fourth conductive plug in the innermost side of the peripheral terminal region.
Optionally, in the super-junction trench gate MOSFET layout structure, the first auxiliary gate includes: the device comprises two first trench gates which are parallel to a first direction and are distributed along a second direction, a plurality of second trench gates which are parallel to the second direction and are distributed along the first direction at intervals, and a plurality of third trench gates which are parallel to the second direction and are distributed along the first direction at intervals, wherein the two first trench gates are respectively positioned at two ends of the plurality of second trench gates to form a closed structure, and the third trench gates are positioned at two sides of the closed structure along the second direction so that the closed structure is connected with the second auxiliary gate.
Optionally, in the super-junction trench gate MOSFET layout structure, the closed structure and second conductive plugs in the closed structure form a charge balance structure, where two second conductive plugs on the outermost side parallel to the second direction in the closed structure are connected with second conductive plugs parallel to the first direction in the first trench gate; the second conductive plug parallel to the second direction inside the closed structure is not connected with the second conductive plug parallel to the first direction in the first trench gate.
Optionally, in the super-junction trench gate MOSFET layout structure, along the first direction, an inner edge of the second conductive layer is located at a middle position of a region between two second auxiliary gates close to the source end extraction region; in a second direction, a portion of the inside edge of the second conductive layer is located over the second conductive plug in the second trench gate, and the portion of the inside edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.
Optionally, in the super-junction trench gate MOSFET layout structure, a lateral dimension of the second trench gate closest to the source terminal extraction region in width is greater than or equal to a lateral dimension of the remaining second trench gate in width.
Optionally, in the super-junction trench gate MOSFET layout structure, a lateral dimension of the second trench gate closest to the source terminal extraction region in width is greater than a lateral dimension of the second conductive plug in width.
Optionally, in the super-junction trench gate MOSFET layout structure, the conductivity types of the doped ions in the substrate, the epitaxial layer, and the source doped region are the first conductivity type; the conductivity type of the ions doped in the deep implant region and the body region is a second conductivity type.
Optionally, in the super-junction trench gate MOSFET layout structure, the super-junction trench gate MOSFET layout structure further includes: and a heavily doped region located in the body region between the first conductive plug and the deep implant region, in the body region between the second conductive plug and the deep implant region, between the third conductive plug and the second auxiliary gate, and in the body region between the fourth conductive plug and the deep implant region.
On the other hand, the embodiment of the application also provides a preparation method of the super-junction trench gate MOSFET layout structure, which comprises the following steps:
providing a substrate, wherein an epitaxial layer is formed on the front surface of the substrate, and the epitaxial layer comprises: a source terminal extraction region, a gate terminal extraction region disposed around the source terminal extraction region, and a peripheral terminal region disposed around the gate terminal extraction region;
Forming a plurality of trenches, wherein the trenches are positioned in the epitaxial layer;
forming a gate dielectric layer, wherein the gate dielectric layer covers the bottom wall and the side wall of the groove;
forming a plurality of main grids, a first auxiliary grid, a plurality of annular second auxiliary grids and a plurality of annular dummy grids, wherein the main grids cover a grid dielectric layer of a source end leading-out area and fill corresponding grooves, the main grids are arranged at intervals along a first direction and are parallel to a second direction, and the first direction and the second direction are mutually perpendicular; the first auxiliary grid electrode covers part of the grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the first auxiliary grid electrode is positioned at one side of the source end leading-out area along the first direction; the second auxiliary grid electrode covers the residual grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the second auxiliary grid electrode is arranged at intervals around the grid end leading-out area, wherein the main grid electrode, the first auxiliary grid electrode and the second auxiliary grid electrode are interconnected through the groove; the dummy gate covers the gate dielectric layer of the peripheral terminal area and fills the corresponding groove, and the dummy gate is arranged around the center of the substrate at intervals;
Performing a global ion implantation process to form a body region, wherein the body region is positioned in the epitaxial layer between the trenches and is close to the surface of the epitaxial layer;
performing a selective ion implantation process to form a source doped region, wherein the source doped region is positioned on the surface of the body region at the side of the main grid electrode;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the epitaxial layer, the main grid electrode, the first auxiliary grid electrode, the second auxiliary grid electrode and the pseudo grid electrode;
forming a first contact hole, a second contact hole, a third contact hole and a fourth contact hole which are annular, wherein the first contact hole penetrates through the interlayer dielectric layer and is positioned in a body region between the main grid electrodes, the second contact hole penetrates through the interlayer dielectric layer and is positioned in the first auxiliary grid electrodes, the third contact hole penetrates through the interlayer dielectric layer and is positioned in the second auxiliary grid electrodes, and the fourth contact hole penetrates through the interlayer dielectric layer and is positioned in the body region between the adjacent pseudo grid electrodes;
forming a deep injection region, wherein the deep injection region is positioned in the epitaxial layer at the bottoms of the first contact hole, the second contact hole and the fourth contact hole;
forming a first conductive plug, a second conductive plug, a third conductive plug and a plurality of annular fourth conductive plugs, wherein the first conductive plug fills the first contact hole, the second conductive plug fills the second contact hole, the third conductive plug fills the third contact hole, and the fourth conductive plug fills the fourth contact hole;
And forming a first conductive layer and a second conductive layer, wherein the first conductive layer covers part of the first conductive plug of the source end extraction region to extract the source doping region, and the second conductive layer covers part of the second conductive plug and part of the third conductive plug of the gate end extraction region to extract the main gate of the source end extraction region.
Optionally, in the method for manufacturing a super-junction trench gate MOSFET layout structure, an outer edge of the second conductive layer is formed at a middle position of a region between a third conductive plug in the second auxiliary gate at an outermost side of the gate terminal extraction region and the fourth conductive plug at an innermost side of the peripheral terminal region.
Optionally, in the method for manufacturing a super-junction trench gate MOSFET layout structure, the first auxiliary gate includes: the device comprises two first trench gates which are parallel to a first direction and are distributed along a second direction, a plurality of second trench gates which are parallel to the second direction and are distributed along the first direction at intervals, and a plurality of third trench gates which are parallel to the second direction and are distributed along the first direction at intervals, wherein the two first trench gates are respectively positioned at two ends of the plurality of second trench gates to form a closed structure, and the third trench gates are positioned at two sides of the closed structure along the second direction so that the closed structure is connected with the second auxiliary gate.
Optionally, in the method for manufacturing the super-junction trench gate MOSFET layout structure, the closed structure and the second conductive plugs in the closed structure form a charge balance structure, where two second conductive plugs on the outermost side parallel to the second direction in the closed structure are connected with the second conductive plugs parallel to the first direction in the first trench gate; the second conductive plug parallel to the second direction inside the closed structure is not connected with the second conductive plug parallel to the first direction in the first trench gate.
Optionally, in the preparation method of the super-junction trench gate MOSFET layout structure, along the first direction, an inner edge of the second conductive layer is located at a middle position of a region between two second auxiliary gates close to the source end extraction region; in a second direction, a portion of the inside edge of the second conductive layer is located over the second conductive plug in the second trench gate, and the portion of the inside edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.
Optionally, in the preparation method of the super-junction trench gate MOSFET layout structure, a lateral dimension of the second trench gate closest to the source terminal extraction region in width is greater than or equal to a lateral dimension of the remaining second trench gate in width.
The technical scheme of the application at least comprises the following advantages:
first, the deep injection region is designed at the bottom of the first conductive plug (the first contact hole), the bottom of the second conductive plug (the second contact hole), the bottom of the third conductive plug (the third contact hole) and the bottom of the fourth conductive plug (the fourth contact hole), so that the deep injection region can be injected by using the photomasks for preparing all the contact holes (the first to fourth contact holes), the photomasks are saved, the preparation process is simplified, and the manufacturing cost is reduced.
Second, through setting the dummy gate in the peripheral terminal area, the fourth conductive plug and the second auxiliary gate and the third conductive plug in the gate terminal lead-out area to be continuous annular structures, the annular dummy gate and the second auxiliary gate do not need to be disconnected, the problem that the charge balance of the device is offset is avoided, and the breakdown voltage of the device is improved.
Third, the second conductive plug parallel to the second direction inside the closed structure is disconnected from the second conductive plug parallel to the first direction in the first trench gate, so that a better charge balance effect can be achieved.
Fourth, the outer side edge of the second conductive layer is placed at the middle position of the area between the third conductive plug in the second auxiliary gate at the outermost side of the gate end leading-out area and the fourth conductive plug at the innermost side of the peripheral terminal area, and the part of the inner side edge of the second conductive layer along the longitudinal direction is placed on the second conductive plug in the second trench gate, namely, the part of the inner side edge of the second conductive layer does not cover the two ends of the second conductive plug in the second trench gate so as to expose the two ends of the second conductive plug in the second trench gate, so that the design window of the second conductive layer and the contact hole process is optimized, and the yield of the process for preparing the super-junction trench gate MOSFET layout structure is improved.
Fifth, the lateral dimension of the second trench gate closest to the source end extraction area is greater than or equal to the lateral dimension of the rest of the second trench gates on the left side of the second trench gate in width, and the lateral dimension of the second trench gate closest to the source end extraction area is greater than the lateral dimension of the second conductive plug in width, so that the second trench gate needs to encase the second contact hole/the second conductive plug/the deep injection area in process, and for small-size devices, the design can be such that the second trench gate closest to the source end extraction area and the adjacent trenches thereof are combined together, design rules between trenches in process are considered, isolation of a deep injection area and a body area below the trenches is realized, and better charge balance requirements are met.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a top view of a semiconductor structure with an epitaxial layer formed in accordance with an embodiment of the present invention;
FIG. 2 is a cross-sectional view of the semiconductor structure shown in FIG. 1 along the NN' direction in accordance with an embodiment of the invention;
fig. 3 is a top view of the semiconductor structure after forming the first through fourth conductive plugs according to the embodiment of the present invention;
FIG. 4 is a partial cross-sectional view of the semiconductor structure shown in FIG. 3 along the direction LL' in accordance with an embodiment of the present invention;
FIG. 5 is a partial cross-sectional view of the semiconductor structure shown in FIG. 3 along the MM' direction in accordance with an embodiment of the present invention;
fig. 6 is a partial top view of a semiconductor structure formed with a first auxiliary gate and a second conductive plug in accordance with an embodiment of the present invention;
FIG. 7 is a top view of the semiconductor structure after forming the first conductive layer and the second conductive layer according to an embodiment of the present invention;
Wherein reference numerals are as follows:
a peripheral terminal region, a B-gate terminal lead-out region and a C-source terminal lead-out region;
101-substrate, 102-epitaxial layer, 103-deep implanted region, 104-gate dielectric layer, 105-main gate, 205-first auxiliary gate, 2051-first trench gate, 2052-second trench gate, 2053-third trench gate, 305-second auxiliary gate, 405-dummy gate, 106-body region, 107-source doped region, 108-heavily doped region, 109-first conductive plug, 209-second conductive plug, 309-third conductive plug, 409-fourth conductive plug, 110-interlayer dielectric layer, 111-first conductive layer, 112-second conductive layer.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The embodiment of the application provides a super-junction trench gate MOSFET layout structure, which comprises: the semiconductor device comprises a substrate 101, an epitaxial layer 102, a plurality of trenches, a gate dielectric layer 104, a plurality of main gates 105, a first auxiliary gate 205, a plurality of second auxiliary gates 305 in a ring shape, a plurality of dummy gates 405 in a ring shape, a body region 106, a source doped region 107, an interlayer dielectric layer 110, a plurality of first conductive plugs 109, a plurality of second conductive plugs 209, a plurality of third conductive plugs 309 in a ring shape, a plurality of fourth conductive plugs 409 in a ring shape, a deep injection region 103, a first conductive layer 111, a second conductive layer 112 and the like.
Referring to fig. 1 and 2, fig. 1 is a top view of a semiconductor structure having an epitaxial layer formed thereon according to an embodiment of the present invention, and fig. 2 is a cross-sectional view of the semiconductor structure shown in fig. 1 along the NN' direction according to an embodiment of the present invention, wherein the epitaxial layer 102 is formed on the front surface of the substrate 101, and the epitaxial layer 102 includes: a source terminal extraction region C, a gate terminal extraction region B disposed around the source terminal extraction region C, and a peripheral terminal region a disposed around the gate terminal extraction region B.
In this embodiment, the material of the substrate 101 is silicon. In other embodiments, the material of the substrate 101 comprises silicon carbide, silicon germanium, a III-V element comprising a multi-semiconductor material, silicon-on-insulator (SOI or germanium-on-insulator (GOI). Wherein the III-V element comprising a multi-semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
Wherein the conductivity type of the doped ions in the substrate 101 is a first conductivity type; the conductivity type of the ions doped in the epitaxial layer 102 is the first conductivity type. In this embodiment, the super junction-trench gate MOSFET with an N-type channel is taken as an example, so in this embodiment, the conductivity type of the doped ions in the substrate 101 is N-type, and the conductivity type of the doped ions in the epitaxial layer 102 is N-type.
Referring to fig. 3 to 5, fig. 3 is a top view of a semiconductor structure after forming first to fourth conductive plugs according to an embodiment of the present invention, fig. 4 is a partial cross-sectional view of the semiconductor structure shown in fig. 3 along the direction LL 'according to an embodiment of the present invention, and fig. 5 is a partial cross-sectional view of the semiconductor structure shown in fig. 3 along the direction MM' according to an embodiment of the present invention. The trenches are located in the epitaxial layer 102, and are used to deposit the gate dielectric layer 104 and all trench gates (the main gate 105, the first auxiliary gate 205, the plurality of second auxiliary gates 305 in a ring shape, and the plurality of dummy gates 405 in a ring shape).
Further, the gate dielectric layer 104 covers the bottom wall and the side wall of the trench, and the gate dielectric layer 104 may be made of silicon oxide. All trench gates (the main gate 105, the first auxiliary gate 205, the plurality of second auxiliary gates 305 in a ring shape and the plurality of dummy gates 405 in a ring shape) are disconnected from the deep implanted regions 103 at the bottom of each by wrapping all trench gates with the gate dielectric layer 104.
As shown in fig. 4, a plurality of the main gates 105 cover the gate dielectric layer 104 of the source-end extraction region C and fill the corresponding trenches, and the main gates 105 are arranged at intervals along a first direction (X direction) and parallel to a second direction (Y direction), where the first direction (X direction) and the second direction (Y direction) are perpendicular to each other.
As shown in fig. 3, the first auxiliary gate 205 covers a portion of the gate dielectric layer 104 of the gate end extraction region B and fills the corresponding trench, the first auxiliary gate 205 is located at one side of the source end extraction region C along the first direction (X direction, transverse direction), and in this embodiment, the first auxiliary gate 205 is located at the left side of the source end extraction region C.
Preferably, referring to fig. 6, fig. 6 is a partial top view of a semiconductor structure formed with a first auxiliary gate and a second conductive plug according to an embodiment of the present invention, where the first auxiliary gate 205 includes: the structure comprises two first trench gates 2051 which are parallel to a first direction (X direction) and are arranged along a second direction (Y direction), a plurality of second trench gates 2052 which are parallel to the second direction and are arranged at intervals along the first direction, and a plurality of third trench gates 2053 which are parallel to the second direction and are arranged at intervals along the first direction, wherein the two first trench gates 2051 are respectively positioned at two ends of the plurality of second trench gates 2052 to form a closed structure, and the third trench gates 2053 are positioned at two sides of the closed structure along the second direction so as to enable the closed structure (a first auxiliary gate 205) to be connected with the second auxiliary gate 305.
Further, the closed structure and the second conductive plugs 209 in the closed structure form a charge balance structure, wherein, in the closed structure, two outermost second conductive plugs parallel to the second direction are connected with the second conductive plugs parallel to the first direction in the first trench gate 2051; as indicated by the dashed line a position, the second conductive plugs 209 within the enclosed structure that are parallel to the second direction are not connected to the second conductive plugs in the first trench gate 2051 that are parallel to the first direction. According to the method and the device, the second conductive plug parallel to the second direction inside the closed structure is disconnected with the second conductive plug parallel to the first direction in the first trench gate, so that a better charge balance effect can be achieved.
Preferably, as indicated by the position of the dashed line b, the lateral dimension in width of the second trench gate 2052 closest to the source terminal extraction region is greater than or equal to the lateral dimension in width of the remaining second trench gate 2052 to the left thereof.
Preferably, as indicated by the position of the virtual line b, the lateral dimension of the second trench gate 2052 closest to the source terminal extraction region is greater than the lateral dimension of the second conductive plug 209 in width, i.e., the width of the second trench gate 2052 is required to be processed to encapsulate the second contact hole/the second conductive plug 209/the deep implant region 103. For small-size devices, the design can combine the second trench gate 2052 closest to the source-end extraction region and the adjacent trench (see the dotted line b in fig. 6 for details), and give consideration to the design rule between trenches in the process, and meanwhile, the isolation between the deep injection region and the body region below the trench is realized, so as to achieve better charge balance requirement.
As shown in fig. 3 and fig. 4, a plurality of second auxiliary gates 305 in a ring shape cover the remaining gate dielectric layer of the gate terminal lead-out area B and fill the corresponding trenches, and the second auxiliary gates 305 are disposed around the gate terminal lead-out area B at intervals, in this embodiment, the plurality of second auxiliary gates 305 are disposed in concentric square rings in the gate terminal lead-out area B. Wherein the main gate 105, the first subsidiary gate 205 and the second subsidiary gate 305 are interconnected by the trench.
As shown in fig. 3 and 4, a plurality of dummy gates 405 in a ring shape cover the gate dielectric layer 104 of the peripheral terminal area a and fill corresponding trenches, and the dummy gates 405 are spaced around the center of the substrate 101.
In this embodiment, the main gate 105, the first auxiliary gate 205, the second auxiliary gate 305 and the dummy gate 405 may be made of polysilicon. In this embodiment, the P-type heavily doped implant is also implanted into the doped polysilicon in part of the trench gate, but the subsequently implanted heavily doped region 107 does not invert the N-type heavily doped polysilicon trench gate because the concentration of the N-type heavily doped polysilicon is more concentrated.
In the present application, by setting the dummy gate 405 and the fourth conductive plug 409 in the peripheral terminal area a and the second auxiliary gate 305 and the third conductive plug 309 in the gate terminal lead-out area B to continuous annular structures, the annular dummy gate 405 and the second auxiliary gate 305 do not need to be disconnected, so that the problem that the charge balance of the device is offset is avoided, and the breakdown voltage of the device is improved.
Further, the body region 106 is located in the epitaxial layer 102 between the trenches and near the surface of the epitaxial layer 102, and the conductivity type of the ions doped in the body region 106 is the second conductivity type, and in this embodiment, the conductivity type of the ions doped in the body region 106 is the P-type.
Preferably, the source doped region 108 is located on the surface of the body region 106 on the side of the main gate 105. The conductivity type of the ions doped in the source doped region 108 is the same as the conductivity type of the ions doped in the epitaxial layer. In this embodiment, the conductivity type of the doped ions in the source doped region 108 is N-type.
Further, the interlayer dielectric layer 110 covers the epitaxial layer 102, the main gate 105, the first auxiliary gate 205, the second auxiliary gate 305, and the dummy gate 405.
Preferably, the super-junction trench gate MOSFET layout structure may further include: a first contact hole, a second contact hole, a third contact hole and a fourth contact hole, wherein the first contact hole penetrates through the interlayer dielectric layer 110 and is located in the body region 106 between the main gates 105, the second contact hole penetrates through the interlayer dielectric layer 110 and is located in the body region 106 between the first auxiliary gates 205 or 205, the third contact hole penetrates through the interlayer dielectric layer 110 and is located in the second auxiliary gate 305, and the fourth contact hole penetrates through the interlayer dielectric layer 110 and is located in the body region between the adjacent dummy gates 405 (it can also be understood that each fourth contact hole is located in the body region 106 on the side of each dummy gate 405). The first contact hole, the second contact hole, the third contact hole in a ring shape, and the fourth contact hole in a ring shape may be simultaneously formed for subsequent formation of the first to fourth conductive plugs 109.
Preferably, as shown in fig. 4 and 5, after forming the first contact hole, the second contact hole, the third contact hole having a ring shape, and the fourth contact hole having a ring shape, an ion implantation process is performed to obtain the deep implantation region 103 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the third contact hole having a ring shape, and the bottom of the fourth contact hole having a ring shape. As shown in fig. 4, in the source extraction region C, the deep implantation region 103 is located at the bottom of the source doping region 108. In the gate end extraction region B, the deep injection region 103 is located at the bottom of the second auxiliary gate 305, the depth of the second auxiliary gate 305 is greater than the injection depth of the body region 106, and the body region 106 is isolated into an independent floating body block by the second auxiliary gate 305+ deep injection region 103, so that the voltage resistance of the gate end extraction region B is improved, and the electrical performance of the device is improved.
The conductivity type of the ions doped in the deep implantation region 103 is the same as the conductivity type of the ions doped in the body region 106, and the conductivity type of the ions doped in the deep implantation region 103 is the second conductivity type, and in this embodiment, the conductivity type of the ions doped in the deep implantation region 103 is the P-type.
In the present application, by designing the deep injection region 103 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the third contact hole, and the bottom of the fourth contact hole, the injection of the deep injection region 103 can be completed by using the masks for preparing all the contact holes (the first to fourth contact holes), thereby saving masks, simplifying the preparation process, and reducing the manufacturing cost.
Preferably, as shown in fig. 4 and 5, the super-junction trench gate MOSFET layout structure may further include: a heavily doped region 107, where the heavily doped region 107 is located in the body region 106 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the third contact hole in a ring shape, and the bottom of the fourth contact hole in a ring shape. That is, the heavily doped region 107 is located in the body region 106 between the first conductive plug 109 and the deep implanted region 103, in the body region between the second conductive plug 209 and the deep implanted region 103, between the third conductive plug 309 and the second auxiliary gate 305, and in the body region between the fourth conductive plug 409 and the deep implanted region 103.
In this embodiment, subsequently, the heavily doped region 107 and the source doped region 108 in the source extraction region C are shorted and extracted through the first conductive plug 109/the first conductive layer 111.
Further, as shown in fig. 3, the first conductive plugs 109 are located in the body region 106 between the main gates 105; the second conductive plugs 209 are located in the first auxiliary gates 205 and in the body region 106 between the first auxiliary gates 205; a plurality of third conductive plugs 309 in a ring shape are located in the second auxiliary gate 305 in a ring shape; a plurality of fourth conductive plugs 409 having a ring shape are respectively located in the body region 106 on the side of each of the dummy gates 405.
Preferably, referring to fig. 7, fig. 7 is a top view of the semiconductor structure after forming the first conductive layer and the second conductive layer according to the embodiment of the present invention, the first conductive layer 111 covers a portion of the first conductive plug 109 of the source terminal extraction region C to extract the source doped region 108; the second conductive layer 112 covers a portion of the second conductive plugs 209 and a portion of the third conductive plugs 309 of the gate terminal extraction region B to extract the main gate 105 of the source terminal extraction region C.
Preferably, as shown in fig. 4 and 7, the outer edge of the second conductive layer 112 is located at an intermediate position of the region between the third conductive plug 309 in the second auxiliary gate 305 at the outermost side of the gate terminal extraction region B and the fourth conductive plug 409 at the innermost side of the peripheral terminal region C. Further, as shown in fig. 4 and 7, along the first direction (lateral direction, X direction), the inner edge of the second conductive layer 112 is located at an intermediate position of the region between the two second auxiliary gates 305 near the source-end extraction region B; in a second direction (longitudinal, Y-direction), a portion of the inner edge of the second conductive layer 112 is located on the second conductive plug 209 in the second trench gate 2052, and a portion of the inner edge of the second conductive layer 112 does not cover both ends of the second conductive plug 209 in the second trench gate 2052, i.e., a portion of the inner edge of the second conductive layer 112 is retracted to the inside of the charge balance structure; the remaining inner edge of the second conductive layer 112 covers the innermost third conductive plug 309, i.e. the remaining inner edge of the second conductive layer 112 is located at an intermediate position of the region between the innermost third conductive plug 309 and the outermost second conductive plug 209 in the second sub-gate 305.
In this application, the outer edge of the second conductive layer 112 is placed at the middle position of the region between the third conductive plug 309 in the second auxiliary gate 305 and the innermost side of the peripheral terminal region a in the gate end extraction region B, and the inner edge of a part of the second conductive layer 112 along the longitudinal direction is placed on the second conductive plug 209 in the second trench gate 2052, that is, the inner edge of a part of the second conductive layer 112 does not cover the two ends of the second conductive plug 209 in the second trench gate 2052, so that the two ends of the second conductive plug 209 in the second trench gate 2052 are specifically exposed, which optimizes the design window of the second conductive layer 112/first conductive layer 111 and the contact hole process, and improves the yield of the process for preparing the super junction trench gate MOSFET structure.
Based on the same inventive concept, the embodiment of the application also provides a preparation method of the super-junction trench gate MOSFET layout structure, which comprises the following steps:
a first step of: a substrate 101 is provided, as shown in fig. 1 and 2, an epitaxial layer 102 is formed on a front surface of the substrate 101, wherein the epitaxial layer 102 includes: a source terminal extraction region C, a gate terminal extraction region B disposed around the source terminal extraction region C, and a peripheral terminal region a disposed around the gate terminal extraction region B.
And a second step of: as shown in fig. 3-5, a plurality of trenches are formed in the epitaxial layer 102 for depositing a gate dielectric layer 104 and all trench gates (a main gate 105, a first subsidiary gate 205, a plurality of second subsidiary gates 305 in a ring shape, and a plurality of dummy gates 405 in a ring shape).
And a third step of: a gate dielectric layer 104 is formed, and the gate dielectric layer 104 covers the bottom wall and the side wall of the trench.
Fourth step: forming a plurality of main gates 105, a first auxiliary gate 205, a plurality of second auxiliary gates 305 in a ring shape and a plurality of dummy gates 405 in a ring shape, wherein the main gates 105 cover the gate dielectric layer 104 of the source end extraction region and fill corresponding trenches, and the main gates 105 are arranged at intervals along a first direction (X direction) and are parallel to a second direction (Y direction); the first auxiliary gate 205 covers a portion of the gate dielectric layer 104 of the gate end lead-out area B and fills the corresponding trench, the first auxiliary gate 205 is located at one side of the source end lead-out area C along the first direction (X direction, transverse direction), and in this embodiment, the first auxiliary gate 205 is located at the left side of the source end lead-out area C; a plurality of annular second auxiliary gates 305 cover the remaining gate dielectric layer of the gate end lead-out area B and fill the corresponding trenches, the second auxiliary gates 305 are arranged around the gate end lead-out area B at intervals, and the dummy gates 405 are arranged around the center of the substrate 101 at intervals.
Wherein the main gate 105, the first subsidiary gate 205 and the second subsidiary gate 305 are interconnected by the trench.
Preferably, as shown in fig. 6, the first auxiliary gate 205 includes: the structure comprises two first trench gates 2051 which are parallel to a first direction (X direction) and are arranged along a second direction (Y direction), a plurality of second trench gates 2052 which are parallel to the second direction and are arranged at intervals along the first direction, and a plurality of third trench gates 2053 which are parallel to the second direction and are arranged at intervals along the first direction, wherein the two first trench gates 2051 are respectively positioned at two ends of the plurality of second trench gates 2052 to form a closed structure, and the third trench gates 2053 are positioned at two sides of the closed structure along the second direction so as to enable the closed structure (a first auxiliary gate 205) to be connected with the second auxiliary gate 305.
Further, the closed structure and the second conductive plugs 209 in the closed structure form a charge balance structure, wherein, in the closed structure, two outermost second conductive plugs parallel to the second direction are connected with the second conductive plugs parallel to the first direction in the first trench gate 2051; as indicated by the dashed line a position, the second conductive plugs 209 within the enclosed structure that are parallel to the second direction are not connected to the second conductive plugs in the first trench gate 2051 that are parallel to the first direction. According to the method and the device, the second conductive plug parallel to the second direction inside the closed structure is disconnected with the second conductive plug parallel to the first direction in the first trench gate, so that a better charge balance effect can be achieved.
Preferably, as indicated by the position of the dashed line b, the lateral dimension in width of the second trench gate 2052 closest to the source terminal extraction region is greater than or equal to the lateral dimension in width of the remaining second trench gate 2052 to the left thereof.
Preferably, as indicated by the position of the virtual line b, the lateral dimension of the second trench gate 2052 closest to the source terminal extraction region is greater than the lateral dimension of the second conductive plug 209 in width, i.e., the width of the second trench gate 2052 is required to be processed to encapsulate the second contact hole/the second conductive plug 209/the deep implant region 103.
Fifth step: a global ion implantation process is performed to form a body region 106, the body region 106 being located in the epitaxial layer 102 between the trenches and near the surface of the epitaxial layer 102. The body region 106 is formed in the source end leading-out region C, the gate end leading-out region B and the peripheral terminal region A by utilizing the global ion implantation process, so that the light cover corresponding to the body region ion implantation is reduced, the preparation process is simplified, and the manufacturing cost is reduced.
Sixth step: a selective ion implantation process is performed to form a source doped region 108, the source doped region 108 being located on the body surface of the main gate 105 side.
Seventh step: an interlayer dielectric layer 110 is formed, and the interlayer dielectric layer 110 covers the epitaxial layer 102, the main gate 105, the first auxiliary gate 205, the second auxiliary gate 305, and the dummy gate 405. Specifically, the material of the interlayer dielectric layer 110 may be silicon oxide.
Eighth step: a first contact hole, a second contact hole, a third contact hole and a fourth contact hole having a ring shape are formed, wherein the first contact hole penetrates through the interlayer dielectric layer 110 and is located in the body region 106 between the main gates 105, the second contact hole penetrates through the interlayer dielectric layer 110 and is located in the body region 106 between the first auxiliary gates 205 or the first auxiliary gates 205, the third contact hole penetrates through the interlayer dielectric layer 110 and is located in the second auxiliary gates 305, and the fourth contact hole penetrates through the interlayer dielectric layer 110 and is located in the body region between the adjacent dummy gates 405 (it can also be understood that each fourth contact hole is located in the body region 106 on the side of each of the dummy gates 405, respectively). The first contact hole, the second contact hole, the third contact hole in a ring shape, and the fourth contact hole in a ring shape may be simultaneously formed for subsequent formation of the first to fourth conductive plugs 109.
Ninth step: forming a deep injection region 103, wherein the deep injection region 103 is formed at the bottom of the first contact hole (the source doping region 108) in the source end extraction region C; in the peripheral terminal region a, a deep implant region 103 is formed at the bottom of the fourth contact hole. In the gate end extraction region B, the deep implantation region 103 is formed at the bottom of the third contact hole (the second sub-gate 305) or at the bottom of the second contact hole. The depth of the second auxiliary gate 305 is greater than the implantation depth of the body region 106, and the body region 106 is isolated by the second auxiliary gate 305+ deep implantation region 103 into an independent floating body block, so that the voltage resistance of the gate terminal extraction region B is improved, and the electrical performance of the device is improved.
Further, before forming the first conductive plug, the second conductive plug, the third conductive plug and the plurality of annular fourth conductive plugs, the preparation method of the super-junction trench gate MOSFET layout structure may further include: a selective ion implantation process is performed to form a heavily doped region 107, where the heavily doped region 107 is located in the body region 106 at the bottom of the first contact hole, the bottom of the second contact hole, the bottom of the third contact hole in a ring shape, and the bottom of the fourth contact hole in a ring shape. That is, the heavily doped region 107 is located in the body region 106 between the first conductive plug 109 and the deep implanted region 103, in the body region between the second conductive plug 209 and the deep implanted region 103, between the third conductive plug 309 and the second auxiliary gate 305, and in the body region between the fourth conductive plug 409 and the deep implanted region 103.
Tenth step: forming a first conductive plug 109, a second conductive plug 209, a third conductive plug 309 and a plurality of annular fourth conductive plugs 409, wherein the first conductive plug 109 fills the first contact hole, the second conductive plug 209 fills the second contact hole, the third conductive plug 309 fills the third contact hole, and the fourth conductive plug 409 fills the fourth contact hole.
Eleventh step: as shown in fig. 7, a first conductive layer 111 and a second conductive layer 112 are formed, the first conductive layer 111 covering a portion of the first conductive plug 109 of the source terminal extraction region C to extract the source doped region 108; the second conductive layer 112 covers a portion of the second conductive plugs 209 and a portion of the third conductive plugs 309 of the gate terminal extraction region B to extract the main gate 105 of the source terminal extraction region C.
Preferably, as shown in fig. 4 and 7, the outer edge of the second conductive layer 112 is located at an intermediate position of the region between the third conductive plug 209 in the second auxiliary gate 305 at the outermost side of the gate terminal extraction region B and the fourth conductive plug 409 at the innermost side of the peripheral terminal region C. Further, as shown in fig. 4 and 7, along the first direction (lateral direction, X direction), the inner edge of the second conductive layer 112 is located at an intermediate position of the region between the two second auxiliary gates 305 near the source-end extraction region B; in a second direction (longitudinal, Y-direction), a portion of the inner edge of the second conductive layer 112 is located on the second conductive plug 209 in the second trench gate 2052, and a portion of the inner edge of the second conductive layer 112 does not cover both ends of the second conductive plug 209 in the second trench gate 2052, i.e., a portion of the inner edge of the second conductive layer 112 is retracted to the inside of the charge balance structure; the remaining inner edge of the second conductive layer 112 covers the innermost third conductive plug 309, i.e. the remaining inner edge of the second conductive layer 112 is located at an intermediate position of the region between the innermost third conductive plug 309 and the outermost second conductive plug 209 in the second sub-gate 305.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (15)

1. The utility model provides a super junction trench gate MOSFET territory structure which characterized in that includes:
a substrate, the front side of the substrate being formed with an epitaxial layer, wherein the epitaxial layer comprises: a source terminal extraction region, a gate terminal extraction region disposed around the source terminal extraction region, and a peripheral terminal region disposed around the gate terminal extraction region;
a plurality of trenches in the epitaxial layer;
the gate dielectric layer covers the bottom wall and the side wall of the groove;
the main grid electrodes cover the grid dielectric layer of the source end leading-out area and fill the corresponding grooves, the main grid electrodes are arranged at intervals along a first direction and are parallel to a second direction, and the first direction and the second direction are mutually perpendicular;
The first auxiliary grid electrode covers part of the grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the first auxiliary grid electrode is positioned at one side of the source end leading-out area along the first direction;
the second auxiliary grid electrode covers the residual grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the second auxiliary grid electrode is arranged at intervals around the grid end leading-out area, wherein the main grid electrode, the first auxiliary grid electrode and the second auxiliary grid electrode are interconnected through the groove;
the dummy gates cover the gate dielectric layer of the peripheral terminal area and fill the corresponding grooves, and the dummy gates are arranged at intervals around the center of the substrate;
the body region is positioned in the epitaxial layer between the grooves and is close to the surface of the epitaxial layer;
the source doping region is positioned on the surface of the body region at the side of the main grid electrode;
the interlayer dielectric layer covers the epitaxial layer, the main grid electrode, the first auxiliary grid electrode, the second auxiliary grid electrode and the pseudo grid electrode;
a plurality of first conductive plugs located in body regions between the main gates;
A plurality of second conductive plugs located in the first subsidiary gates and in body regions between the first subsidiary gates;
a plurality of annular third conductive plugs, wherein the third conductive plugs are positioned in the second auxiliary grid electrode;
a plurality of annular fourth conductive plugs, wherein the fourth conductive plugs are respectively positioned in the body region of each pseudo gate side;
the deep injection region is positioned in the epitaxial layers at the bottoms of the first conductive plug, the second conductive plug and the fourth conductive plug;
a first conductive layer covering a portion of the first conductive plug of the source terminal extraction region to extract the source doped region;
and the second conductive layer covers part of the second conductive plug and part of the third conductive plug of the gate end extraction region so as to extract the main gate of the source end extraction region.
2. The superjunction trench gate MOSFET layout structure of claim 1, wherein an outer edge of said second conductive layer is located midway between a region of said second auxiliary gate outermost said gate terminal extraction region, and said fourth conductive plug innermost said peripheral termination region.
3. The super junction trench gate MOSFET layout structure of claim 1, wherein said first auxiliary gate comprises: the device comprises two first trench gates which are parallel to a first direction and are distributed along a second direction, a plurality of second trench gates which are parallel to the second direction and are distributed along the first direction at intervals, and a plurality of third trench gates which are parallel to the second direction and are distributed along the first direction at intervals, wherein the two first trench gates are respectively positioned at two ends of the plurality of second trench gates to form a closed structure, and the third trench gates are positioned at two sides of the closed structure along the second direction so that the closed structure is connected with the second auxiliary gate.
4. The superjunction trench-gate MOSFET layout structure of claim 3 wherein said closed structure and second conductive plugs in said closed structure form a charge balance structure, wherein two second conductive plugs in said closed structure that are outermost parallel to a second direction are connected to second conductive plugs in said first trench gate that are parallel to a first direction; the second conductive plug parallel to the second direction inside the closed structure is not connected with the second conductive plug parallel to the first direction in the first trench gate.
5. The super-junction trench-gate MOSFET layout structure of claim 3, wherein, in a first direction, an inner edge of said second conductive layer is located midway between two second auxiliary gates adjacent to a source-side extraction region; in a second direction, a portion of the inside edge of the second conductive layer is located over the second conductive plug in the second trench gate, and the portion of the inside edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.
6. The superjunction trench gate MOSFET layout structure of claim 3, wherein a lateral dimension of a second trench gate closest to said source terminal extraction region is greater than or equal to a lateral dimension of the remaining second trench gate in width.
7. The superjunction trench gate MOSFET layout structure of claim 3, wherein a lateral dimension in width of a second trench gate nearest said source terminal extraction region is greater than a lateral dimension in width of said second conductive plug.
8. The super junction trench gate MOSFET layout structure of claim 1, wherein the conductivity type of the ions doped in said substrate, said epitaxial layer, said source doped region is a first conductivity type; the conductivity type of the ions doped in the deep implant region and the body region is a second conductivity type.
9. The superjunction trench gate MOSFET layout structure of claim 1, further comprising: and a heavily doped region located in the body region between the first conductive plug and the deep implant region, in the body region between the second conductive plug and the deep implant region, between the third conductive plug and the second auxiliary gate, and in the body region between the fourth conductive plug and the deep implant region.
10. The preparation method of the super-junction trench gate MOSFET layout structure is characterized by comprising the following steps of:
providing a substrate, wherein an epitaxial layer is formed on the front surface of the substrate, and the epitaxial layer comprises: a source terminal extraction region, a gate terminal extraction region disposed around the source terminal extraction region, and a peripheral terminal region disposed around the gate terminal extraction region;
forming a plurality of trenches, wherein the trenches are positioned in the epitaxial layer;
forming a gate dielectric layer, wherein the gate dielectric layer covers the bottom wall and the side wall of the groove;
forming a plurality of main grids, a first auxiliary grid, a plurality of annular second auxiliary grids and a plurality of annular dummy grids, wherein the main grids cover a grid dielectric layer of a source end leading-out area and fill corresponding grooves, the main grids are arranged at intervals along a first direction and are parallel to a second direction, and the first direction and the second direction are mutually perpendicular; the first auxiliary grid electrode covers part of the grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the first auxiliary grid electrode is positioned at one side of the source end leading-out area along the first direction; the second auxiliary grid electrode covers the residual grid dielectric layer of the grid end leading-out area and fills the corresponding groove, and the second auxiliary grid electrode is arranged at intervals around the grid end leading-out area, wherein the main grid electrode, the first auxiliary grid electrode and the second auxiliary grid electrode are interconnected through the groove; the dummy gate covers the gate dielectric layer of the peripheral terminal area and fills the corresponding groove, and the dummy gate is arranged around the center of the substrate at intervals;
Performing a global ion implantation process to form a body region, wherein the body region is positioned in the epitaxial layer between the trenches and is close to the surface of the epitaxial layer;
performing a selective ion implantation process to form a source doped region, wherein the source doped region is positioned on the surface of the body region at the side of the main grid electrode;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the epitaxial layer, the main grid electrode, the first auxiliary grid electrode, the second auxiliary grid electrode and the pseudo grid electrode;
forming a first contact hole, a second contact hole, a third contact hole and a fourth contact hole which are annular, wherein the first contact hole penetrates through the interlayer dielectric layer and is positioned in a body region between the main grid electrodes, the second contact hole penetrates through the interlayer dielectric layer and is positioned in the first auxiliary grid electrodes, the third contact hole penetrates through the interlayer dielectric layer and is positioned in the second auxiliary grid electrodes, and the fourth contact hole penetrates through the interlayer dielectric layer and is positioned in the body region between the adjacent pseudo grid electrodes;
forming a deep injection region, wherein the deep injection region is positioned in the epitaxial layer at the bottoms of the first contact hole, the second contact hole and the fourth contact hole;
forming a first conductive plug, a second conductive plug, a third conductive plug and a plurality of annular fourth conductive plugs, wherein the first conductive plug fills the first contact hole, the second conductive plug fills the second contact hole, the third conductive plug fills the third contact hole, and the fourth conductive plug fills the fourth contact hole;
And forming a first conductive layer and a second conductive layer, wherein the first conductive layer covers part of the first conductive plug of the source end extraction region to extract the source doping region, and the second conductive layer covers part of the second conductive plug and part of the third conductive plug of the gate end extraction region to extract the main gate of the source end extraction region.
11. The method for fabricating a super junction trench gate MOSFET layout structure of claim 10, wherein an outer edge of said second conductive layer is formed at a location intermediate a region between a third conductive plug in said second auxiliary gate outermost said gate terminal extraction region and said fourth conductive plug innermost said peripheral termination region.
12. The method for preparing a super junction trench gate MOSFET layout structure of claim 10, wherein said first auxiliary gate comprises: the device comprises two first trench gates which are parallel to a first direction and are distributed along a second direction, a plurality of second trench gates which are parallel to the second direction and are distributed along the first direction at intervals, and a plurality of third trench gates which are parallel to the second direction and are distributed along the first direction at intervals, wherein the two first trench gates are respectively positioned at two ends of the plurality of second trench gates to form a closed structure, and the third trench gates are positioned at two sides of the closed structure along the second direction so that the closed structure is connected with the second auxiliary gate.
13. The method for fabricating a super junction trench gate MOSFET layout structure of claim 12, wherein said closed structure and second conductive plugs in said closed structure form a charge balance structure, wherein two second conductive plugs in said closed structure that are outermost in parallel with a second direction are connected to second conductive plugs in said first trench gate that are parallel with a first direction; the second conductive plug parallel to the second direction inside the closed structure is not connected with the second conductive plug parallel to the first direction in the first trench gate.
14. The method for fabricating a super junction trench gate MOSFET layout structure of claim 12, wherein, in a first direction, an inner edge of said second conductive layer is located at a middle position of a region between two second auxiliary gates adjacent to a source terminal extraction region; in a second direction, a portion of the inside edge of the second conductive layer is located over the second conductive plug in the second trench gate, and the portion of the inside edge of the second conductive layer does not cover both ends of the second conductive plug in the second trench gate; the remaining inner edge of the second conductive layer covers the innermost third conductive plug.
15. The method of fabricating a super junction trench gate MOSFET layout structure of claim 12 wherein the lateral dimension of the second trench gate closest to said source terminal extraction region is greater than or equal to the lateral dimension of the remaining second trench gate in width.
CN202310203962.6A 2023-03-06 2023-03-06 Super-junction trench gate MOSFET layout structure and preparation method thereof Pending CN116314332A (en)

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