CN116314216A - CIS sensor based on silicon-based columnar body array, preparation method and application - Google Patents

CIS sensor based on silicon-based columnar body array, preparation method and application Download PDF

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CN116314216A
CN116314216A CN202211101598.4A CN202211101598A CN116314216A CN 116314216 A CN116314216 A CN 116314216A CN 202211101598 A CN202211101598 A CN 202211101598A CN 116314216 A CN116314216 A CN 116314216A
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cis sensor
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陈晓刚
胡朝阳
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Suzhou Haiguang Xinchuang Photoelectric Technology Co ltd
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H—ELECTRICITY
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Abstract

The invention relates to a CIS sensor based on a silicon-based columnar array, a preparation method and application thereof, which belong to the technical field of photoelectric sensors, can improve the charge collection efficiency and the overall quantum efficiency of the CIS sensor, effectively improve the detection area and the duty ratio, greatly reduce the crosstalk of adjacent pixel parts and improve the imaging quality; the sensor comprises a silicon wafer layer positioned at the bottom, a conductive film layer positioned at the top and a two-dimensional silicon-based micro/nano column array positioned between the silicon wafer layer and the conductive film layer; the two-dimensional silicon-based micro/nano column array comprises a plurality of silicon-based columns with certain smoothness in the vertical arrangement periphery, wherein the bottom ends of the silicon-based columns are connected with the upper surface of the silicon wafer layer, and the top ends of the silicon-based columns are connected with the lower surface of the conductive film layer; gaps between different silicon-based columns are filled with air; each silicon-based column body has a vertical p-i-n structure.

Description

CIS sensor based on silicon-based columnar body array, preparation method and application
Technical Field
The invention relates to the technical field of photoelectric sensors, in particular to a CIS sensor based on a silicon-based columnar array and a preparation method thereof.
Background
Photoelectric sensors are key components indispensable to modern intelligent equipment. The CIS (CMOS Image Sensor) image sensor has wide and deep application in a plurality of fields such as digital cameras, machine vision, consumer mobile terminal devices (such as mobile phones, tablet computers, intelligent wearable devices and the like), portable photoelectric detection devices, laser radars, security protection, telemedicine, high-end full-automatic manufacturing devices (including automatic product quality monitoring devices), high-end scientific research devices (high-end spectrometers, high-end fluorescence microscopes and high-end astronomical detection devices) and the like.
The traditional CIS image sensor utilizes the advantage of the CMOS integrated circuit that the large-scale production is convenient, integrates a large number of photodiodes and related signal reading circuits on a silicon-based chip, and finally achieves the ideal state of high speed, high precision and high dynamic range through continuous optimal design. Since the photoelectric conversion element of the CIS image sensor is a diode, which is one of the core elements of the CMOS circuit, the fabrication of the CIS image sensor chip can be completely seamlessly matched with the fabrication of the conventional chip. Since the 90 s of the last century, through the continuous development of more than 30 years, CIS image sensors have been capable of achieving excellent image sensing characteristics of high resolution, full color range, low digital noise, etc., and in addition to the high speed, high precision, and high dynamic range mentioned above, CIS has been an absolute dominant in digital image sensors instead of charge transfer mode image Sensors (CCDs). Moreover, the cost advantage is very significant since it is well suited for mass production of CMOS processes.
CMOS photo-image sensors employ conventional digital logic fabrication processes to fabricate photo-sensing elements on planar silicon-based semiconductor wafers and integrate them with drive and readout circuitry. This limits the effective lighting area, or duty cycle (FF), available for the corresponding CIS sensor, with FF <10% for most CIS, and most advanced CIS's are only up to around 20%. Even with CIS devices employing a back-to-back illumination (BSI) scheme, FF can be relatively improved, but all of the photodetector elements are fabricated on the same device plane, with spatial physical connections between each other. When the detection units are irradiated by light, charges generated by the photoelectric effect always have a certain probability of being diffused to adjacent detection units, so that pixel diffusion and image blurring are generated, and the resolution of the image is reduced. Especially in weak light detection, in order to increase the sensitivity of each pixel, together with the bias voltage of each photodiode being very high (tens of volts or even higher), the average kinetic energy obtained by the photoelectrons in each sensor is higher, and this dispersion effect is also more remarkable. In the conventional CMOS process, an oxide insulating layer may be introduced between adjacent photosensitive pixels by an ion implantation method, or a spatial isolation trench may be introduced between the photosensitive pixels by a plasma reactive etching (ICP-RIE) method, so as to reduce a charge diffusion effect. The former generally requires a large chip area to further reduce the duty cycle of the CIS sensor, and neither uniformity of the full chip area nor accuracy of the lateral dimensions can be achieved too high. The latter tends to cause the device walls to be very rough, affecting light absorption and photoelectric conversion efficiency, and may even damage the crystal structure of the wafer, affecting the performance of the entire device.
Accordingly, there is a need to develop a new three-dimensional CIS sensor based on a silicon-based pillar array to address the deficiencies of the prior art, to solve or mitigate one or more of the problems described above.
Disclosure of Invention
In view of the above, the invention provides a three-dimensional CIS sensor based on a silicon-based columnar array, a preparation method and application thereof, which can improve the charge collection efficiency and the overall quantum efficiency of the CIS sensor, effectively improve the detection area and the duty ratio, greatly reduce the crosstalk of adjacent pixel parts and improve the imaging quality.
In one aspect, the invention provides a CIS sensor based on a silicon-based pillar array, which is characterized in that the CIS sensor comprises a silicon wafer layer at the bottom, a conductive thin film layer at the top, and a two-dimensional silicon-based micro/nano pillar array between the silicon wafer layer and the conductive thin film layer;
the two-dimensional silicon-based micro/nano column array comprises a plurality of silicon-based columns with certain smoothness in the vertical arrangement periphery, wherein the bottom ends of the silicon-based columns are connected with the upper surface of the silicon wafer layer, and the top ends of the silicon-based columns are connected with the lower surface of the conductive film layer; gaps between different silicon-based columns are filled with air, nitrogen or inert gas;
each silicon-based column body has a vertical p-i-n structure.
In aspects and any one of the possible implementations described above, there is further provided an implementation, wherein the silicon-based columnar body has a diameter of 500nm to 5 μm.
In aspects and any one of the possible implementations described above, there is further provided an implementation in which the smoothness of the silicon-based columnar body periphery is atomic-scale smoothness.
In aspects and any possible implementation manner as described above, there is further provided an implementation manner, where the duty cycle of the two-dimensional silicon-based micro/nano-pillar array is above 50%.
In the aspect and any possible implementation manner described above, there is further provided an implementation manner, wherein a ratio of a height to a diameter of the silicon-based columnar body is 2 to 20.
In another aspect, the present invention provides a method for preparing a CIS sensor based on a silicon-based pillar array, the method being used for preparing a CIS sensor based on a silicon-based pillar array as described in any one of the above; the preparation method comprises the following steps:
s1, sequentially growing four film layers of a p+ conducting layer, a p-type silicon layer, an intrinsic silicon layer and an n-type silicon layer on the surface of a silicon wafer;
s2, preparing a photoetching mask layer on the surface of the n-type silicon layer;
s3, etching a plurality of groove structures in an array on the photoetching mask layer through a photoetching process;
s4, depositing catalytic metal in the etched groove structure;
s5, washing off the residual photoetching mask layer, and only leaving the catalytic metal array;
s6, etching the four thin film layers grown in the step S1 by adopting etching liquid to obtain a two-dimensional silicon-based micro/nano column array;
and S7, covering an n+ type conductive film layer above the two-dimensional silicon-based micro/nano column array.
In aspects and any possible implementation manner as described above, there is further provided an implementation manner, wherein the thin film layer is grown in step S1 by using a PECVD process.
In the aspect and any possible implementation manner as described above, there is further provided an implementation manner, where the catalytic metal in step S4 is gold.
In the aspects and any possible implementation manner as described above, there is further provided an implementation manner, where the etching solution in step S6 is H 2 O 2 And etching is performed using a mactech process.
In still another aspect, the present invention provides an application of the CIS sensor based on a silicon-based columnar array as described in any one of the above, where the CIS sensor is integrated with a driving circuit and a readout circuit to obtain a three-dimensional integrated photoelectric sensor chip.
Compared with the existing planar CIS sensor preparation technology, the invention has the following main advantages:
1. the 3D device layout, the SPAD nano array and the supporting circuit can not compete with each other for the area of the wafer, so that the detection area of the detection element is greatly improved (the duty ratio can be realized to be more than 50%);
2. the adjacent pixel units are physically isolated, so that the photoelectric crosstalk between the adjacent pixel units is greatly reduced;
3. the side wall of the micro/nano wire can realize atomic level smoothness, and the nano wire forms an optical waveguide with very high light collecting efficiency;
4. the ultra-high height-diameter ratio of the micro/nano wire can realize the interaction distance between ultra-long light and substances, greatly improve the photoelectric conversion efficiency, and is particularly suitable for CIS sensing chips under the condition of weak light (APD or SPAD mode);
5. the process for preparing the SPAD nanowire array by MacEth is completely matched with the existing CMOS integrated circuit preparation process, and is convenient for large-scale integration, thereby realizing a micro-light image detection device with ultra-sensitivity and ultra-high image resolution.
Of course, it is not necessary for any of the products embodying the invention to achieve all of the technical effects described above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a process flow diagram for preparing a silicon-based large-scale two-dimensional micro/nano-pillar array using MacEth according to one embodiment of the present invention;
FIG. 2 is a Scanning Electron Microscope (SEM) photograph of a p+ -type nanowire array (upper layer) and an n+ -type nanowire array (lower layer) prepared using a MacEtch process according to one embodiment of the present invention;
fig. 3 is a Scanning Electron Microscope (SEM) photograph of a p+ silicon nanowire array prepared with gold (Au) as a catalyst, according to an embodiment of the present invention.
Detailed Description
For a better understanding of the technical solution of the present invention, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Aiming at the defects of the prior art, the invention adopts a metal catalyzed chemical etching method to prepare the two-dimensional silicon-based micro/nano column array CIS photoelectric sensor, which can effectively overcome the defects of the prior CIS, firstly, the invention can effectively improve the duty ratio of the CMOS photoelectric sensor to more than 70 percent, greatly improve the effective receiving area of optical signals and further improve the sensitivity of the CIS sensor. And secondly, the charge crosstalk between adjacent pixels can be effectively stopped by a physical space isolation method, the pixel dispersion effect is reduced to the minimum, and the spatial resolution of the CIS sensor is greatly improved. And the production process adopted by the invention can be used for generating a large-scale two-dimensional area array sensor array at one time, and can easily realize a pixel array of more than 2000 multiplied by 2000. And the size of a single pixel can be controlled to be in the range from hundreds of nanometers to hundreds of micrometers as required, and the area of the whole CIS sensing chip can be controlled to be in the range from hundreds of to tens of square millimeters. Fourth, the production process of the invention can manufacture the micro/nano column photoelectric detection array with the side wall reaching the atomic level smoothness. The photoelectric detection array can be independent of the production of the CMOS digital logic circuit, and is integrated with the CMOS driving and reading chips in a three-dimensional way in a back wafer bonding way, so that the requirement of mass production is met.
The invention adopts a metal catalyzed chemical etching method (Metal assisted chemical etching, macEth) to prepare a silicon-based large-scale two-dimensional micro/nano column array in a silicon material as a photosensitive pixel, and combines the photosensitive pixel with a driving and reading circuit in a three-dimensional integration mode, thereby realizing a three-dimensional integrated photoelectric sensing chip with high resolution, high speed, high light collecting efficiency and high flexibility. The process flow for preparing the silicon-based large-scale two-dimensional micro/nano-pillar array by using MacEtch is shown in FIG. 1, and comprises the following steps:
step 1, sequentially growing four thin film layers, namely a p+ conductive layer (p+ contact layer in fig. 1), p-type silicon (p Si layer in fig. 1), intrinsic silicon (Si layer in fig. 1) and n-type silicon (n Si layer in fig. 1), on the surface of a general silicon Wafer (Si Wafer layer in the figure) by using PECVD, and sequentially stacking the four thin film layers; the corresponding thickness of each layer can be precisely controlled by adjusting the growth process according to the specific application requirements;
step 2, covering a photoetching mask layer (mask layer in fig. 1) on the surface of the silicon wafer with the corresponding film coating;
step 3, precisely etching a regular two-dimensional array groove in the mask layer through photoetching;
step 4, depositing catalytic metal (black column in fig. 1) in the etching groove of the mask layer, wherein the catalytic metal is most suitable gold;
step 5, washing off mask layer residues, and only leaving a two-dimensional catalytic metal array on the surface of the wafer;
step 6, adding an etching solution (typically H 2 O 2 ) Then, a silicon-based large-scale two-dimensional micro/nano column array can be manufactured at one time in a MacEtch mode; each of the p-i-n structures commonly used for the photodiodes are formed in the vertical direction; covering n+ type transparent conductive film layer above the micro/nano column array to form two-dimensional silicon-based micro/nanoA pillar array CIS photosensor.
Fig. 2 is a Scanning Electron Microscope (SEM) photograph of a p+ -type nanowire array (upper layer) and an n+ -type nanowire array (lower layer) prepared using a mactech process. Figures (a) - (c) are p+ nanowire arrays with nanowire diameters of 800, 550, and 200nm, respectively; graphs (d) - (f) are n+ nanowire arrays with nanowire diameters of 800, 550, and 200nm, respectively. The chemical etching process can reach atomic level smoothness of the side wall of the prepared micron/nanometer column. As shown in FIG. 2 (c), the uniformity of the pillars is not good enough for the 200nm nano-pillars, which is not suitable for large-scale industrial production.
Since the density of the micro/nano-pillar array and the size (diameter, pitch, etc.) of each micro/nano-pillar set are determined by the photolithographic mask, the precision thereof can reach several to tens of nanometers. The duty ratio of the micro/nano column array can easily reach 50% or even more than 70% through theoretical design and process optimization. Fig. 3 is a Scanning Electron Microscope (SEM) photograph of a p+ silicon nanowire array prepared using mactech with gold (Au) as a catalyst. The diameter of the nanowire is 500 nm-5 mu m, and the aspect ratio of the nanowire is 2-20.
The invention adopts a metal catalyzed chemical etching method to prepare a silicon-based two-dimensional micro/nano column array in a silicon material, and the silicon-based two-dimensional micro/nano column array is used as a photosensitive pixel to form a large-scale CIS sensing chip. The novel CIS chip has large effective detection area and high duty ratio. In addition, each pixel is separated by an etched space gap, so that crosstalk between adjacent pixels caused by charge dispersion is greatly reduced, and imaging quality can be effectively improved. The vertical p-i-n structure and the smooth side wall limit the radial movement of holes and electrons generated after sensitization in the micro/nano column when the vertical bias voltage is applied, reduce the charge annihilation caused by the rough surface of the side wall, improve the charge collection efficiency and further improve the overall quantum efficiency of the CIS sensor. Because the silicon material adopted by the micro/nano columns has higher refractive index (about 3.5), the gap between the micro/nano columns is filled with air, the refractive index is close to 1, and a larger refractive index difference exists between the micro/nano columns. This allows each silicon-based micro/nano-pillar to be considered as a highly efficient optical waveguide with light collection efficiencyThe numerical aperture formula of the fiber can be used to estimate:
Figure BDA0003840702470000101
Figure BDA0003840702470000102
thus alpha is>90 deg.. It can be understood that light incident from any angle above the micro/nano column is refracted into the micro/nano column, thereby greatly improving the light collection efficiency of each pixel. A finer FDTD vertical simulation shows that even if no condensing element such as a micro lens is used, the light collecting efficiency of the silicon-based micro/nano column in the near infrared to visible wave band can reach more than 95%. The filling gas may also be nitrogen or an inert gas.
The novel CIS chip can be combined with a driving and reading circuit in a three-dimensional integration mode, so that the three-dimensional integrated photoelectric sensing chip with high resolution, high speed, high light collecting efficiency and high flexibility is realized.
The invention can prepare large-scale (from full HD to 8K) two-dimensional silicon-based micro/nano-pillar arrays by combining MacEth technology with film growth and photoetching technology in the traditional CMOS technology. Each micro/nano column is a vertical p-i-n structure and can be used as an independent photoelectric sensor pixel. The lateral geometry of the micro/nano-pillars can be precisely controlled by photolithography. Through the optimal design of the diameter of the micro/nano column and the distance between adjacent pixels, the duty ratio of the photoelectric sensor can be greatly improved, and the light collection efficiency is improved. For example, if the ratio of the radius of each micro/nano column to the distance between adjacent micro/nano columns is 4.5:1, the duty cycle of the whole micro/nano column array can reach more than 60%, which is far higher than that of the best planar CIS sensor at present, which is less than 20%.
The above detailed description is provided for the CIS sensor based on the silicon-based columnar body array, the preparation method and the application provided by the embodiment of the present application. The above description of embodiments is only for aiding in understanding the method of the present application and its core ideas; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. A CIS sensor based on a silicon-based pillar array, wherein the CIS sensor comprises a silicon wafer layer at the bottom, a conductive thin film layer at the top, and a two-dimensional silicon-based micro/nano pillar array between the silicon wafer layer and the conductive thin film layer;
the two-dimensional silicon-based micro/nano column array comprises a plurality of silicon-based columns with certain smoothness in the vertical arrangement periphery, wherein the bottom ends of the silicon-based columns are connected with the upper surface of the silicon wafer layer, and the top ends of the silicon-based columns are connected with the lower surface of the conductive film layer; gaps between different silicon-based columns are filled with air, nitrogen or inert gas;
each silicon-based column body has a vertical p-i-n structure.
2. The CIS sensor based on a silicon-based pillar array according to claim 1, wherein the diameter of the silicon-based pillar is 500nm to 5 μm.
3. The CIS sensor based on a silicon-based pillar array according to claim 1, wherein the smoothness of the outer periphery of the silicon-based pillar is atomic-level smoothness.
4. The CIS sensor of claim 1, wherein the two-dimensional silicon-based micro/nano pillar array has a duty cycle of 50% or more.
5. The CIS sensor based on a silicon-based pillar array according to claim 1, wherein the ratio of the height and diameter of the silicon-based pillar is 2 to 20.
6. A method for manufacturing a CIS sensor based on a silicon-based pillar array, wherein the method is used for manufacturing the CIS sensor based on a silicon-based pillar array according to any one of claims 1 to 5; the preparation method comprises the following steps:
s1, sequentially growing four film layers of a p+ conducting layer, a p-type silicon layer, an intrinsic silicon layer and an n-type silicon layer on the surface of a silicon wafer;
s2, preparing a photoetching mask layer on the surface of the n-type silicon layer;
s3, etching a plurality of groove structures in an array on the photoetching mask layer through a photoetching process;
s4, depositing catalytic metal in the etched groove structure;
s5, washing off the residual photoetching mask layer, and only leaving the catalytic metal array;
s6, etching the four thin film layers grown in the step S1 by adopting etching liquid to obtain a two-dimensional silicon-based micro/nano column array;
and S7, covering an n+ type conductive film layer above the two-dimensional silicon-based micro/nano column array.
7. The method for manufacturing a CIS sensor based on a silicon-based pillar array according to claim 6, wherein the thin film layer is grown by a PECVD process in step S1.
8. The method for manufacturing a CIS sensor based on a silicon-based pillar array according to claim 6, wherein the catalytic metal in step S4 is gold.
9. The method for manufacturing a CIS sensor based on a silicon-based pillar array according to claim 6, wherein the etching solution in step S6 is H 2 O 2 And etching is performed using a mactech process.
10. Use of a CIS sensor based on an array of silicon-based pillars according to any one of claims 1-5, characterized in that the CIS sensor is integrated with a driving circuit and a readout circuit to obtain a three-dimensional integrated photo-sensor chip.
CN202211101598.4A 2022-09-09 2022-09-09 CIS sensor based on silicon-based columnar body array, preparation method and application Pending CN116314216A (en)

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