CN116314115A

CN116314115A - Semiconductor packaging device

Info

Publication number: CN116314115A
Application number: CN202111461587.2A
Authority: CN
Inventors: 叶昶麟
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2023-06-23

Abstract

The embodiment of the present disclosure provides a semiconductor packaging apparatus, including: and the rewiring layer is provided with a capacitor, the capacitor comprises a first electrode, a second electrode and a conductive particle layer positioned between the first electrode and the second electrode, and the surface of the conductive particle layer is coated with a barrier layer.

Description

Semiconductor packaging device

Technical Field

The present disclosure relates to the field of semiconductor packaging technology, and in particular, to a semiconductor packaging apparatus.

Background

In the design of disposing the capacitor in the interlayer of the upper and lower substrates, the common MLCC (Multi-layer Ceramic Capacitors, chip Multi-layer) and SMD (Surface Mount Technology, surface mount) capacitors are exemplified by chip capacitors, and if the capacitance is to be increased, the capacitance size needs to be increased, so that the overall size of the package device is limited.

Disclosure of Invention

The present disclosure provides a semiconductor package apparatus.

In a first aspect, the present disclosure provides a semiconductor package apparatus comprising:

and the rewiring layer is provided with a capacitor, the capacitor comprises a first electrode, a second electrode and a conductive particle layer positioned between the first electrode and the second electrode, and the surface of the conductive particle layer is coated with a barrier layer.

In some alternative embodiments, the capacitor is a non-polar capacitor.

In some alternative embodiments, the apparatus further comprises:

the first electronic element and the second electronic element are adjacently arranged on the rewiring layer.

In some alternative embodiments, the conductive particle layer includes a plurality of conductive particles coated with a barrier layer, and electrical coupling between adjacent conductive particles forms a capacitance.

In some alternative embodiments, the diameter of the conductive particles comprises 1 to 10 microns.

In some alternative embodiments, the redistribution layer has a plurality of capacitors arranged in a matrix.

In some alternative embodiments, at least two of the plurality of capacitors are electrically connected.

In some alternative embodiments, the redistribution layer comprises a first dielectric layer;

the first dielectric layer comprises a corresponding upper surface, a corresponding lower surface and a first through hole extending from the upper surface to the lower surface, the conductive particle layer is arranged in the first through hole, and the first electrode and the second electrode are correspondingly arranged on the upper surface and the lower surface.

In some alternative embodiments, the redistribution layer comprises a second dielectric layer;

the second dielectric layer comprises a second through hole, the side wall of the second dielectric layer is exposed through the second through hole, the first electrode and the second electrode are arranged on the side wall, and the conductive particle layer is arranged in the second through hole.

In some alternative embodiments, the barrier layer is an insulating material.

In some alternative embodiments, the apparatus further comprises:

the electric connecting piece is arranged below the rewiring layer and is electrically connected with the rewiring layer.

The semiconductor packaging device provided in the present disclosure includes: the rewiring layer is provided with a capacitor, the capacitor comprises a first electrode, a second electrode and a conductive particle layer positioned between the first electrode and the second electrode, and the surface of the conductive particle layer is coated with a barrier layer; here, the conductive particle layer with the surface coated with the barrier layer forms a capacitance structure between the first electrode and the second electrode, so that the capacitance value of the capacitor can be improved.

Drawings

Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings:

fig. 1A is a schematic longitudinal sectional structure of one embodiment of a semiconductor package apparatus according to the present disclosure;

FIG. 1B is a schematic diagram of a partial structure corresponding to the dashed line portion in FIG. 1A;

fig. 2A is a schematic structural view of yet another embodiment of a semiconductor package apparatus according to the present disclosure;

FIG. 2B is a schematic diagram illustrating a partial structure corresponding to the dotted line portion in FIG. 2A;

3A-3E are cross-sectional views of a semiconductor package apparatus manufactured at various stages according to one embodiment of the present disclosure;

FIGS. 4A, 4B, 4C, 4D, 4Ea, 4F, and 4G are cross-sectional views of a semiconductor package apparatus fabricated at various stages according to yet another embodiment of the present disclosure;

fig. 4Eb is a schematic top view of the semiconductor package apparatus of fig. 4 Ea.

Symbol description:

11-a rewiring layer; 111a first dielectric layer; 111 a-upper surface; 111 b-lower surface; 1111-a first sub-dielectric layer; 1112 a second sub-dielectric layer; 112-a second dielectric layer; 113-a first redistribution line; 114-a second redistribution line; 115-third redistribution lines; 12-a capacitor; 121-a first electrode; 122-a second electrode; 123-a layer of conductive particles; 1231-conductive particles; 124 a barrier layer; 13-a first electronic component; 14-a second electronic component; 15-electrical connectors; 21-a first through hole; 22-a second through hole; 23-bonding pads; 24-via holes; 25-metal layer.

Detailed Description

The technical problems to be solved by the present disclosure and the technical effects to be produced will be readily apparent to those skilled in the art from the following descriptions of the present disclosure, which are given in connection with the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. In addition, for convenience of description, only a portion related to the related invention is shown in the drawings.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the descriptions of the structures, proportions, sizes, etc. for the understanding and reading of the disclosure, and are not intended to limit the applicable limitations of the disclosure, so that any structural modifications, proportional changes, or adjustments of sizes are not technically essential, and thus, any structural modifications, proportional changes, or adjustments of sizes may fall within the scope of the disclosure without affecting the efficacy or achievement of the present disclosure. Meanwhile, the terms such as "upper", "first", "second", and "a" and the like are also used in the present specification for convenience of description, and are not intended to limit the scope of the disclosure, but rather to change or adjust the relative relationship thereof, and should be considered as the scope of the disclosure without substantial change of technical content.

It should be further noted that, the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the upper view direction.

In addition, embodiments of the present disclosure and features of embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring to fig. 1A and 1B, fig. 1A is a schematic view of a longitudinal cross-sectional structure of one embodiment of a semiconductor package apparatus according to the present disclosure, and fig. 1B is a schematic view of a partial structure corresponding to a broken line portion in fig. 1A from an oblique view.

As shown in fig. 1A and 1B, the semiconductor package apparatus 100A may include:

the rewiring layer 11 is provided with a capacitor 12, the capacitor 12 comprises a first electrode 121, a second electrode 122 and a conductive particle layer 123 positioned between the first electrode 121 and the second electrode 122, wherein the surface of the conductive particle layer 123 is coated with a barrier layer 124.

The redistribution layer 11 may be a redistribution layer (RDL, re-Distribution Layer) composed of conductive traces and Dielectric material (Dielectric). It should be noted that the present disclosure is not limited thereto, and the re-wiring layer may be formed by using currently known or future developed re-wiring layer forming techniques, for example, but not limited to, photolithography, electroplating (plating), electroless plating (Electroless plating), and the like. Here, the dielectric material may include organic and/or inorganic matters, wherein the organic matters may be, for example: polyamide fibers (PA), polyimide (PI), epoxy resins (Epoxy), poly-p-phenylene benzobisoxazole, PBO) fibers, FR-4 Epoxy glass laminates, PP (pre reg, prePreg, or semi-cured resins, prepregs), ABF (Ajinomoto Build-up Film), etc., while the inorganic material may be, for example, silicon (Si), glass, ceramics (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), or the like, and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The redistribution layer 11 may further include an interconnect structure (interconnect), such as a Conductive trace (Conductive trace), a Conductive Via (Conductive Via), and the like. Here, the conductive via may be a via hole, a buried hole, or a blind hole, and the via hole, the buried hole, or the blind hole may be filled with a conductive material such as a metal or a metal alloy, where the metal may be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof, for example.

In some alternative embodiments, as shown in fig. 1A, the redistribution layer 11 may include a first redistribution line 113 and a second redistribution line 114, where the capacitors 12 are connected in series or parallel through the first redistribution line 113 or the second redistribution line 114 to adjust and control a required capacitance value, so as to provide voltage stabilization and filtering of the power consumption power, where the redistribution layer 11 may further include an inductance element, to assist in voltage stabilization and filtering of the power consumption power.

As shown in fig. 1B, the conductive particle layer 123 may include a plurality of conductive particles 1231 covered by the barrier layer 124, and the adjacent conductive particles 1231 are electrically coupled to form a capacitor.

Here, the conductive particles 1231 may include a metal material, and may be, for example, barium titanium (ba+ti) alloy, copper (Cu), tantalum (Ta), or nickel (Ni). Correspondingly, the barrier layer 124 may include an insulating material, which may be barium titanium oxide (BaTiO 3), copper oxide (CuO), tantalum oxide (TaO 2), or nickel oxide (NiO 2), for example.

In some embodiments, the conductive particles 1231 may be formed by sputtering and then oxidized on their surface to form the barrier layer 124.

The first electrode 121 and the second electrode 122 may be made of a conductive material such as copper or nickel, for example. In some embodiments, as shown in fig. 1A and 1B, the first electrode 121 and the second electrode 122 are disposed in a staggered manner.

In some alternative embodiments, as shown in fig. 1A, the redistribution layer 11 includes a first dielectric layer 111.

The first dielectric layer 111 includes corresponding upper and

lower surfaces

111a and 111b, and a first via 21 extending from the upper surface 111a to the lower surface 111b, the conductive particle layer 123 is disposed in the first via 21, and the first and

second electrodes

121 and 122 are disposed on the upper and

lower surfaces

111a and 111b, respectively.

The first electrode 121 and the second electrode 122 may be completely or partially overlapped in a direction perpendicular to the upper surface 111a, and the non-overlapped portion may be used to provide a connection portion for the conductive Via, so as to reduce unnecessary influence and damage to the conductive particle layer 123 caused by a process of forming the conductive Via and change a predetermined capacitance. Wherein the conductive Via connecting the second electrode 122 is connected to the second electrode 122 by a narrower portion (as shown in FIG. 1A), and the conductive Via connecting the first electrode 121 is connected to the first electrode 121 by a paid portion (as shown in FIG. 1A).

In some alternative embodiments, the diameter of the conductive particles 1231 may comprise 1 to 10 microns.

In some alternative embodiments, capacitor 12 may comprise a non-polar capacitor.

In some alternative embodiments, as shown in fig. 1A, the semiconductor package apparatus 100A may further include: the first electronic component 13 and the second electronic component 14 are adjacently disposed on the rewiring layer 11.

In the present embodiment, the first electronic component 13 and the second electronic component 14 may be, for example, a die (die), an ASIC (Application Specific Integrated Circuit ) chip, a power management circuit (Power Management Integrated Circuit, PMIC) chip, or an HBM (High Bandwidth Memory ) chip, or the like. The first electronic component 13 and the second electronic component 14 may be the same or different electronic components, which is not limited by the present disclosure.

In some alternative embodiments, as shown in fig. 1A, the redistribution layer 11 may further include a third redistribution line 115, where the third redistribution line 115 is electrically connected to the first electronic component 13 and the second electronic component 14. The third redistribution line 115 may be used as a medium for electrical signal communication between the first electronic device 13 and the second electronic device 14, and the third redistribution line 115 may be used to provide digital signal transmission. Wherein the third redistribution line 115 forms an open circuit with the first redistribution line 113 and the second redistribution line 114.

In some alternative embodiments, as shown in fig. 1A, the semiconductor package apparatus 100A may further include: the electrical connector 15 is disposed under the redistribution layer 11 and electrically connected to the redistribution layer 11.

The electrical connection 15 may be, for example, a Solder ball (Solder ball), a Solder bump (Solder bump), a conductive post (Conductive Pillar), a Solder Pad (Solder Pad), or the like.

In some alternative embodiments, as shown in fig. 1A and 1B, the capacitor 12 may comprise a horizontal pinch capacitor.

In some alternative embodiments, as shown in fig. 1A, the redistribution layer 11 has a plurality of capacitors 12, with the plurality of capacitors 12 being arranged in a matrix.

In some alternative embodiments, at least two capacitors 12 of the plurality of capacitors 12 are electrically connected. The connection manner of the electrical connection between at least two capacitors 12 in the plurality of capacitors 12 in the embodiments of the present disclosure is not particularly limited, and for example, the at least two capacitors 12 may be electrically connected through the interconnection structure of the redistribution layer 11.

Referring to fig. 2A and 2B, fig. 2A is a schematic structural view of still another embodiment of a semiconductor package apparatus according to the present disclosure, and fig. 2B is a schematic partial structural oblique view corresponding to a broken line portion in fig. 2A. The semiconductor package apparatus 200A shown in fig. 2A is similar to the semiconductor package apparatus 100A shown in fig. 1A, except that, as shown in fig. 2A and 2B, in the semiconductor package apparatus 200A, the first electrode 121 and the second electrode 122 are disposed opposite to each other from left to right.

In some alternative embodiments, as shown in fig. 2A, the redistribution layer 11 includes a second dielectric layer 112.

The second dielectric layer 112 includes a second via hole 22, a sidewall of the second dielectric layer 112 is exposed through the second via hole 22, the first electrode 121 and the second electrode 122 are disposed on the sidewall of the second dielectric layer 112, and the conductive particle layer 123 is disposed in the second via hole 22.

In some alternative embodiments, as shown in fig. 2A and 2B, the capacitor 12 may comprise a vertical fill capacitance.

According to the embodiment, the conductive particle layer with the surface coated with the barrier layer forms a capacitance structure between the first electrode and the second electrode, so that the capacitance value of the capacitor can be improved.

Referring now to fig. 3A-3E, fig. 3A-3E are schematic longitudinal cross-sectional structural views of

semiconductor packages

300A, 300B, 300C, 300D, and 300E fabricated at various stages according to one embodiment of the present disclosure. The figures have been simplified in order to facilitate a better understanding of aspects of the present disclosure.

Referring to fig. 3A, a first sub-dielectric layer 1111 is provided, and a second electrode 122 is disposed on the first sub-dielectric layer 1111.

Referring to fig. 3B, a conductive particle layer 123 is disposed on the second electrode 122.

Here, the conductive particle layer 123 includes a plurality of conductive particles 1231 coated with a barrier layer 124.

Referring to fig. 3C, first, a second sub-dielectric layer 1112 is provided, and a first electrode 121 is disposed on the second sub-dielectric layer 1112.

Then, the first electrode 121 is pressed against the second electrode 122 such that the conductive particle layer 123 is disposed between the first electrode 121 and the second electrode 122 to form the capacitor 12.

Referring to fig. 3D, dielectric materials and conductive traces are provided to form the redistribution layer 11.

Referring to fig. 3E, a via 24 is opened in the rewiring layer 11, and a pad 23 is provided on the rewiring layer 11, the pad 23 being electrically connected to the first electrode 121 through the via 24.

Referring now to fig. 4A, 4B, 4C, 4D, 4Ea, 4Eb, 4F, and 4G, fig. 4A, 4B, 4C, 4D, 4Ea, 4Eb, 4F, and 4G are schematic longitudinal cross-sectional structural views of

semiconductor packages

400A, 400B, 400C, 400D, 400E, 400F, and 400G, and schematic top view structural views of semiconductor packages 400E, fabricated at various stages according to one embodiment of the present disclosure. The figures have been simplified in order to facilitate a better understanding of aspects of the present disclosure.

Referring to fig. 4A, a second dielectric layer 112 is provided.

Referring to fig. 4B, a second through hole 22 is formed in the second dielectric layer 112, and a sidewall of the second dielectric layer 112 is exposed through the second through hole 22.

Referring to fig. 4C, a metal layer 25 is disposed, and the metal layer 25 encapsulates the upper and lower surfaces of the second dielectric layer 112 and the sidewalls of the second via hole 22.

Referring to fig. 4D, the second via hole 22 is filled with a conductive particle layer 123.

Referring to fig. 4Ea and 4Eb, a portion of the metal layer 25 is removed such that both sides of the sidewall of the second via hole 22 form a first electrode 121 and a second electrode 122, respectively, and a conductive particle layer 123 is disposed between the first electrode 121 and the second electrode 122 to form the capacitor 12.

Referring to fig. 4F, first, a dielectric material and conductive traces are provided to form the rewiring layer 11.

Then, an electrical connector 15 is provided under the rewiring layer 11, and the electrical connector 15 is electrically connected to the rewiring layer 11.

Here, the electrical connection 15 may be disposed under the rewiring layer 11 using flip chip bonding (Controlled Collapsed Chip Connection, C4).

Referring to fig. 4G, first, the first electronic component 13 and the second electronic component 14 are provided.

Then, the first electronic component 13 and the second electronic component 14 are adjacently disposed on the rewiring layer 11. The first electronic component 13 and the second electronic component 14 may be electrically connected to the capacitor 12 through the communication structure of the redistribution layer 11.

Flip chip bonding (Flip Chip Bonding, FCB), thermocompression bonding (Thermal Compression Bonding, TCB) or similar techniques may be used in the electrical connection process.

The method for manufacturing a semiconductor structure provided by the present disclosure can achieve similar technical effects as the aforementioned semiconductor structure, and is not described herein again.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, the description and illustration is not intended to limit the disclosure. It will be apparent to those skilled in the art that various changes may be made and equivalents substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in the present disclosure due to variables in the manufacturing process, etc. There may be other embodiments of the disclosure not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications fall within the scope of this appended claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present disclosure.

Claims

1. A semiconductor package apparatus comprising:

2. The device of claim 1, wherein the conductive particle layer comprises a plurality of conductive particles surrounded by a barrier layer, and wherein adjacent conductive particles are electrically coupled to form a capacitance.

3. The apparatus of claim 2, wherein the capacitor is a non-polar capacitor.

4. The apparatus of claim 2, wherein the redistribution layer has a plurality of capacitors arranged in a matrix.

5. The apparatus of claim 4, wherein at least two of the plurality of capacitors are electrically connected.

6. The apparatus of claim 4, wherein the redistribution layer comprises a first dielectric layer;

7. The apparatus of claim 4, wherein the re-routing layer comprises a second dielectric layer;

8. The apparatus of claim 6 or 7, wherein the apparatus further comprises:

9. The device of claim 2, wherein the barrier layer is an insulating material.

10. The apparatus of claim 8, wherein the apparatus further comprises: