CN116313765A - Manufacturing method of SGT MOS device gate polysilicon structure - Google Patents
Manufacturing method of SGT MOS device gate polysilicon structure Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 169
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 156
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 173
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000002344 surface layer Substances 0.000 claims abstract description 13
- 238000005498 polishing Methods 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 230000002378 acidificating effect Effects 0.000 claims description 3
- 238000012876 topography Methods 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000000243 solution Substances 0.000 description 4
- 238000000227 grinding Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a SGT MOS device gate polysilicon structure. The manufacturing method comprises the following steps: providing a semiconductor substrate layer; depositing polysilicon, namely covering an oxide layer on the upper surface of the semiconductor substrate layer and the inner surface of the deep groove on the basis of the upper end shape of the semiconductor substrate layer until the polysilicon covered on the inner surface of the second groove is filled with the second groove to form a polysilicon structure; etching to remove the polysilicon on the back of the semiconductor substrate layer; carrying out chemical mechanical polishing on the polysilicon structure, and polishing off the surface layer of the polysilicon structure until the upper surface of the remaining polysilicon structure is smooth and flat, and the remaining polysilicon structure fills the second groove and covers the oxide layer positioned on the upper surface of the semiconductor substrate layer; and wet etching is carried out on the residual polysilicon layer, polysilicon covering the oxide layer on the upper surface of the semiconductor substrate layer in the residual polysilicon layer is removed, and a gate polysilicon structure is formed in the second groove.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a SGT MOS device gate polysilicon structure.
Background
The shielded gate trench MOS device, which is a representative of a medium voltage MOS device, is widely used as a switching device in a motor driving system, an inverter system, a power management system, and the like, and is a core power control component.
The shield gate trench MOS device in the related art includes a deep trench, a first trench, and a second trench. The first groove is formed at the lower part of the deep groove, polysilicon is filled in the first groove, the second groove is formed at the upper part of the deep groove, and polysilicon is filled in the second groove. The deep groove, the first groove and the second groove are mutually isolated through an oxide layer.
Related art generally, a SGT (Shield Gate Trench, shielded gate trench) MOS device gate polysilicon structure is fabricated in a furnace, that is, a monosilane gas is introduced into the furnace to crack the monosilane gas into polysilicon and adhere to the surface of the device with the second trench, so as to gradually fill the second trench, and then the polysilicon outside the second trench is removed by chemical mechanical polishing.
In the related process, when the gate polysilicon structure is manufactured, an over-grinding method is generally adopted to ensure that polysilicon does not remain outside the second trench. However, the over-grinding method also causes a problem that part of the gate oxide layer is removed and the thickness uniformity is poor. Particularly, the gate oxide layer at the top angle of the second trench is more prone to the problem that the second leakage current of the device is large and discrete due to the fact that the gate oxide layer is too thin.
Disclosure of Invention
The application provides a manufacturing method of a SGT MOS device gate polysilicon structure, which can solve the problems that in the related art, the uniformity of a gate oxide layer is poor, and the reverse second leakage of a device is large and discrete due to over-thinness easily occurs.
In order to solve the technical problems described in the background art, the present application provides a method for manufacturing a SGT MOS device gate polysilicon structure, the method for manufacturing a SGT MOS device gate polysilicon structure includes the following steps:
providing a semiconductor substrate layer; the semiconductor substrate layer is internally provided with a deep groove, a first groove positioned at the lower part and a second groove positioned at the upper part are formed in the deep groove, the first groove and the second groove are mutually isolated through an oxide layer, the oxide layer extends from the deep groove and covers the upper surface of the semiconductor substrate layer, the first groove is filled with first polysilicon, and the upper end of the second groove is opened;
depositing polysilicon, namely covering an oxide layer on the upper surface of the semiconductor substrate layer and the inner surface of the deep trench on the basis of the appearance of the upper end of the semiconductor substrate layer until the polysilicon covered on the inner surface of the second trench fills the second trench to form a polysilicon structure;
etching to remove the polysilicon on the back of the semiconductor substrate layer;
carrying out chemical mechanical polishing on the polysilicon structure, and polishing off the surface layer of the polysilicon structure until the upper surface of the remaining polysilicon structure is smooth and flat, and the remaining polysilicon structure fills the second groove and covers the oxide layer positioned on the upper surface of the semiconductor substrate layer;
and carrying out wet etching on the residual polysilicon layer by taking the oxide layer as an etching stop layer, removing polysilicon which is covered on the oxide layer on the upper surface of the semiconductor substrate layer in the residual polysilicon layer, and forming the gate polysilicon structure in the second groove.
Optionally, the step of depositing polysilicon so that polysilicon covers the upper surface of the semiconductor substrate layer and the inner surface of the deep trench based on the upper end morphology of the semiconductor substrate layer until the polysilicon covering the inner surface of the deep trench fills the deep trench to form a polysilicon structure includes:
and in the furnace tube, introducing SiH4 gas into the furnace tube at the temperature of 500-600 ℃ for 9-12 hours to deposit polysilicon, so that the polysilicon is covered on the upper surface of the semiconductor substrate layer and the inner surface of the deep groove based on the upper end morphology of the semiconductor substrate layer until the polysilicon covered on the inner surface of the deep groove fills the deep groove to form a polysilicon structure.
Optionally, the step of performing chemical mechanical polishing on the polysilicon structure to polish away the surface layer of the polysilicon structure until the upper surface of the remaining polysilicon structure is smooth and flat, and the remaining polysilicon structure fills the deep trench and covers the oxide layer on the upper surface of the semiconductor substrate layer, wherein the thickness of the remaining polysilicon structure covering the oxide layer on the upper surface of the semiconductor substrate layer is 400 to 600 angstroms.
Optionally, the step of performing wet etching on the remaining polysilicon layer with the oxide layer as an etching stop layer to remove polysilicon covering the oxide layer on the upper surface of the semiconductor substrate layer in the remaining polysilicon layer, and the step of forming the gate polysilicon structure in the second trench includes:
and carrying out wet etching on the residual polysilicon layer by taking the oxide layer as an etching stop layer through acid etching liquid, removing polysilicon which covers the oxide layer on the upper surface of the semiconductor substrate layer in the residual polysilicon layer, and forming the gate polysilicon structure in the second groove.
Optionally, the acidic etching solution comprises hydrofluoric acid, nitric acid or a mixed solution of hydrofluoric acid and nitric acid.
Optionally, wet etching is performed on the remaining polysilicon layer by using the oxide layer as an etching stop layer, polysilicon covering the oxide layer on the upper surface of the semiconductor substrate layer in the remaining polysilicon layer is removed, and after the step of forming the gate polysilicon structure in the second trench is completed, the height of the upper surface of the gate polysilicon structure lower than the semiconductor substrate layer is 800 angstrom to 1000 angstrom.
Optionally, the polysilicon is deposited so that the polysilicon is based on the upper end appearance of the semiconductor substrate layer, and covers the oxide layer on the upper surface of the semiconductor substrate layer and the inner surface of the deep trench until the polysilicon covering the inner surface of the second trench fills the second trench to form a polysilicon structure, wherein the thickness of the polysilicon layer covering the oxide layer on the upper surface of the semiconductor substrate layer is 3500-4500 angstroms.
The technical scheme of the application at least comprises the following advantages: the method and the device can protect the top angle of the oxide layer, and avoid the problem that the reverse second electric leakage of the device is large and discrete because the top angle of the oxide layer is ground and thinned.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for fabricating a gate polysilicon structure of an SGT MOS device according to an embodiment of the present application;
fig. 2 shows a schematic cross-sectional structure of the device after completion of step S110;
fig. 3 shows a schematic cross-sectional structure of the device after completion of step S120;
fig. 4 shows a schematic cross-sectional structure of the device after completion of step S140;
fig. 5 shows a schematic cross-sectional structure of the device formed after completion of step S150.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Fig. 1 is a flowchart of a method for fabricating a gate polysilicon structure of an SGT MOS device according to an embodiment of the present application, and as can be seen from fig. 1, the method for fabricating a gate polysilicon structure of an SGT MOS device includes the following steps S110 to S150, which are sequentially performed.
Wherein, step S110: providing a semiconductor substrate layer; the semiconductor substrate layer is internally provided with a deep groove, a first groove positioned at the lower part and a second groove positioned at the upper part are formed in the deep groove, the first groove and the second groove are mutually isolated through an oxide layer, the oxide layer extends from the deep groove and covers the upper surface of the semiconductor substrate layer, the first groove is filled with first polysilicon, and the upper end of the second groove is opened.
Referring to fig. 2, which shows a schematic cross-sectional structure of the device after completion of step S110, it can be seen from fig. 2 that a deep trench 310 is formed in the provided semiconductor substrate layer 300, a first trench 320 located at a lower portion of the deep trench 310 and a second trench 330 located at an upper portion of the deep trench 310 are formed in the deep trench 310, the first trench 320 and the second trench 330 are isolated from each other by an oxide layer 340, the oxide layer 340 extends from the deep trench 310 and covers an upper surface of the semiconductor substrate layer 300, the first trench 320 is filled with a first polysilicon, and an upper end of the second trench 330 is opened.
Step S120: and depositing polycrystalline silicon, namely covering an oxide layer on the upper surface of the semiconductor substrate layer and the inner surface of the second groove on the basis of the appearance of the upper end of the semiconductor substrate layer until the polycrystalline silicon covering the inner surface of the second groove fills the second groove to form a polycrystalline silicon structure.
Referring to fig. 3, which shows a schematic cross-sectional structure of the device after the completion of step S120, as can be seen from fig. 3, the polysilicon structure 400 formed after the completion of step S120 fills the second trench 330 and covers the upper surface of the semiconductor substrate layer 300. Since the polysilicon in step S120 is deposited based on the upper end topography of the semiconductor base layer 300, the surface layer of the formed polysilicon structure 400 has a concave taper angle formed at a position corresponding to the second trench 330 as shown in fig. 3. Optionally, in the step S120, a thickness w of the polysilicon layer covering the oxide layer on the upper surface of the semiconductor substrate layer is 3500 to 4500 a.
Optionally, during the step S120, siH4 gas may be introduced into the furnace tube at a temperature of 500 ℃ to 600 ℃ for 9 hours to 12 hours in the furnace tube, so as to deposit polysilicon, so that the polysilicon is covered on the upper surface of the semiconductor substrate layer and the inner surface of the deep trench based on the upper end morphology of the semiconductor substrate layer until the polysilicon covered on the inner surface of the deep trench fills the deep trench to form a polysilicon structure.
Step S130: and etching to remove the polysilicon on the back of the semiconductor substrate layer.
In the step S120, the polysilicon is covered on the back surface of the semiconductor substrate layer 300 in addition to the front surface of the semiconductor substrate layer 300 shown in fig. 3, and the polysilicon covered on the back surface of the semiconductor substrate layer 300 needs to be etched and removed in the step S130 of the present embodiment.
Step S140: and carrying out chemical mechanical polishing on the polycrystalline silicon structure, and polishing off the surface layer of the polycrystalline silicon structure until the upper surface of the residual polycrystalline silicon structure is smooth and flat, and the residual polycrystalline silicon structure fills the second groove and covers the oxide layer positioned on the upper surface of the semiconductor substrate layer.
Referring to fig. 4, which is a schematic cross-sectional view of the device after completion of step S140, it can be seen in conjunction with fig. 3 and 4 that the concave sharp corners on the surface layer of the polysilicon structure 400 are polished away when the surface layer of the polysilicon structure 400 is polished away, so that the upper surface of the remaining polysilicon structure 500 is smooth and flat, and the remaining polysilicon structure 500 covers the oxide layer 340 on the upper surface of the semiconductor substrate layer 300 in addition to filling the second trench 300.
The concave sharp corners on the surface layer of the polysilicon structure 400 are polished away by polishing away the surface layer of the polysilicon structure 400, thereby avoiding the subsequent wet etching step from amplifying the concave sharp corners into the gate polysilicon structure.
Optionally, the remaining polysilicon structure 500 covers the oxide layer 340 on the upper surface of the semiconductor substrate layer 300 to a thickness d of 400 a to 600 a. Illustratively, the thickness d of the remaining polysilicon structure 500 overlying the upper surface oxide layer 340 of the semiconductor substrate layer 300 is 500 angstroms.
Step S150: and carrying out wet etching on the residual polysilicon layer by taking the oxide layer as an etching stop layer, removing polysilicon which is covered on the oxide layer on the upper surface of the semiconductor substrate layer in the residual polysilicon layer, and forming the gate polysilicon structure in the second groove.
Optionally, wet etching is performed on the remaining polysilicon layer by using an acidic etching solution, such as hydrofluoric acid, nitric acid, or a mixed solution of hydrofluoric acid and nitric acid, with the oxide layer as an etching stop layer, so as to remove polysilicon in the remaining polysilicon layer, which covers the oxide layer on the upper surface of the semiconductor substrate layer, and the gate polysilicon structure is formed in the second trench.
Referring to fig. 5, which is a schematic cross-sectional structure of a device formed after the completion of step S150, it can be seen from fig. 5 that the etching solution is used to remove the polysilicon in the remaining polysilicon layer 500 in fig. 4 that covers the oxide layer 340 on the upper surface of the semiconductor substrate layer 300, so that the gate polysilicon structure 600 formed after the completion of step S150 is located only in the second trench 330. Optionally, the height h of the upper surface of the gate polysilicon structure 600 below the semiconductor substrate layer 300 is 800 to 1000 angstroms.
The surface layer of the polycrystalline silicon structure is ground, so that the sunken sharp corners on the surface layer of the polycrystalline silicon structure are ground, the residual polycrystalline silicon structure is filled in the second groove and covers the oxide layer on the upper surface of the semiconductor substrate layer, the top angle of the oxide layer can be protected, the top angle is prevented from being ground and thinned, then the oxide layer is used as an etching stop layer to carry out wet etching on the residual polycrystalline silicon layer, and the polycrystalline silicon on the oxide layer on the upper surface of the semiconductor substrate layer is removed, so that the grid polycrystalline silicon structure is finally formed.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (7)
1. The manufacturing method of the SGT MOS device gate polysilicon structure is characterized by comprising the following steps of:
providing a semiconductor substrate layer; the semiconductor substrate layer is internally provided with a deep groove, a first groove positioned at the lower part and a second groove positioned at the upper part are formed in the deep groove, the first groove and the second groove are mutually isolated through an oxide layer, the oxide layer extends from the deep groove and covers the upper surface of the semiconductor substrate layer, the first groove is filled with first polysilicon, and the upper end of the second groove is opened;
depositing polysilicon, namely covering an oxide layer on the upper surface of the semiconductor substrate layer and the inner surface of the deep trench on the basis of the appearance of the upper end of the semiconductor substrate layer until the polysilicon covered on the inner surface of the second trench fills the second trench to form a polysilicon structure;
etching to remove the polysilicon on the back of the semiconductor substrate layer;
carrying out chemical mechanical polishing on the polysilicon structure, and polishing off the surface layer of the polysilicon structure until the upper surface of the remaining polysilicon structure is smooth and flat, and the remaining polysilicon structure fills the second groove and covers the oxide layer positioned on the upper surface of the semiconductor substrate layer;
and carrying out wet etching on the residual polysilicon layer by taking the oxide layer as an etching stop layer, removing polysilicon which is covered on the oxide layer on the upper surface of the semiconductor substrate layer in the residual polysilicon layer, and forming the gate polysilicon structure in the second groove.
2. The method of forming a SGT MOS device gate polysilicon structure of claim 1, wherein the depositing polysilicon such that polysilicon covers the upper surface of the semiconductor substrate layer and the inner surface of the deep trench based on the upper topography of the semiconductor substrate layer until polysilicon covering the inner surface of the deep trench fills the deep trench to form a polysilicon structure comprises:
and in the furnace tube, introducing SiH4 gas into the furnace tube at the temperature of 500-600 ℃ for 9-12 hours to deposit polysilicon, so that the polysilicon is covered on the upper surface of the semiconductor substrate layer and the inner surface of the deep groove based on the upper end morphology of the semiconductor substrate layer until the polysilicon covered on the inner surface of the deep groove fills the deep groove to form a polysilicon structure.
3. The method of claim 1, wherein the step of performing chemical mechanical polishing on the polysilicon structure to polish away the surface layer of the polysilicon structure until the upper surface of the remaining polysilicon structure is smooth and flat, and the remaining polysilicon structure fills the deep trench and covers the oxide layer on the upper surface of the semiconductor substrate layer, wherein the thickness of the remaining polysilicon structure covering the oxide layer on the upper surface of the semiconductor substrate layer is 400 to 600 angstroms.
4. The method for fabricating the gate polysilicon structure of the SGT MOS device of claim 1, wherein the step of forming the gate polysilicon structure in the second trench by wet etching the remaining polysilicon layer using the oxide layer as an etch stop layer to remove polysilicon in the remaining polysilicon layer overlying the oxide layer on the upper surface of the semiconductor substrate layer comprises:
and carrying out wet etching on the residual polysilicon layer by taking the oxide layer as an etching stop layer through acid etching liquid, removing polysilicon which covers the oxide layer on the upper surface of the semiconductor substrate layer in the residual polysilicon layer, and forming the gate polysilicon structure in the second groove.
5. The method of claim 4, wherein the acidic etching solution comprises hydrofluoric acid, nitric acid, or a mixture of hydrofluoric acid and nitric acid.
6. The method of fabricating a SGT MOS device gate polysilicon structure of claim 1 wherein, after the step of forming the gate polysilicon structure in the second trench is completed, the remaining polysilicon layer is wet etched using the oxide layer as an etch stop layer to remove polysilicon in the remaining polysilicon layer overlying the oxide layer on the upper surface of the semiconductor substrate layer, the upper surface of the gate polysilicon structure being between 800 a and 1000 a below the height of the semiconductor substrate layer.
7. The method of forming a SGT MOS device gate polysilicon structure of claim 1, wherein the polysilicon is deposited such that the polysilicon is based on the topography of the upper end of the semiconductor substrate layer, covering the oxide layer on the upper surface of the semiconductor substrate layer and the inner surface of the deep trench, until the polysilicon covering the inner surface of the second trench fills the second trench to form the polysilicon structure, wherein the thickness of the polysilicon layer covering the oxide layer on the upper surface of the semiconductor substrate layer is 3500 a to 4500 a.
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