CN116312409A - Display panel and display terminal - Google Patents
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- CN116312409A CN116312409A CN202310244012.8A CN202310244012A CN116312409A CN 116312409 A CN116312409 A CN 116312409A CN 202310244012 A CN202310244012 A CN 202310244012A CN 116312409 A CN116312409 A CN 116312409A
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- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 7
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
- G09G2330/045—Protection against panel overheating
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the application discloses a display panel, which comprises a scanning driving circuit and a plurality of pixel units, wherein the scanning driving circuit is used for driving the pixel units to execute image display. The scanning driving circuit comprises a voltage regulating module and a shifting scanning module, wherein the voltage regulating module is used for outputting a driving clock signal to the shifting scanning module so as to control the shifting scanning module to output a scanning signal. The voltage regulating module is also used for detecting the current of the driving clock signal, and when the current of the driving clock signal is larger than a first threshold value and smaller than a second threshold value, the voltage regulating module controls the current of the driving clock signal to be maintained in a preset range; when the current of the driving clock signal is greater than or equal to the second threshold value, the voltage regulating module stops outputting the driving clock signal to the shift scanning module. The damage of components can be effectively prevented by detecting the clock signal and controlling the current in a preset range or stopping outputting the clock signal according to the detection result. The embodiment of the application also discloses a display terminal comprising the display panel.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display terminal.
Background
Liquid crystal displays (Liquid Crystal Display, LCDs) have been widely used in electronic devices such as computers, cell phones, and televisions. When the liquid crystal display displays images, the time sequence control circuit needs to output a large amount of clock signals to the scanning driving circuit and the data driving circuit so as to control the pixel units in the panel to display the images, and in the process of outputting the clock signals, the circuit for transmitting the clock signals is heated due to overlarge current pumping during the operation of the pixel units in the display panel, so that the driving circuit and components in the display panel are damaged.
Therefore, how to control the current of the clock signal and prevent the excessive current from damaging the components in the panel is a need to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application provides a display panel and a display terminal that effectively control the magnitude of a clock signal current.
A display panel comprises a scanning driving circuit, a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of pixel units arranged in an array, wherein the scanning driving circuit is used for outputting scanning signals to the pixel units through the scanning lines so as to control the pixel units to receive data signals for image display to execute image display. The scanning driving circuit comprises a voltage regulating module and a shifting scanning module, wherein the voltage regulating module is used for outputting a driving clock signal to the shifting scanning module so as to control the shifting scanning module to output a scanning signal. The voltage regulating module is also used for detecting the current of the driving clock signal, and when the current of the driving clock signal is larger than a first threshold value and smaller than a second threshold value, the voltage regulating module controls the current of the driving clock signal to be maintained in a preset range; when the current of the driving clock signal is greater than or equal to the second threshold value, the voltage regulating module stops outputting the driving clock signal to the shift scanning module.
Optionally, the voltage regulating module includes a control unit and a potential lifting unit, the control unit is electrically connected to the potential lifting unit, the control unit is used for converting the received initial clock signal into a plurality of shift clock signals with different phases and transmitting the shift clock signals to the potential lifting unit, and the potential lifting unit is used for adjusting the received shift clock signals into driving clock signals and transmitting the driving clock signals to the shift scanning module.
Optionally, the potential boosting unit includes a plurality of amplifiers, each of the plurality of amplifiers is connected to the control unit, and is configured to sequentially receive a plurality of shift clock signals from the control unit, and boost the shift clock signals into the driving clock signals.
Optionally, the voltage regulating module further includes a current limiting protection unit, and the current limiting protection unit is electrically connected to the control unit and the potential lifting unit, and is configured to receive the driving clock signal from the potential lifting unit, and simultaneously receive the control signal from the control unit and adjust the internal resistance within a preset range according to the control signal, so as to control the current of the driving clock signal within the preset range.
Optionally, the current limiting protection unit includes a plurality of adjustable resistors, the adjustable resistors are respectively and electrically connected to the plurality of amplifiers according to a one-to-one correspondence manner, and are used for respectively receiving driving clock signals from the amplifiers and transmitting the driving clock signals to the shift scanning module, and meanwhile, the adjustable resistors are electrically connected to the control unit, and are used for receiving control signals from the control unit and adjusting internal resistors according to the control signals.
Optionally, the voltage regulating module further includes a detection protection unit, the detection protection unit is electrically connected to the control unit and the current limiting protection unit, the detection protection unit is used for detecting a current of the driving clock signal, when the current of the driving clock signal is greater than a first threshold value and less than a second threshold value, the detection protection unit outputs a first detection signal to the control unit, and the control unit adjusts the resistance of the current limiting protection unit according to the first detection signal.
Optionally, when the detecting protection unit detects that the current of the driving clock signal is greater than or equal to the second threshold, the detecting protection unit outputs a second detection signal to the control unit to control the control unit to stop outputting the shift clock signal.
Optionally, the display panel further includes a current limiting circuit, and the current limiting circuit is electrically connected to the voltage regulating module and the shift scanning module, and is configured to receive the driving clock signal from the voltage regulating module, and limit a current of the driving clock signal to be in a preset range.
Optionally, the current limiting circuit includes a plurality of resistors having a preset resistance value, and the plurality of resistors are electrically connected to the shift scanning module and are respectively electrically connected to the plurality of adjustable resistors in a one-to-one correspondence manner, and are used for limiting the driving clock signal to a preset range and then transmitting the driving clock signal to the shift scanning module.
The embodiment of the application also discloses a display terminal, which comprises a backlight module, a power supply module and the display panel, wherein the backlight module is used for providing light for image display for the display panel, and the power supply module is used for providing power supply signals for driving for the backlight module and the display panel.
Compared with the prior art, the voltage regulating module detects the current of the driving clock signal and controls the output condition of the driving clock signal according to the current of the driving clock signal, so that the problems of line heating, panel damage and the like caused by overlarge current pumping of the driving clock signal can be effectively prevented.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic side view of a display terminal according to a first embodiment of the present application;
FIG. 2 is a schematic plan layout of the display panel shown in FIG. 1;
FIG. 3 is a block diagram of the voltage regulation module of FIG. 2;
FIG. 4 is a schematic diagram of an equivalent circuit of the level shifter in FIG. 3;
fig. 5 is a schematic diagram of connection of the scan driving circuit in fig. 2.
Reference numerals illustrate: the display device comprises a display terminal-1, a display panel-10, a backlight module-20, a display area-10 a, a non-display area-10 b, an array substrate-10 c, a liquid crystal layer-10 e, a color film substrate-10 d, a time sequence control circuit-11, a data driving circuit-12, a scanning driving circuit-13, a current limiting circuit-14, a voltage regulating module-131, a shift scanning module-132, a pixel unit-P, a first direction-F1, a second direction-F2, a scanning line-G, a data line-S, a horizontal synchronizing signal-Hsyn, a vertical synchronizing signal-Vsyn, a grid output control signal-Cg, a source output control signal-Cs, a clock signal-CLK, a control unit-1311, a potential lifting unit-1312, a current limiting protection unit-1313, a detection protection unit-1314, an amplifier-OP, an adjustable resistor-RP and a resistor-R.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.
Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic side view of a display terminal 1 according to a first embodiment of the present application. As shown in fig. 1, the display terminal 1 includes a display panel 10 and a backlight module 20 (Back light Module, BM), wherein the backlight module 20 is used for providing light for display to the display panel 10.
The display terminal 1 further comprises other components (not shown), which may be a power module, a signal processor module, a signal sensing module, etc. For example, the power module is used for providing power voltage for the display panel 10 and the backlight module 20.
The display panel 10 includes a display region 10a for images and a non-display region 10b. The display area 10a is used for performing image display, and the non-display area 10b is disposed around the display area 10a to provide other auxiliary components or modules. Specifically, the display panel 10 includes an Array Substrate (AS) 10c, a color film substrate (Color film substrate, CF) 10d, and a liquid crystal layer 10e interposed between the Array substrate 10c and the color film substrate 10 d. The array substrate 10c and the color film substrate 10d are provided with driving elements for generating corresponding electric fields according to the Data signals (Data), so as to drive the rotation angles of the liquid crystal molecules in the liquid crystal layer 10e to emit light rays with corresponding brightness, and image display is performed.
Referring to fig. 2, fig. 2 is a schematic plan layout of the display panel 10 shown in fig. 1. As shown in fig. 2, the array substrate 10c includes a plurality of m×n Pixel units (pixels) P, m Data lines (Data lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn arranged in a matrix, where m and n are natural numbers greater than 1.
The plurality of data lines S1 to Sm are insulated from each other by a first predetermined distance along the second direction F2 and are arranged in parallel, the plurality of scan lines G1 to Gn are also insulated from each other by a second predetermined distance along the first direction F1 and are arranged in parallel, and the plurality of scan lines G1 to Gn are insulated from the plurality of light-emitting data lines S1 to Sm, wherein the first direction F1 and the second direction F2 are perpendicular to each other.
The display terminal 1 further includes a timing control circuit 11, a Data driving circuit (Data Driver) 12, and a Scan driving circuit (Scan Driver) 15 for driving the pixel units to display an image, which correspond to the non-display region 10b of the display panel 10, disposed on the array substrate 10c.
The data driving circuit 12 is electrically connected to the plurality of data lines S1 to Sm, and is configured to transmit the image data to be displayed to the plurality of pixel units P in the form of data voltages through the plurality of data lines S1 to Sm.
The scan driving circuit 13 is electrically connected to the plurality of scan lines G1 to Gn, and is configured to output a scan signal Gn through the plurality of scan lines G1 to Gn for controlling when the pixel unit P receives image data. The scan driving circuit 13 sequentially outputs scan signals from the plurality of scan lines G1 to Gn in the position arrangement order from the scan lines G1, G2, … …, gn in the scan period.
The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used for controlling the operation timings of the data driving circuit 12 and the scan driving circuit 13, that is, outputting corresponding timing control signals to the data driving circuit 12 and the scan driving circuit 13 so as to control when to output corresponding scan signals Gn and image data.
In the present embodiment, the circuit elements in the scan driving circuit 13 and the pixel units P in the display panel 10 are fabricated in the same process in the display panel 10, i.e. GOA (Gate Driver on Array) technology.
It can be understood that the display terminal 1 further includes other auxiliary circuits for jointly completing the display of the image, such as an image receiving processing circuit (Graphics Processing Unit, GPU), a power circuit, etc., which will not be described in detail in this embodiment.
Specifically, the timing control circuit 11 receives an image signal Dv representing image information, a horizontal synchronization signal Hsyn and a vertical synchronization signal Vsyn for synchronization from an external signal source, and outputs a gate output control signal Cg and an initial clock signal for controlling the scan driving circuit 13, a source output control signal Cs for controlling the data driving circuit 12, and an original data signal representing image information.
The scan driving circuit 13 receives the gate output control signal Cg and the original clock signal outputted from the timing control circuit 11, and outputs scan signals to the respective scan lines G1 to Gn. The data driving circuit 12 receives the source output control signal Cs output from the timing control circuit 11, and outputs data signals for performing image display to the driving elements in the respective pixel units P in the display area 10a to the respective data lines S1 to Sm. Wherein the data signal provided to the display panel 10 is a gray scale voltage in analog form. The scan driving circuit 13 outputs a scan signal to control the pixel unit P to receive the data signal output from the data driving circuit 12, so as to control the pixel unit P to display a corresponding image.
The scan driving circuit 13 includes a voltage regulating module 131 and a shift scanning module 132, wherein the voltage regulating module 131 is configured to receive an initial clock signal from the timing control circuit 11, adjust a potential of the initial clock signal CLK to a preset potential, and output a driving clock signal to the shift scanning module 132, and the shift scanning module 132 outputs a scanning signal to the pixel unit according to the driving clock signal to control the pixel unit to receive a data signal for image display. The voltage regulating module 131 is further configured to detect a current of the driving clock signal, when the current of the driving clock signal is detected to be greater than the first threshold and less than the second threshold, the voltage regulating module 131 controls the current of the driving clock signal to be maintained within a preset range, and when the current of the driving clock signal is detected to be greater than or equal to the second threshold, the voltage regulating module 131 stops outputting the driving clock signal, so as to prevent components damaged by overlarge current.
Referring to fig. 3, fig. 3 is a block diagram of the voltage regulating module in fig. 2.
As shown in fig. 3, the voltage regulating module 131 includes a control unit 1311 and a potential lifting unit 1312, the control unit 1311 is electrically connected to the potential lifting unit 1312, the control unit 1311 is configured to convert a received initial clock signal into a plurality of shift clock signals with different phases and transmit the shift clock signals to the potential lifting unit 1312, the potential lifting unit 1312 is configured to adjust the received shift clock signals into a driving clock signal CLK and transmit the driving clock signal CLK to the shift scanning module 132, and the shift scanning module 132 outputs a scanning signal according to the driving clock signal CLK to control pixel units at corresponding positions to receive data signals for image display.
The voltage regulation module 131 further includes a current limiting protection unit 1313, where the current limiting protection unit 1313 is electrically connected to the control unit 1311 and the potential lifting unit 1312, and is configured to receive the driving clock signal CLK from the potential lifting unit 1312, and simultaneously receive a control signal from the control unit 1311 and adjust an internal resistance according to the control signal, so as to control a current of the driving clock signal CLK to be maintained in a preset range.
Specifically, the control unit 1311 is configured to receive an initial clock signal from the timing control circuit 11, convert the initial clock signal into a plurality of shift clock signals with different phases, and transmit the shift clock signals to the potential boosting unit 1312, and the potential boosting unit 1312 is configured to adjust the received shift clock signal to a driving clock signal CLK, i.e. boost the potential of the shift clock signal to a preset potential, and transmit the driving clock signal CLK to the current limiting protection unit 1313, and transmit the driving clock signal CLK to the scan driving circuit 13 through the current limiting protection unit 1313.
The voltage regulating module 131 further includes a detecting and protecting unit 1314, the detecting and protecting unit 1314 is electrically connected to the control unit 1311 and the current limiting and protecting unit 1313, the detecting and protecting unit 1314 is configured to detect a current of the driving clock signal CLK, and when the detecting and protecting unit 1314 detects that the current of the driving clock signal CLK is greater than a first threshold value or less than a second threshold value, the detecting and protecting unit 1314 outputs a first detecting signal to the control unit 1311, the control unit 1311 adjusts a resistance of the current limiting and protecting unit 1313 according to the first detecting signal, and reduces the current of the driving clock signal CLK to a preset range by adjusting a resistance value of the current limiting and protecting unit 1313.
When the detection protection unit 1314 detects that the current of the driving clock signal CLK is greater than the second threshold, the detection protection unit 1314 immediately performs current protection on the voltage regulation module 131, and the detection protection unit 1314 outputs the second detection signal value control unit 1311, so that the control unit 1311 stops receiving the initial clock signal from the timing control circuit 11 and stops outputting the shift clock signal to the potential boosting unit 1312. Thereby blocking or stopping the current flow of the clock signal to prevent the large current from damaging the components.
When the detecting protection unit 1314 detects that the current of the clock signal CLK has a tendency to gradually increase or is greater than the first threshold, the control unit 1311 outputs a control signal to the current limiting protection unit 1313 for adjusting the resistance value of the current limiting protection unit 1313, and when the detecting protection unit 1314 detects that the current of the clock signal CLK has a tendency to suddenly increase in a shorter time and is greater than the second threshold, the detecting protection unit 1314 performs current protection to shut off or stop the output of the driving clock signal CLK so as to prevent the large current from damaging the components in the display panel 10.
Referring to fig. 4, fig. 4 is an equivalent circuit schematic diagram of the level shifter in fig. 3.
As shown in fig. 4, the potential boosting unit includes a plurality of amplifiers OP, which are respectively a first amplifier OP1 to an n-th amplifier OPn, wherein the plurality of amplifiers OP respectively receive the shift clock signal from the control unit 1311, and adjust the received shift clock signal to a driving clock signal CLK and output the driving clock signal CLK to the current limiting protection unit 1313, wherein the process of adjusting the shift clock signal to the driving clock signal CLK is to adjust the shift clock signal of the first potential to a preset potential, and transmit the clock signal of the preset potential as the driving clock signal CLK to the current limiting protection unit 1313.
The current limiting protection unit 1313 includes a plurality of adjustable resistors RP, which are respectively a first adjustable resistor RP1 to an nth adjustable resistor RPn, wherein the first adjustable resistor RP1 to the nth adjustable resistor RPn are respectively connected to the first amplifier OP1 to the nth amplifier OPn in a one-to-one correspondence manner, and are used for respectively receiving the driving clock signal CLK from the amplifier, and meanwhile, the first adjustable resistor RP1 to the nth adjustable resistor RPn are respectively connected to the control unit 1311, and are used for receiving the control signal from the control unit and adjusting the resistance value of the corresponding adjustable resistor RP according to the control signal, so that the current of the driving clock signal CLK is controlled to be maintained in a preset range through adjusting the resistance value.
Specifically, when the control unit 1311 receives the initial clock signal from the timing control circuit 11, the detection protection unit 1314 detects the current of the initial clock signal, when detecting that the current of the first clock signal CLK1 is lower than the first threshold value, the control unit 1311 converts the initial clock signal into a plurality of shift clock signals and transmits the shift clock signals to the potential lifting unit 1312, the potential lifting unit 1312 boosts and adjusts the received shift clock signals to a preset potential to form a driving clock signal CLK and transmits the driving clock signal CLK to the current limiting protection unit 1313, the current limiting protection unit 1313 receives the control signal output by the control unit 1311 and adjusts the internal resistance according to the control signal and transmits the received driving clock signal CLK to the shift scanning module 132, the detection protection unit 1314 detects the current of the driving clock signal CLK output by the current limiting protection unit 1313 and outputs the first detection signal or the second detection signal to the control unit 1311 according to the current level, and the control unit 1311 outputs the control signal to the current limiting protection unit 1313 according to the received first detection signal or the second detection signal.
When the current of the first driving clock signal CLK1 is detected to be greater than the first threshold and less than the second threshold, the detection protection unit 1314 outputs a first detection signal to the control unit 1311, and the control unit 1311 outputs a control signal to all the adjustable resistors RP1 to RPn according to the first detection signal, so as to adjust the resistances of all the adjustable resistors RP1 to RPn. By increasing the resistance of the adjustable resistor RP, the impedance in the transmission line of the first clock signal CLK1 is increased, and the current of the first clock signal CKL1 is controlled within a preset range.
When the detection protection unit 1314 detects that the current of the first driving clock signal CLK1 is greater than the second threshold, the detection protection unit 1314 blocks or intercepts the first driving clock signal CLK1 to control the current of the first driving clock signal CLK1 to stop outputting to other components, thereby preventing the other components from being damaged due to high current.
When the control unit 1311 receives the second driving clock signal CLK2 from the timing control circuit 11, the detection protection unit 1314 detects the current of the second driving clock signal CLK2, and when detecting that the current of the second clock signal CLK2 is lower than the first threshold, the control unit 1311 controls the resistances of all the adjustable resistors RP1 to RPn to be 0Ω, the control unit 1311 transmits the received second driving clock signal CLK2 to the second amplifier OP2, and the second amplifier OP2 amplifies the second clock signal CLK2 and then transmits the amplified second driving clock signal CLK2 to the second adjustable resistor RP2, and transmits the second driving clock signal CLK2 to the shift scan module 132 via the second adjustable resistor RP 2.
When the current of the second driving clock signal CLK2 is detected to be greater than the first threshold and less than the second threshold, and the current of the first driving clock signal CLK2 is greater than the current of the first clock signal CLK1, i.e. the clock signal CLK has a gradually increasing trend, the detection protection unit 1314 outputs a first detection signal to the control unit 1311, and the control unit 1311 outputs a control signal to all the adjustable resistors RP1 to RPn according to the first detection signal so as to adjust the resistances of all the adjustable resistors RP1 to RPn. By increasing the resistance value of the adjustable resistor RP, the impedance in the transmission line of the second driving clock signal CLK2 is increased, and the current of the second driving clock signal CKL2 is controlled within a preset range.
When the detection protection unit 1314 detects that the current of the second driving clock signal CLK2 is greater than the second threshold, the detection protection unit 1314 blocks or intercepts the second driving clock signal CLK2 to control the current of the second driving clock signal CLK2 to stop outputting to other components, thereby preventing the other components from being damaged due to high current.
Similarly, current detection is performed on a plurality of driving clock signals CLK.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating connection of the scan driving circuit in fig. 2. As shown in fig. 5, the display panel 10 further includes a current limiting circuit 14, the current limiting protection unit 1313 is electrically connected to the current limiting circuit 14, and is configured to transmit a clock signal to the current limiting circuit 14, and to transmit the clock signal to the shift scanning module 132 in the array substrate 10c through the current limiting circuit 14, and the shift scanning module 132 outputs a scanning signal according to the clock signal CLK to control the pixel unit P to perform image display.
The current limiting circuit 14 includes a plurality of resistors R, which are respectively a first resistor R1 to an nth resistor Rn, and the first resistor R1 to the nth resistor Rn are respectively electrically connected to the first adjustable resistor RP1 to the nth adjustable resistor RPn, and are configured to receive corresponding clock signals CLK from the first adjustable resistor RP1 to the nth adjustable resistor RPn and transmit the clock signals CLK to the shift scanning module 132.
Through the setting of the detection protection unit and the current-limiting protection unit, different current protection measures can be executed for clock signals with different current magnitudes, the current change of the clock signals is detected in real time, corresponding impedance is set through the current-limiting protection unit according to the current change of the clock signals, the current of the clock signals is effectively controlled in a preset range, and when the detected current of the clock signals is greater than a second threshold value, the detection protection unit controls the clock signals to stop outputting so as to block the output of large current, and the damage of components in a circuit and the burning of a display panel are prevented.
It is to be understood that the application of the present application is not limited to the examples described above, but that modifications and variations can be made by a person skilled in the art from the above description, all of which modifications and variations are intended to fall within the scope of the claims appended hereto.
Claims (10)
1. A display panel comprising a scan driving circuit and a plurality of scan lines extending in a first direction and arranged in a second direction, and a plurality of pixel units arranged in an array, the scan driving circuit being configured to output a scan signal to the pixel units through the scan lines to control the pixel units to receive a data signal for image display to perform image display;
the scanning driving circuit is characterized by comprising a voltage regulating module and a shifting scanning module, wherein the voltage regulating module is used for outputting a driving clock signal to the shifting scanning module so as to control the shifting scanning module to output the scanning signal;
the voltage regulating module is also used for detecting the current of the driving clock signal, and when the current of the driving clock signal is larger than a first threshold value and smaller than a second threshold value, the voltage regulating module controls the current of the driving clock signal to be maintained in a preset range; when the current of the driving clock signal is greater than or equal to the second threshold value, the voltage regulating module stops outputting the driving clock signal to the shift scanning module.
2. The display panel according to claim 1, wherein the voltage regulating module comprises a control unit and a potential lifting unit, the control unit is electrically connected to the potential lifting unit, the control unit is used for converting a received initial clock signal into a plurality of shift clock signals with different phases and transmitting the shift clock signals to the potential lifting unit, and the potential lifting unit is used for adjusting the received shift clock signals into the driving clock signals and transmitting the driving clock signals to the shift scanning module.
3. The display panel of claim 2, wherein,
the potential lifting unit comprises a plurality of amplifiers, wherein the amplifiers are respectively connected to the control unit and are used for respectively and sequentially receiving a plurality of shift clock signals from the control unit and boosting the shift clock signals into the driving clock signals.
4. The display panel of claim 3, wherein the voltage regulation module further comprises a current limiting protection unit electrically connected to the control unit and the potential lifting unit, for receiving the driving clock signal from the potential lifting unit, and receiving a control signal from the control unit and adjusting an internal resistance within the preset range according to the control signal, so as to control a current of the driving clock signal within the preset range.
5. The display panel according to claim 4, wherein the current limiting protection unit comprises a plurality of adjustable resistors, the adjustable resistors are respectively and electrically connected to the plurality of amplifiers in a one-to-one correspondence manner, and are used for respectively receiving the driving clock signals from the amplifiers and transmitting the driving clock signals to the shift scanning module, and the adjustable resistors are electrically connected to the control unit, and are used for receiving control signals from the control unit and adjusting internal resistance according to the control signals.
6. The display panel according to claim 5, wherein the voltage regulating module further comprises a detection protection unit electrically connected to the control unit and the current limiting protection unit, the detection protection unit is configured to detect a current of the driving clock signal, and when detecting that the current of the clock signal is greater than the first threshold and less than the second threshold, the detection protection unit outputs a first detection signal to the control unit, and the control unit adjusts the resistance of the current limiting protection unit according to the first detection signal.
7. The display panel according to claim 6, wherein the detection protection unit outputs a second detection signal to the control unit to control the control unit to stop outputting the shift clock signal when the detection protection unit detects that the current of the driving clock signal is greater than or equal to the second threshold.
8. The display panel of any one of claims 5-7, further comprising a current limiting circuit electrically connected to the voltage regulation module and the shift scan module for receiving the driving clock signal from the voltage regulation module and limiting a current of the driving clock signal to be within the predetermined range.
9. The display panel of claim 8, wherein the current limiting circuit comprises a plurality of resistors having a predetermined resistance value, and the plurality of resistors are electrically connected to the shift scan module and are respectively electrically connected to the plurality of adjustable resistors in a one-to-one correspondence manner, and are configured to limit the driving clock signal to the predetermined range and then transmit the driving clock signal to the shift scan module.
10. A display terminal, comprising a backlight module, a power module and a display panel according to any one of claims 1-9, wherein the backlight module is used for providing light for displaying images for the display panel, and the power module is used for providing power signals for driving the backlight module and the display panel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310244012.8A CN116312409A (en) | 2023-03-14 | 2023-03-14 | Display panel and display terminal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310244012.8A CN116312409A (en) | 2023-03-14 | 2023-03-14 | Display panel and display terminal |
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