CN116301272A - Server, server power-on management system and method - Google Patents

Server, server power-on management system and method Download PDF

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Publication number
CN116301272A
CN116301272A CN202310293908.5A CN202310293908A CN116301272A CN 116301272 A CN116301272 A CN 116301272A CN 202310293908 A CN202310293908 A CN 202310293908A CN 116301272 A CN116301272 A CN 116301272A
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power
module
server
field
management
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张明瑞
王培培
苏云学
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Shanghai Huayi Microelectronic Material Co Ltd
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Shanghai Huayi Microelectronic Material Co Ltd
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Priority to CN202310293908.5A priority Critical patent/CN116301272A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
    • H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • General Health & Medical Sciences (AREA)
  • Software Systems (AREA)
  • Power Sources (AREA)

Abstract

The invention discloses a server, a server power-on management system and a method, which belong to the technical field of computers, wherein the server comprises a server main board, the server main board comprises a power-on controlled area and a power-on management area, the power-on management area is provided with a power-on control FPGA, a FLASH and a power-on trigger source, and the power-on control FPGA, the FLASH and the power-on trigger source are arranged in the power-on management area, wherein the power-on control FPGA, the FLASH and the power-on trigger source are arranged in the power-on management area, and the power-on trigger source is arranged in the power-on control area. The power-on control FPGA comprises a network port communication module, an encryption and decryption module, a FLASH control module and a power-on management module, wherein the network port communication module is used for being connected with an upper computer, the encryption and decryption module is connected with the network port communication module, the FLASH control module is connected with the output end of the encryption and decryption module, and the power-on management module is connected with the output end of the FLASH control module; the FLASH control module is connected with the FLASH, and the power-on management module is connected with the controlled module and the power-on trigger source in the power-on controlled area. The invention has high flexibility, does not need to re-burn the FPGA, and can remotely manage the power-on time sequence of the server mainboard even if the mainboard is sealed in the chassis.

Description

Server, server power-on management system and method
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a server, and a system and a method for power-on management of the server.
Background
The current server motherboard is powered on, and power-on time sequence control is usually realized by setting a power supply enabling signal of each module controlled by a state machine in a CPLD (Complex Programmable Logic Device ), but the method needs to modify CPLD codes and re-write every time the time sequence is modified, which brings inconvenience to equipment debugging and use. Furthermore, when the motherboard is already installed in the server chassis, the chassis needs to be opened if the power-on sequence is to be modified. Therefore, there is an urgent need for a method that can remotely manage power-on timing of a server. Moreover, CPLD, although low cost, is far less logically resource than FPGA (Field Programmable Gate Array ).
Disclosure of Invention
The invention aims to provide a server capable of remotely managing power-on time sequence of the server, a power-on management system and a power-on management method of the server.
In order to solve the technical problems, the invention provides the following technical scheme:
in one aspect, a server is provided, including the server mainboard, the server mainboard is including the controlled region of power on and power on management area, power on management area is equipped with power on control FPGA, FLASH and power on trigger source, wherein:
the power-on control FPGA comprises a network port communication module, an encryption and decryption module, a FLASH control module and a power-on management module, wherein the network port communication module is used for being connected with an upper computer, the encryption and decryption module is connected with the network port communication module, the FLASH control module is connected with the output end of the encryption and decryption module, and the power-on management module is connected with the output end of the FLASH control module;
the FLASH control module is connected with the FLASH, and the power-on management module is connected with the controlled module in the power-on controlled area and the power-on trigger source.
Further, a power-on enabling signal connection end of the controlled module in the power-on controlled area is connected with an output end of the power-on management module;
and/or the power-on feedback signal connection end of the controlled module in the power-on controlled area is connected with the input end of the power-on management module.
Further, the output end of the power-on management module is connected with the input end of the encryption and decryption module;
and/or the power-on trigger source is a key or an external signal.
On the other hand, a server power-on management system is provided, which comprises an upper computer and the server.
In still another aspect, a method for power-on management of a server by using the power-on management system of a server is provided, including:
step 101: the server main board receives a configuration file issued by the upper computer, wherein the configuration file firstly passes through the network port communication module, then is decrypted through the encryption and decryption module, and then is written into FLASH through the FLASH control module;
step 102: when the power-on control FPGA is restarted after power-off, the FLASH control module reads out the configuration file from the FLASH and sends the configuration file to the power-on management module, and the configuration file is converted into a state machine in the power-on management module to control the power-on time sequence of a power-on controlled area of the server main board.
Further, the step 102 includes:
step 103: after the power-on management module runs, the power-on response message is encrypted by the encryption and decryption module and then uploaded to the upper computer through the network port communication module.
Further, the ethernet frame between the server motherboard and the upper computer adopts a custom frame structure, that is, a "type" field in a traditional MAC frame is changed into an "encryption selection" field, which is used to indicate whether a message in the frame is a plaintext or a ciphertext, and other fields are the same as the traditional MAC frame, including a destination address, an original address, a message and a frame check sequence FCS.
Further, the configuration message issued by the upper computer includes a 4-byte message identification code, a 2-byte message length field, a 2-byte start type field, a 2-byte module number field repeated later, a 2-byte time unit field, and a 5-byte delay value field.
Further, in the start type field, when the value is 1, the main board is set to be powered on for self-starting, and when the value is 2, the main board is set to be triggered for starting;
in the time unit field, 1 represents that the time unit corresponding to the delay value field is ns,2 represents μs,3 represents ms, and 4 represents s;
the delay value in the delay value field indicates how long the last module is delayed after completion and then the current module is enabled, and when the value is 0, the delay value and the current module are started simultaneously.
Further, in the response message uploaded to the upper computer:
a transmission response field, wherein 1 indicates that FCS errors exist, 2 indicates that message identification code errors exist, 3 indicates that the message identification code errors are normal, and when the content of the transmission response field is not 3, the upper computer needs to resend the configuration message;
and a power-on response field which indicates whether power-on management is normal or not, wherein 1 indicates normal, 2 indicates abnormal, and when the power-on response field is 1, a subsequent power-on response content field does not exist in the message, and conversely, the power-on response content field indicates which module is abnormal in power-on.
The invention has the following beneficial effects:
(1) The flexibility is high, the FPGA does not need to be re-programmed, and the power-on time sequence of the server main board can be remotely managed even if the main board is sealed in the case;
(2) The security is high, and the messages passing through the network port communication module are all encrypted and decrypted;
(3) The integration is good, and the enabling signals of all the controlled modules can be processed uniformly.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a power-on management system of a server according to the present invention;
FIG. 2 is a flow chart of a power-on management method of a server according to the present invention;
FIG. 3 is a schematic diagram of a custom MAC frame according to the present invention;
FIG. 4 is a schematic diagram of a configuration message according to the present invention;
fig. 5 is a schematic structural diagram of a response message in the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
In one aspect, as shown in fig. 1, the present invention provides a server, including a server motherboard 10, where the server motherboard 10 includes a power-on controlled area 10a and a power-on management area 10b, and the power-on management area 10b is provided with a power-on control FPGA (module) 11, a FLASH memory 12, and a power-on trigger source 13, where:
the power-on control FPGA11 comprises a network port communication module 111 connected with the upper computer 20, an encryption and decryption module 112 connected with the network port communication module 111, a FLASH control module 113 connected with the output end of the encryption and decryption module 112, and a power-on management module 114 connected with the output end of the FLASH control module 113;
the FLASH control module 113 is connected with the FLASH 12, and the power-on management module 114 is connected with the controlled module in the power-on controlled area 10a and the power-on trigger source 13.
In specific implementation, the power-on enable signal connection end of the controlled module in the power-on controlled area 10a may be connected to the output end of the power-on management module 114; the power-on feedback signal connection terminal of the controlled module in the power-on controlled area 10a may be connected to the input terminal of the power-on management module 114, so as to determine whether the module is powered on successfully. For the power-on feedback signal, the power chip may use a pg (power good) signal, and the processor chip may use a gpio (General-purpose input/output port) signal, and output a fixed level after power-on.
Further, the output end of the power management module 114 may be connected to the input end of the encryption/decryption module 112, so that the response message sent by the power management module 114 to the upper computer 20 may be encrypted, thereby improving security. The power-on trigger source 13 may be a key or an external signal.
In another aspect, the present invention provides a server power-on management system, as shown in fig. 1, including an upper computer 20 and the server described above. The structure of the server is the same as above and will not be described here again.
In still another aspect, the present invention provides a method for managing power on a server by using the above power on management system for a server, as shown in fig. 2, including:
step 101: the server main board 10 receives a configuration file issued by the upper computer 20, wherein the configuration file firstly passes through the network port communication module 111, then is decrypted through the encryption and decryption module 112, and then is written into the FLASH 12 through the FLASH control module 113;
step 102: when the power-on control FPGA11 is powered off and restarted, the FLASH control module 113 reads the configuration file from the FLASH 12 and sends the configuration file to the power-on management module 114, and converts the configuration file into a state machine in the power-on management module 114 to control the power-on timing of the power-on controlled area 10a (each controlled module) of the server motherboard 10.
Thus, the remote management of the power-on time sequence of the server can be conveniently realized through the steps 101-102.
To facilitate the host computer 20 to know the power-on condition, the step 102 may include:
step 103: after the power-on management module 114 runs, the power-on response message is encrypted by the encryption and decryption module 112 and then uploaded to the upper computer 20 through the network port communication module 111.
In the present invention, the upper computer 20 is responsible for issuing configuration messages and receiving response messages through the internet access. The ethernet frame between the server motherboard 10 and the host computer 20 may adopt a custom frame structure, as shown in fig. 3, i.e. the "type" field in the conventional MAC frame is changed to the "encryption select" field, which is used to indicate whether the message in the frame is plaintext or ciphertext, and other fields are the same as the conventional MAC frame, including the destination address, the original address, the message, and the frame check sequence FCS (Frame Check Sequence). Whether the message in the custom frame is plaintext or ciphertext, the parsed message uses the same message structure.
In the present invention, as shown in fig. 4, the configuration message issued by the upper computer 20 may include a 4-byte message identifier, a 2-byte message length field, a 2-byte start type field, a 2-byte module number field repeated later, a 2-byte time unit field, and a 5-byte delay value field. In the startup type field, when the value is 1, the main board is set to be powered on for self startup, and when the value is 2, the main board is set to be triggered for startup, and the triggering condition can include a key or other triggering signals. The module number field refers to the consensus between the upper computer and the power-on control FPGA11, and numbers the power-on enable signals of all the controlled modules of the main board that need to be managed. In the time unit field, 1 indicates that the time unit corresponding to the delay value field is ns, and correspondingly, 2 indicates μs,3 indicates ms, and 4 indicates s. The delay value in the delay value field indicates how long the last (controlled) module is delayed after completion, and the current module is enabled again, and when the value is 0, the two modules are started simultaneously.
In the present invention, as shown in fig. 5, the response message uploaded by the power-on control FPGA11 to the upper computer 20 may include a 4-byte header (message identification code), a 2-byte message length field, a 1-byte transmission response field, a 1-byte power-on response field, and a 8-byte power-on response content field repeated later (this field may be omitted). Wherein, the transmission response field, 1 indicates that there is an FCS error, 2 indicates that the message identification code is wrong, 3 indicates that it is normal, and when the content of the transmission response field is not 3, the upper computer 20 needs to resend the configuration message. A power-on response field indicates whether power-on management is running normally, 1 indicates normal, and 2 indicates abnormal. When the power-on response field is 1, the subsequent power-on response content field does not exist in the message, and conversely, the power-on response content field indicates which module is abnormal in power-on. The PADDING field in the figure is PADDING data.
In summary, the server power-on management system and the server power-on management method have the following advantages:
(1) The flexibility is high, the FPGA does not need to be re-programmed, and the power-on time sequence of the server main board can be remotely managed even if the main board is sealed in the case;
(2) The security is high, and the messages passing through the network port communication module are all encrypted and decrypted;
(3) The integration is good, and the enabling signals of all the controlled modules can be processed uniformly.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims (10)

1. The utility model provides a server, includes the server mainboard, its characterized in that, the server mainboard is including the controlled region of power on and power on management area, power on management area is equipped with power on control FPGA, FLASH and power on trigger source, wherein:
the power-on control FPGA comprises a network port communication module, an encryption and decryption module, a FLASH control module and a power-on management module, wherein the network port communication module is used for being connected with an upper computer, the encryption and decryption module is connected with the network port communication module, the FLASH control module is connected with the output end of the encryption and decryption module, and the power-on management module is connected with the output end of the FLASH control module;
the FLASH control module is connected with the FLASH, and the power-on management module is connected with the controlled module in the power-on controlled area and the power-on trigger source.
2. The server according to claim 1, wherein a power-on enable signal connection terminal of a controlled module in the power-on controlled area is connected to an output terminal of the power-on management module;
and/or the power-on feedback signal connection end of the controlled module in the power-on controlled area is connected with the input end of the power-on management module.
3. The server of claim 1, wherein an output of the power-on management module is connected to an input of the encryption and decryption module;
and/or the power-on trigger source is a key or an external signal.
4. A server power-on management system, comprising a host computer and the server of any one of claims 1-3.
5. The power-on management method for a server by a power-on management system for a server according to claim 4, comprising:
step 101: the server main board receives a configuration file issued by the upper computer, wherein the configuration file firstly passes through the network port communication module, then is decrypted through the encryption and decryption module, and then is written into FLASH through the FLASH control module;
step 102: when the power-on control FPGA is restarted after power-off, the FLASH control module reads out the configuration file from the FLASH and sends the configuration file to the power-on management module, and the configuration file is converted into a state machine in the power-on management module to control the power-on time sequence of a power-on controlled area of the server main board.
6. The method according to claim 5, wherein said step 102 is followed by:
step 103: after the power-on management module runs, the power-on response message is encrypted by the encryption and decryption module and then uploaded to the upper computer through the network port communication module.
7. The method of claim 5, wherein the ethernet frame between the server motherboard and the host computer adopts a custom frame structure, i.e., a "type" field in a conventional MAC frame is changed to an "encryption select" field, which is used to indicate whether a message in the frame is plaintext or ciphertext, and other fields are the same as the conventional MAC frame, including a destination address, a source address, a message, and a frame check sequence FCS.
8. The method of claim 7, wherein the configuration message issued by the host computer includes a 4-byte message identification code, a 2-byte message length field, a 2-byte start type field, and a 2-byte module number field, a 2-byte time unit field, and a 5-byte delay value field that are repeated thereafter.
9. The method of claim 8, wherein a1 value in the start type field indicates that the motherboard is set to a power-on self-start and a 2 value indicates that the motherboard is set to a trigger start;
in the time unit field, 1 represents that the time unit corresponding to the delay value field is ns,2 represents μs,3 represents ms, and 4 represents s;
the delay value in the delay value field indicates how long the last module is delayed after completion and then the current module is enabled, and when the value is 0, the delay value and the current module are started simultaneously.
10. The method of claim 7, wherein the response message uploaded to the host computer is:
a transmission response field, wherein 1 indicates that FCS errors exist, 2 indicates that message identification code errors exist, 3 indicates that the message identification code errors are normal, and when the content of the transmission response field is not 3, the upper computer needs to resend the configuration message;
and a power-on response field which indicates whether power-on management is normal or not, wherein 1 indicates normal, 2 indicates abnormal, and when the power-on response field is 1, a subsequent power-on response content field does not exist in the message, and conversely, the power-on response content field indicates which module is abnormal in power-on.
CN202310293908.5A 2023-03-21 2023-03-21 Server, server power-on management system and method Pending CN116301272A (en)

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CN202310293908.5A CN116301272A (en) 2023-03-21 2023-03-21 Server, server power-on management system and method

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Application Number Priority Date Filing Date Title
CN202310293908.5A CN116301272A (en) 2023-03-21 2023-03-21 Server, server power-on management system and method

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CN116301272A true CN116301272A (en) 2023-06-23

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