CN116301260A - Heat dissipation mode determining method and device, storage medium and electronic equipment - Google Patents
Heat dissipation mode determining method and device, storage medium and electronic equipment Download PDFInfo
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Abstract
A heat dissipation mode determining method, a heat dissipation mode determining device, a storage medium and electronic equipment are disclosed. The method comprises the following steps: determining the hot air risk level corresponding to each of a plurality of chips included in the circuit board; determining first target simulation heat dissipation parameters corresponding to heat dissipation bosses respectively arranged on at least part of the chips based on the hot air risk levels corresponding to the chips respectively; taking the circuit board as a simulation object, and simulating the plurality of chips based on the first target simulation heat dissipation parameters to obtain first target simulation junction temperatures corresponding to the chips respectively; and determining a target heat dissipation mode of the circuit board based on the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips. The embodiment of the disclosure can effectively and reliably distinguish whether different chips are necessary to be provided with the heat dissipation boss.
Description
Technical Field
The disclosure relates to chip technology, and in particular relates to a method and a device for determining a heat dissipation mode, a storage medium and electronic equipment.
Background
In general, the circuit board may include a plurality of chips, and as the power consumption of the chips increases, the heat dissipation of the chips may be enhanced at a lower cost by providing the chips with heat dissipation bosses. Since the excessive arrangement of the heat dissipation boss significantly increases the production cost and difficulty, it is necessary to distinguish whether different chips are necessary to arrange the heat dissipation boss.
Disclosure of Invention
The present disclosure is presented for efficient and reliable distinction of whether different chips are necessarily provided with heat dissipating bosses. The embodiment of the disclosure provides a heat dissipation mode determining method, a heat dissipation mode determining device, a storage medium and electronic equipment.
According to an aspect of the embodiments of the present disclosure, there is provided a heat dissipation manner determining method, including:
determining the hot air risk level corresponding to each of a plurality of chips included in the circuit board;
determining first target simulation heat dissipation parameters corresponding to heat dissipation bosses respectively arranged on at least part of the chips based on the hot air risk grades corresponding to the chips respectively;
taking the circuit board as a simulation object, and simulating the plurality of chips based on the first target simulation heat dissipation parameters to obtain first target simulation junction temperatures corresponding to the plurality of chips respectively;
and determining a target heat dissipation mode of the circuit board based on the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips.
According to another aspect of the embodiments of the present disclosure, there is provided a heat dissipation manner determining apparatus, including:
the first determining module is used for determining hot air risk levels corresponding to a plurality of chips included in the circuit board;
The second determining module is used for determining first target simulation heat dissipation parameters corresponding to heat dissipation bosses respectively arranged on at least part of the chips based on the hot air risk levels corresponding to the chips determined by the first determining module;
the simulation module is used for simulating the plurality of chips based on the first target simulation heat dissipation parameters determined by the second determination module by taking the circuit board as a simulation object to obtain first target simulation junction temperatures corresponding to the plurality of chips;
and the third determining module is used for determining a target heat dissipation mode of the circuit board based on the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips, which are obtained by the simulation module.
According to still another aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium storing a computer program for executing the above-described heat radiation pattern determination method.
According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including:
a processor;
A memory for storing the processor-executable instructions;
the processor is used for reading the executable instructions from the memory and executing the instructions to realize the heat dissipation mode determining method.
Based on the method, the device, the storage medium and the electronic equipment for determining the heat dissipation mode provided by the embodiment of the disclosure, the first target simulation heat dissipation parameters can be determined by referring to the hot air risk levels corresponding to the chips included in the circuit board, and the first target simulation heat dissipation parameters are used for simulating the chips, so that the first target simulation junction temperatures corresponding to the chips can be obtained efficiently and reliably through simulation calculation, the first target simulation junction temperatures can reflect the working junction temperatures of the chips under the real working conditions more effectively, and the maximum junction temperatures corresponding to the chips are combined, so that the target heat dissipation mode of the circuit board can be determined efficiently and reliably, and can be used for indicating whether different chips are required to be provided with heat dissipation bosses.
The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing embodiments thereof in more detail with reference to the accompanying drawings. The accompanying drawings are included to provide a further understanding of embodiments of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. In the drawings, like reference numerals generally refer to like parts or steps.
Fig. 1 is a flowchart illustrating a heat dissipation method determining method according to an exemplary embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a heat dissipation mode determining method according to another exemplary embodiment of the present disclosure.
Fig. 3 is a flowchart illustrating a heat dissipation mode determining method according to still another exemplary embodiment of the present disclosure.
Fig. 4 is a flowchart illustrating a heat dissipation mode determining method according to another exemplary embodiment of the present disclosure.
Fig. 5 is a flowchart illustrating a heat dissipation mode determining method according to another exemplary embodiment of the present disclosure.
Fig. 6 is a flowchart illustrating a heat dissipation mode determining method according to another exemplary embodiment of the present disclosure.
Fig. 7 is a flowchart illustrating a heat dissipation mode determining method according to another exemplary embodiment of the present disclosure.
Fig. 8 is a schematic structural diagram of a heat dissipation mode determining device according to an exemplary embodiment of the present disclosure.
Fig. 9 is a schematic structural view of a heat dissipation mode determining device provided in another exemplary embodiment of the present disclosure.
Fig. 10 is a schematic structural view of a heat dissipation mode determining device provided in still another exemplary embodiment of the present disclosure.
Fig. 11 is a schematic structural view of a heat dissipation mode determining device provided in still another exemplary embodiment of the present disclosure.
Fig. 12 is a schematic structural view of a heat dissipation mode determining device provided in still another exemplary embodiment of the present disclosure.
Fig. 13 is a schematic structural view of a heat dissipation mode determining device provided in still another exemplary embodiment of the present disclosure.
Fig. 14 is a block diagram of an electronic device provided in an exemplary embodiment of the present disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.
It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or modules, etc., and do not represent a particular technical meaning or necessarily logical order.
It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.
It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.
In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship.
It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.
Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
Embodiments of the present disclosure may be applicable to electronic devices such as terminal devices, computer systems, servers, etc., which may operate with numerous other general purpose or special purpose computing system environments or configurations. Examples of well known terminal devices, computing systems, environments, and/or configurations that may be suitable for use with the terminal device, computer system, server, or other electronic device include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments that include any of the above systems, and the like.
Electronic devices such as terminal devices, computer systems, servers, etc. may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform particular tasks or implement particular abstract data types. The computer system/server may be implemented in a distributed cloud computing environment in which tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computing system storage media including memory storage devices.
Summary of the application
The circuit board may include a plurality of chips, for example, the circuit board in a domain controller of a vehicle may include a plurality of artificial intelligence (Artificial Intelligence, AI) chips.
Along with the rising of chip consumption, can be through setting up the heat dissipation boss for the chip, with the quick conduction of the heat of chip department to forced air cooler or liquid cooler department to strengthen the chip heat dissipation with lower cost. Since the excessive arrangement of the heat dissipation boss significantly increases the production cost and difficulty, it is necessary to distinguish whether different chips are necessary to arrange the heat dissipation boss. How to efficiently and reliably distinguish whether different chips are necessary to be provided with heat dissipation bosses is a problem to be solved for those skilled in the art.
Exemplary overview
In the embodiment of the disclosure, whether the heat dissipation boss is necessary to be arranged on different chips can be effectively and reliably distinguished through the application of computer simulation technology (Computer Simulation Technology, CST).
It can be appreciated that the computer simulation technology is a comprehensive technology that utilizes the results of computer science and technology to build a model of a system to be simulated and to perform dynamic experiments on the model under certain experimental conditions, and has the advantages of high efficiency, safety, less constraint by environmental conditions, and the like, and has become an important tool for analyzing, designing, running, evaluating, and training systems (especially complex systems).
Alternatively, the computer simulation technique may include a computer fluid dynamics (Computational Fluid Dynamics, CFD) simulation technique.
It will be appreciated that CFD simulation techniques are equivalent to "virtually" experiments performed on a computer, using numerical solutions to differential equations for controlling fluid flow, to derive the discrete distribution of the flow field of the fluid flow over a continuous region, thereby approximating the actual fluid flow conditions.
Exemplary method
Fig. 1 is a flowchart illustrating a heat dissipation method determining method according to an exemplary embodiment of the present disclosure. The method shown in fig. 1 may include step 110, step 120, step 130, and step 140, each of which is described below.
Alternatively, the circuit board may be located in a domain controller of the vehicle, or in other electronic systems of the vehicle in addition to the domain controller. Of course, the circuit board may also be located in other electronic devices than a vehicle.
Optionally, the circuit board may include: a substrate and a plurality of chips disposed on the substrate; wherein the substrate may be a printed circuit board (PriRted Circuit Board, PCB); the plurality of chips may refer to all chips provided on the substrate, or to a part of chips among all chips provided on the substrate.
It should be noted that, the hot air risk level corresponding to the chip may refer to: the risk level of the chip over-temperature phenomenon; the higher the hot air risk level is, the more easily the chip is overtemperature, and the lower the hot air risk level is, the less easily the chip is overtemperature.
Alternatively, the hot risk levels may be divided into n+1 levels in order of the levels from low to high, level 0, level 1, level 2, … …, level n-1, level n, respectively.
In step 120, with reference to the hot air risk levels corresponding to the chips, a plurality of chips (for convenience of description, a set of chips is referred to as a first chipset to be verified) that need to verify the rationality of the heat dissipation boss may be determined from the chips, and according to the determination result, heat dissipation characteristic values are determined for the chips, so as to obtain a first target simulated heat dissipation parameter composed of the heat dissipation characteristic values corresponding to the chips.
Alternatively, for each of the plurality of chips, if the chip is located in the first chipset to be verified, a first preset feature value for characterizing that the heat dissipation boss is set may be determined as a heat dissipation feature value corresponding to the chip, and if the chip is not located in the first chipset to be verified, a second preset feature value for characterizing that the heat dissipation boss is not set may be determined as a heat dissipation feature value corresponding to the chip.
Alternatively, the first preset feature value may be 1, and the second preset feature value may be 0; alternatively, the first preset feature value may be YES, and the second preset feature value may be NO.
And 130, simulating the plurality of chips based on the first target simulated heat dissipation parameters by taking the circuit board as a simulation object to obtain first target simulated junction temperatures corresponding to the plurality of chips.
In step 130, the drawing, the size, the material, and the like of the circuit board and the first target simulation heat dissipation parameters may be provided to the computer simulation software, so that the computer simulation software may build a model of the circuit board, simulate the working conditions of the heat dissipation bosses set by the chips in the first chipset to be verified, and perform a dynamic experiment on the model of the circuit board to obtain the first target simulation junction temperatures corresponding to the chips through simulation calculation.
It is understood that junction temperature generally refers to: the highest temperature of a semiconductor chip located in an electronic device, typically above the case temperature and the device surface temperature, may be used to measure the heat dissipation capability of the chip from the semiconductor wafer to the case.
And 140, determining a target heat dissipation mode of the circuit board based on the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips.
Alternatively, the maximum junction temperature corresponding to the chip may refer to: the maximum junction temperature which can be born by the chip is designed for the chip in advance; the maximum junction temperatures corresponding to different chips can be the same or different.
In step 140, by combining the first target simulated junction temperatures corresponding to the chips and the maximum junction temperatures corresponding to the chips, it is possible to evaluate which chips of the chips are necessary to be provided with the heat dissipation boss and which chips are not necessary to be provided with the heat dissipation boss, so that a target heat dissipation manner including the evaluation result can be obtained.
Based on the method for determining the heat dissipation mode provided by the embodiment of the disclosure, the first target simulation heat dissipation parameters can be determined by referring to the hot air risk levels corresponding to the chips included in the circuit board, and the first target simulation heat dissipation parameters are used for simulating the chips, so that the first target simulation junction temperatures corresponding to the chips can be obtained efficiently and reliably through simulation calculation, the working junction temperatures of the chips under real working conditions can be reflected more effectively by the first target simulation junction temperatures, and then the target heat dissipation mode of the circuit board can be determined efficiently and reliably by combining the maximum junction temperatures corresponding to the chips.
On the basis of the embodiment shown in fig. 1, step 120, as shown in fig. 2, includes step 1201, step 1203, step 1205, step 1207, step 1209, and step 1211.
Alternatively, the first preset hot air risk Level may be the hot air risk Level with the highest Level, and the case that the hot air risk levels are totally divided into n+1 levels in the order from low Level to high Level is taken as an example, and the first preset hot air risk Level may be Level n.
In step 1203, a plurality of chips (for convenience of description, the set of chips is referred to as a second chip set to be verified) for which the rationality of the heat dissipation boss needs to be verified may be determined from the first set, and according to the determination result, heat dissipation characteristic values are determined for the plurality of chips (specifically, the manner of determining the heat dissipation characteristic values for the chips in order to obtain the first target simulated heat dissipation parameter may be referred to above), so that the first reference simulated heat dissipation parameter may be obtained.
And 1205, simulating the plurality of chips based on the first reference simulated heat dissipation parameters by taking the circuit board as a simulation object to obtain first reference simulated junction temperatures corresponding to the plurality of chips.
It should be noted that, the specific embodiment of step 1205 is referred to the description of step 130, and will not be described herein.
Alternatively, the preset number may be 0, 1, 2 or other number, i.e. the second preset thermal risk level may be a one-level, two-level, three-level or more lower hot air risk level than the first preset hot air risk level. For ease of understanding, in the embodiments of the present disclosure, the case where the preset number is 0 and the second preset hot risk Level is a hot risk Level that is one Level lower than the first preset hot risk Level is taken as an example to describe that the second preset hot risk Level may be Level n-1.
In step 1207, each chip of the plurality of chips may be determined that the corresponding hot air risk level is between the first preset thermal risk level and the second preset hot air risk level (including both the first preset thermal risk level and the second preset thermal risk level), and for each determined chip, a difference between the maximum junction temperature corresponding to the chip and the first reference simulated junction temperature may be referred to determine whether the chip meets the preset overtemperature condition.
Assume that the first reference simulation result corresponding to the chip is expressed as T 1 The maximum junction temperature corresponding to the chip is expressed as T max The difference between the maximum junction temperature corresponding to the chip and the first reference simulation junction temperature can be T max －T 1 Characterization is carried out, or with (T) max －T 1 )/T max Characterization was performed. Alternatively, it may be at T max －T 1 Judging that the chip meets the preset overtemperature condition under the condition that the chip is larger than the preset difference value; alternatively, the time interval may be set at (T max －T 1 )/T max And under the condition that the ratio is larger than the first preset ratio, judging that the chip meets the preset overtemperature condition. The method for determining whether the chip meets the preset overtemperature condition is described in the section with reference to the related description, and is not described in detail later.
The hot air risk level corresponding to the chips is located between the first preset hot risk level and the second preset hot risk level, and the set of the chips meeting the preset overtemperature condition can be used as the second set.
The specific embodiment of step 1209 is described with reference to step 1203, and will not be described herein.
In one embodiment, step 1211 comprises:
determining a second reference simulated heat dissipation parameter as a first target simulated heat dissipation parameter in response to the second preset hot air risk level being the hot air risk level with the lowest level;
Responding to the fact that the second preset thermal risk level is not the hot air risk level with the lowest level, using the circuit board as a simulation object, and simulating the plurality of chips based on the second reference simulation heat dissipation parameters to obtain second reference simulation junction temperatures corresponding to the plurality of chips respectively; determining a third set of chips, which are positioned between a first preset hot air risk level and a third preset hot air risk level and meet preset overtemperature conditions, from the plurality of chips based on second reference simulated junction temperatures corresponding to the plurality of chips and maximum junction temperatures corresponding to the plurality of chips, wherein the level of the third preset hot air risk level is lower than the second preset hot air risk level and is spaced from the second preset hot air risk level by a preset number of hot air risk levels; determining a third reference simulation heat dissipation parameter corresponding to each chip in the third set, wherein each chip is respectively provided with a heat dissipation boss; and determining a first target simulated heat dissipation parameter based on the third preset hot air risk level and the third reference simulated heat dissipation parameter.
It should be noted that, based on the third preset hot air risk level and the third reference simulation heat dissipation parameter, the method of determining the first target simulation heat dissipation parameter may refer to the method of determining the first target simulation heat dissipation parameter based on the second preset hot air risk level and the second reference simulation heat dissipation parameter, and only the third preset hot air risk level is regarded as a new second preset hot air risk level, and the third reference simulation heat dissipation parameter is regarded as a new second reference simulation heat dissipation parameter.
In a specific example, the hot air risk Level may be divided into 3 levels in order of low Level to high Level, namely Level 0, level 1 and Level 2, and the multiple chips may be 30 chips, namely I 1 、I 2 、I 3 、……、I 30 Wherein I 1 To I 10 Corresponding to Level 2, I 11 To I 22 Corresponding to Level 1, I 23 To I 30 Corresponding to Level 0.
Assuming the first preset hot risk Level is Level 2, the first set may include I 1 To I 10 . Assuming that the first reference simulation heat dissipation parameters correspond to the situation that all chips in the first set are respectively provided with heat dissipation bosses, the circuit board can be used as a simulation object, and the heat dissipation is simulated based on the first referenceAnd carrying out primary simulation on the 30 chips to obtain first reference simulation junction temperatures corresponding to the 30 chips. Based on the first reference simulated junction temperature corresponding to each of 30 chips and the maximum junction temperature corresponding to each of 30 chips, the method can be implemented by I 1 To I 22 And selecting all chips meeting the preset overtemperature condition to form a second set. Assuming that the second set includes I 1 To I 5 I 18 To I 22 The second reference simulation heat dissipation parameter corresponds to I 1 To I 5 I 18 To I 22 The 10 chips are respectively provided with heat dissipation bosses.
Assuming that the second preset thermal risk Level is Level 1 and the third preset thermal risk Level is Level 0, it is obvious that the second preset thermal risk Level is not the lowest hot air risk Level, then the circuit board can be used as a simulation object, based on the second reference simulation heat dissipation parameters, the second simulation is performed on the 30 chips to obtain second reference simulation junction temperatures corresponding to the 30 chips, and the maximum junction temperatures corresponding to the 30 chips are combined, so that the simulation device can obtain the simulation result from I 1 To I 30 And selecting all the chips meeting the preset overtemperature condition from the chips to form a third set. Assuming that the third set includes I 1 To I 5 、I 18 To I 20 I 23 To I 28 Then it can be determined that I 1 To I 5 、I 18 To I 20 I 23 To I 28 And third reference simulation heat dissipation parameters corresponding to the heat dissipation bosses are respectively arranged. Because the third preset hot air risk level is already the hot air risk level with the lowest level, the third reference simulated heat dissipation parameter can be directly determined as the first target simulated heat dissipation parameter.
It should be noted that, assuming that Level 0 as the third preset thermal risk Level is not the lowest-Level hot air risk Level, for example, there is Level 0 'with a Level lower than Level 0, the circuit board may be used as a simulation object, multiple chips included in the circuit board may be simulated based on the third reference simulated heat dissipation parameters to obtain reference simulated junction temperatures corresponding to the multiple chips, and then, in combination with the maximum junction temperatures corresponding to the multiple chips, each chip meeting the preset overtemperature condition may be selected from the chips with the corresponding hot air risk levels between Level 2 and Level 0' to form another set, and the subsequent processing after determining the third set is similar to that described above, which is not repeated herein.
It can be seen that, referring to whether the second preset thermal risk level is the hot air risk level with the lowest level, the second reference simulation heat dissipation parameter can be selected to be directly determined as the first target simulation heat dissipation parameter, or according to the data obtained by simulating the plurality of chips based on the second reference simulation heat dissipation parameter, the chip with the overtemperature in the chip with the lower level is brought into the category of the chip with the rationality of the heat dissipation boss to be verified, and simulation is performed again, so that the appropriate first target simulation heat dissipation parameter is determined by referring to the data obtained by the re-simulation, thereby being beneficial to ensuring the rationality and reliability of the finally determined first target simulation heat dissipation parameter.
It should be noted that, the specific embodiment of step 1211 is not limited thereto, for example, if the second preset hot air risk level is the hot air risk level with the lowest level, the second reference simulated heat dissipation parameter may not be directly determined as the first target simulated heat dissipation parameter, but the second reference simulated heat dissipation parameter is presented to the user, and the user manually corrects the second reference simulated heat dissipation parameter, and uses the correction result of the second reference simulated heat dissipation parameter as the first target simulated heat dissipation parameter.
In addition, after the second reference simulated heat dissipation parameter is obtained by executing step 1209, the second reference simulated heat dissipation parameter may also be directly determined as the first target simulated heat dissipation parameter, without determining the first target simulated heat dissipation parameter according to whether the second preset thermal risk level is the thermal risk level with the lowest level.
In the embodiment of the disclosure, the rationality of the heat dissipation boss set on the chip can be verified through simulation from the chip with the highest corresponding hot air risk level, then the chip with the relatively lower corresponding hot air risk level can be gradually brought into the range of the chip with the rationality of the heat dissipation boss set to be verified, and simulation is performed again until the first target simulation heat dissipation parameter is obtained, so that the rationality and reliability of the finally determined first target simulation heat dissipation parameter can be ensured through multiple simulations, and the determination efficiency of the first target simulation heat dissipation parameter can be ensured through the application of the hot air risk level.
In an alternative example, step 1203 includes:
determining a fourth reference simulation heat dissipation parameter corresponding to a heat dissipation boss which is not arranged on all chips in the plurality of chips;
taking the circuit board as a simulation object, and simulating the plurality of chips based on fourth reference simulation heat dissipation parameters to obtain third reference simulation junction temperatures corresponding to the chips respectively;
Determining a chip meeting a preset overtemperature condition in the first set based on a third reference simulation junction temperature corresponding to each of the plurality of chips and a maximum junction temperature corresponding to each of the plurality of chips;
and determining that the chips meeting the preset overtemperature condition in the first set are respectively provided with first reference simulation heat dissipation parameters corresponding to the heat dissipation bosses.
In the embodiment of the disclosure, the heat dissipation characteristic values corresponding to the chips may be set to the second preset characteristic value, so as to obtain a fourth reference simulation heat dissipation parameter, where the fourth reference simulation heat dissipation parameter corresponds to a case that the chips are not provided with heat dissipation bosses. And then, the drawing, the size, the material and other information of the circuit board and the fourth reference simulation heat dissipation parameters can be provided for computer simulation software, the computer simulation software can establish a model of the circuit board according to the information, simulate the working condition that the heat dissipation bosses are not arranged on the chips, and perform dynamic experiments on the model of the circuit board so as to obtain the third reference simulation junction temperatures corresponding to the chips through simulation calculation. For each chip in the first set, determining whether the chips meet the preset overtemperature condition according to the difference between the maximum junction temperature corresponding to the reference chip and the third reference simulation junction temperature, thereby determining each chip meeting the preset overtemperature condition in the first set and further obtaining the first reference simulation heat dissipation parameters. The first reference simulation heat dissipation parameters correspond to the situation that only the chips meeting the preset overtemperature conditions in the first set are provided with the heat dissipation bosses, and the chips easy to generate the overtemperature phenomenon are the chips really necessary to be provided with the heat dissipation bosses, so that the first reference simulation heat dissipation parameters have stronger pertinence, and the rationality and the reliability of the first target simulation heat dissipation parameters determined later are guaranteed.
Of course, the specific embodiment of step 1205 is not limited thereto, and for example, the first reference simulation heat dissipation parameter may directly correspond to a case where all chips in the first set are respectively provided with heat dissipation bosses.
On the basis of the embodiment shown in fig. 1, as shown in fig. 3, step 140 includes step 1401, step 1403, step 1405, step 1407, and step 1409.
In step 1401, for each of the plurality of chips, a difference between the maximum junction temperature corresponding to the chip and the first target simulated junction temperature may be referred to, and whether the chip satisfies a preset overtemperature condition may be determined, where a set of each of the plurality of chips satisfying the preset overtemperature condition may be used as the fourth set.
The specific embodiment of step 1403 is described with reference to step 1203, and will not be described herein.
In step 1405, the circuit board is used as a simulation object, and the multiple chips are simulated based on the second target simulation heat dissipation parameters, so as to obtain second target simulation junction temperatures corresponding to the multiple chips.
It should be noted that, the specific embodiment of step 1405 is referred to the description of step 130, and will not be described herein.
In step 1407, for each of the plurality of chips, a maximum junction temperature corresponding to the chip may be differed from the second target simulated junction temperature to obtain a first temperature difference corresponding to the chip.
Optionally, the target heat dissipation mode determined in step 1409 may be used to indicate: the chips in the fourth set need to be provided with heat dissipation bosses respectively. For each chip in the fourth set, the first temperature difference corresponding to the chip can be referred to determine what material, what size, etc. the heat dissipation boss set by the chip is made of, for example, the larger the first temperature difference corresponding to the chip is, the better the heat conduction performance of the heat dissipation boss set by the chip can be, and in addition, if a heat conduction interface material is set between the chip and the heat dissipation boss, the heat conduction interface material can also be selected according to the first temperature difference corresponding to the chip. That is, the target heat dissipation mode not only can be used for indicating which chips need to be provided with the heat dissipation boss, but also can indicate what material and what size the heat dissipation boss adopts, what heat conduction interface material is selected, and the like.
In the embodiment of the disclosure, the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips are combined, so that the fourth set of chips meeting the preset overtemperature condition in the plurality of chips can be determined efficiently and reliably, the second target simulation heat dissipation parameters can be determined for the fourth set, the second target simulation junction temperature corresponding to each of the plurality of chips is obtained through simulation, the first temperature difference corresponding to each of the plurality of chips can be obtained by combining the maximum junction temperature corresponding to each of the plurality of chips, the first temperature difference corresponding to each of the plurality of chips and the fourth set can be used for determining the target heat dissipation mode together, and the determined target heat dissipation mode can be used for indicating whether different chips need to be provided with heat dissipation bosses or not, and can also be used for indicating what material and what size the heat dissipation bosses adopt, and selecting information such as what heat conduction interface, and the like, so that effective reference can be provided for the design of the chips, the circuit board and the whole domain controller.
On the basis of the embodiment shown in fig. 1, as shown in fig. 4, step 110 includes step 1101, step 1103 and step 1105.
Alternatively, the theoretical junction temperature corresponding to the chip may refer to: and aiming at the chip, the junction temperature is obtained through theoretical calculation.
In one embodiment, step 1101 includes:
determining a cooling mode of the circuit board, calculating a safety coefficient by a chip junction temperature, and a third temperature difference between the circuit board and an environment temperature;
determining the temperature of a cooling medium corresponding to the cooling mode;
determining a sum of the cooling medium temperature and the third temperature difference;
for each of the plurality of chips, calculating a chip junction temperature, calculating a product of a safety coefficient, heating power of the chip and hardening thermal resistance of the chip, and determining a theoretical junction temperature corresponding to the chip based on a sum of the product, a cooling medium temperature and a sum value.
Alternatively, the cooling mode of the circuit board may be set manually, including but not limited to an air cooling mode, a liquid cooling mode, etc.; the chip junction temperature calculation safety coefficient can be a safety coefficient estimated according to experience; the environmental temperature can be set manually, and the third temperature difference between the circuit board and the environmental temperature can be a temperature difference set manually or estimated empirically; the temperature of the cooling medium corresponding to the cooling mode may be manually set, the temperature of the cooling medium corresponding to the air cooling mode may be an ambient temperature, and the cooling medium corresponding to the liquid cooling mode may be a cooling liquid inlet temperature.
Alternatively, the theoretical junction temperature of the chip may be calculated using the following formula:
T pcb ＝T α +△T pcb
T j ＇＝k×P×R jb +T α +T pcb
wherein T is α Indicating the temperature of the cooling medium，△T pcb Represents a third temperature difference, T pcb Representing the sum of the temperature of the cooling medium and the third temperature difference, T j ' represents the theoretical junction temperature of the chip, k represents the junction temperature of the chip, the calculated safety coefficient, P represents the heating power of the chip, and R jb Representing the thermal hardening resistance of the chip.
It is understood that the thermal resistance of the chip may refer to the thermal resistance between the heat source junction of the chip and the PCB. R is as follows jb There are two cases, in one case, R jb May refer to the hardening thermal resistance of the chip itself, in another case R jb May refer to the empirically estimated thermal hardening resistance for the chip.
In this embodiment, the theoretical junction temperature corresponding to the chip can be determined efficiently and reliably by referring to the cooling medium temperature and the chip junction temperature corresponding to the cooling mode of the circuit board, and the third temperature difference between the circuit board and the ambient temperature, and by simple arithmetic logic such as addition and multiplication.
Of course, the specific embodiment of step 1101 is not limited thereto, e.g., T in the above formula j ' after that, T can be manually controlled j ' make corrections and let T j The correction result of' is taken as the theoretical junction temperature corresponding to the chip.
In step 1103, a maximum junction temperature corresponding to each of the plurality of chips is determined.
Alternatively, the maximum junction temperatures corresponding to the chips may be set in advance.
In a specific embodiment, step 1105 includes:
determining a second temperature difference between a maximum junction temperature corresponding to each of the plurality of chips and a theoretical junction temperature for the chip;
determining a temperature difference range to which a second temperature difference corresponding to each of the plurality of chips belongs, wherein different temperature difference ranges correspond to different hot air risk levels;
and determining the hot air risk level corresponding to each of the chips based on the temperature difference range to which each of the second temperature differences corresponding to the chips belongs.
It should be noted that a plurality of temperature difference ranges may be preset, and a corresponding relationship between the plurality of temperature difference ranges and the corresponding hot air risk levels may be constructed. Alternatively, there may be a one-to-one correspondence between temperature differential ranges and hot air risk levels.
For each of the plurality of chips, the maximum junction temperature corresponding to the chip and the theoretical junction temperature can be differed to obtain a second temperature difference corresponding to the chip, the second temperature difference corresponding to the chip can be regarded as a junction temperature design margin of the chip, and the hot air risk level corresponding to the temperature difference range to which the second temperature difference corresponding to the chip belongs can be regarded as the hot air risk level corresponding to the chip.
In a specific example, the correspondence between the multiple temperature difference ranges and the corresponding hot air risk levels may be referred to in table 1 below, and then the hot air risk levels corresponding to the multiple chips may be determined according to the information described in table 1.
TABLE 1
As can be seen from Table 1, (-infinity, N) 1 ]、(N 1 ，N 2 ]、(N 2 ，N 3 ]、……、(N n-1 ，N n ]、(N n , + -infinity any of the above-mentioned) to respectively provide indicating a range of temperature differences. In addition, deltaT j A corresponding second temperature difference of the chip may be represented. Thus, the design margin of the chip can be expressed as DeltaT j Or T max —T j ＇。
Assume that the second error corresponding to the chip belongs to (N 2 ，N 3 ]In this temperature difference range, according to the information described in table 1, the hot air risk Level corresponding to the chip may be Level 2.
In this embodiment, through presetting the corresponding relation between the multiple temperature difference ranges and the corresponding hot air risk levels, only the maximum junction temperature corresponding to the chip is required to be differed from the theoretical junction temperature, and the hot air risk level corresponding to the chip can be determined efficiently and reliably according to the obtained distribution condition of the second temperature difference relative to the multiple temperature difference ranges.
Of course, the specific embodiment of step 1105 is not limited thereto, and for example, the correspondence between a plurality of proportion ranges and the corresponding hot air risk levels may be preset, and after the difference between the maximum junction temperature corresponding to the chip and the theoretical junction temperature is obtained, the obtained second temperature difference may be divided from the theoretical junction temperature corresponding to the chip, and the hot air risk level corresponding to the proportion range to which the obtained division result belongs may be used as the hot air risk level corresponding to the chip.
In the embodiment of the disclosure, for each chip in the plurality of chips, referring to the difference between the theoretical junction temperature and the maximum junction temperature corresponding to the chip, the design margin of the chip can be effectively evaluated, specifically, the larger the difference between the theoretical junction temperature and the maximum junction temperature is, the larger the design margin of the chip can be considered, the smaller the difference between the theoretical junction temperature corresponding to the chip and the maximum junction temperature is, the smaller the design margin of the chip can be considered, and according to the design margin, a reasonable hot air risk level can be determined for the chip, for example, the larger the design margin of the chip is, and the higher the hot air risk level corresponding to the chip can be.
On the basis of the embodiment shown in fig. 4, as shown in fig. 5, the method provided by the embodiment of the disclosure may further include a step 150, a step 160 and a step 170.
Alternatively, for each of the plurality of chips, the area on the circuit board corresponding to the chip may refer to: the computer simulation software is obtained through simulation calculation, and the temperature of the area on the circuit board, where the chip is arranged.
In step 160, for each of the plurality of chips, a difference between the simulated temperature of the area corresponding to the chip and the ambient temperature may be made to obtain a fourth temperature difference corresponding to the chip.
In step 170, for each of the plurality of chips, the third temperature difference corresponding to the chip may be updated to the fourth temperature difference corresponding to the chip, and then the updated third temperature difference is brought into the above related calculation formula of the theoretical junction temperature to perform calculation, so as to obtain a new theoretical junction temperature corresponding to the chip.
In the embodiment of the disclosure, the fourth temperature difference can be determined by applying a computer simulation technology, the theoretical junction temperature of the chip obtained by pure theoretical calculation is updated accordingly, and the chips can be classified again according to the updated theoretical junction temperature to obtain corresponding hot air risk levels, so that the rationality and reliability of the finally determined hot air risk levels corresponding to the chips are guaranteed.
On the basis of the embodiment shown in fig. 1, step 110, as shown in fig. 6, includes step 1107, step 1109, and step 1111.
In step 1107, the respective thermal resistance of the crust of all the chips included in the circuit board is determined.
It is understood that the thermal resistance of the chip to the crust may refer to: the heat source of the chip is bonded to the thermal resistance of the housing. Alternatively, the thermal resistance of the chip to the crust may be expressed as R jc 。
In step 1109, a plurality of chips with a crust thermal resistance less than a preset thermal resistance are screened from all the chips included in the circuit board.
In step 1109, the respective thermal resistance of the crust of all the chips included in the circuit board may be compared with a preset thermal resistance one by one to select a plurality of chips having a thermal resistance of crust less than the preset thermal resistance.
And step 1111, determining hot air risk levels corresponding to the chips with the crusting heat resistance smaller than the preset heat resistance.
In general, if the thermal resistance of the chip is too large, the heat generated during the actual operation of the chip is not excessive, the chip is not heated up greatly, and the normal operation of the circuit board and the domain controller is not greatly influenced. In view of this, in the embodiment of the present disclosure, only a plurality of chips with a crust thermal resistance smaller than a preset thermal resistance may be screened out from all the chips included in the circuit board, and only the screened chips are used to determine a corresponding hot air risk level for further determining whether a heat dissipation boss needs to be set, so that it is not necessary to verify whether the heat dissipation boss needs to be set for all the chips included in the circuit board, which is beneficial to improving verification efficiency.
In an alternative example, as shown in fig. 7, in order to distinguish whether different chips need to be provided with heat dissipation bosses, the cooling mode may be first determined for the circuit board, and related parameters may be estimated, where the related parameters include, but are not limited to, the chip junction temperature calculation safety coefficient k, and the third temperature difference Δt between the circuit board and the ambient temperature pcb Based on the above, the chip junction temperature can be theoretically calculated to obtain the theoretical junction temperature corresponding to each of the plurality of chips included in the circuit board. According to the theoretical junction temperature corresponding to each of the chips, and then combining the maximum junction temperature corresponding to each of the chips, the junction temperature design margin corresponding to each of the chips can be calculated in a difference mode, and according to the obtained junction temperature design margin, the chips can be classified to obtain the hot air risk Level corresponding to each of the chips, for example, the chips can be divided into Level 0, level 1, level 2, … …, level n-1 and Level n.
Then, a first version of heat dissipation structure without heat dissipation bosses on all the chips can be determined, simulation calculation is performed to obtain junction temperatures of the chips at different levels, and the chips with over-temperature are marked (which is equivalent to the fourth reference simulation heat dissipation parameters corresponding to the fact that all the chips in the plurality of chips are determined not to be provided with the heat dissipation bosses, a circuit board is taken as a simulation object, the plurality of chips are simulated based on the fourth reference simulation heat dissipation parameters to obtain third reference simulation junction temperatures corresponding to the plurality of chips, and the chips meeting preset over-temperature conditions in the first set are determined based on the third reference simulation junction temperatures corresponding to the plurality of chips and the maximum junction temperatures corresponding to the plurality of chips).
And then, designing and checking all the Level n chips, designing heat dissipation bosses and heat conduction interface materials for the overtemperature Level n chips, determining a second-version heat dissipation structure (corresponding to the first reference simulation heat dissipation parameters), and performing simulation calculation to obtain junction temperatures of all the chips.
And then, aiming at the Level n-1 and the Level n Level chips, a heat dissipation boss and a heat conduction interface material can be designed for the overtemperature chips determined in the last simulation, a third heat dissipation structure (corresponding to the second reference simulation heat dissipation parameters) can be determined according to the heat dissipation boss and the heat conduction interface material, and simulation calculation is performed to obtain junction temperatures of all the chips. And then the method is analogized until the n+1th edition heat radiation structure is determined, so that the chips which need to be provided with the heat radiation boss and the chips which do not need to be provided with the heat radiation boss can be determined.
Optionally, after each simulation, updating the theoretical junction temperature according to the simulated area simulation temperature, so as to redetermine the hot air risk level corresponding to each of the plurality of chips.
In summary, by adopting the embodiment of the disclosure, whether different chips are necessary to be provided with the heat dissipation boss can be distinguished efficiently and reliably.
Any of the heat dissipation manner determination methods provided by the embodiments of the present disclosure may be performed by any suitable device having data processing capabilities, including, but not limited to: terminal equipment, servers, etc. Alternatively, any of the heat dissipation mode determining methods provided by the embodiments of the present disclosure may be executed by a processor, such as the processor executing any of the heat dissipation mode determining methods mentioned by the embodiments of the present disclosure by calling corresponding instructions stored in a memory. And will not be described in detail below.
Exemplary apparatus
Fig. 8 is a schematic structural diagram of a heat dissipation mode determining device according to an exemplary embodiment of the present disclosure. The apparatus shown in fig. 8 includes a first determination module 810, a second determination module 820, a simulation module 830, and a third determination module 840.
A first determining module 810, configured to determine hot air risk levels corresponding to a plurality of chips included in the circuit board;
a second determining module 820, configured to determine, based on the hot air risk levels corresponding to the multiple chips determined by the first determining module 810, first target simulation heat dissipation parameters corresponding to the heat dissipation bosses respectively provided on at least some of the multiple chips;
the simulation module 830 is configured to simulate the plurality of chips based on the first target simulated heat dissipation parameter determined by the second determination module 820 by using the circuit board as a simulation object, so as to obtain first target simulated junction temperatures corresponding to the plurality of chips;
The third determining module 840 is configured to determine a target heat dissipation mode of the circuit board based on the first target simulated junction temperatures corresponding to the multiple chips obtained by the simulating module 830 and the maximum junction temperatures corresponding to the multiple chips.
In an alternative example, as shown in fig. 9, the second determining module 820 includes:
a first determining submodule 8201, configured to determine a first set of chips with a corresponding hot air risk level being a first preset hot risk level among the plurality of chips;
the second determining submodule 8203 is configured to determine that at least some chips in the first set determined by the first determining submodule 8201 are respectively provided with a first reference simulation heat dissipation parameter corresponding to the heat dissipation boss;
the first simulation submodule 8205 is configured to simulate the plurality of chips based on the first reference simulation heat dissipation parameter determined by the second determination submodule 8203 by using the circuit board as a simulation object, so as to obtain first reference simulation junction temperatures corresponding to the plurality of chips;
a third determining submodule 8207, configured to determine, based on the first reference simulated junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips obtained by the first simulating submodule 8205, that the corresponding hot air risk level is between a first preset hot air risk level and a second preset hot air risk level, and that the second set of chips meets the preset overtemperature condition, where the second preset hot air risk level is lower than the first preset hot air risk level, and that a preset number of hot air risk levels are spaced between the second preset hot air risk level;
A fourth determining submodule 8209, configured to determine that each chip in the second set determined by the third determining submodule 8207 is respectively provided with a second reference simulation heat dissipation parameter corresponding to the heat dissipation boss;
the fifth determining submodule 8211 is configured to determine a first target simulated heat dissipation parameter based on the second preset thermal risk level and the second reference simulated heat dissipation parameter determined by the fourth determining submodule 8209.
In an alternative example, fifth determination submodule 8211 includes:
a first determining unit, configured to determine, in response to the second preset hot air risk level being the hot air risk level with the lowest level, the second reference simulated heat dissipation parameter determined by the fourth determining submodule 8209 as the first target simulated heat dissipation parameter;
the second determining unit is configured to simulate, in response to the second preset thermal risk level not being the hot air risk level with the lowest level, the plurality of chips based on the second reference simulated heat dissipation parameter determined by the fourth determining submodule 8209 by using the circuit board as a simulation object, to obtain second reference simulated junction temperatures corresponding to the plurality of chips; determining a third set of chips, which are positioned between a first preset hot air risk level and a third preset hot air risk level and meet preset overtemperature conditions, from the plurality of chips based on second reference simulated junction temperatures corresponding to the plurality of chips and maximum junction temperatures corresponding to the plurality of chips, wherein the level of the third preset hot air risk level is lower than the second preset hot air risk level and is spaced from the second preset hot air risk level by a preset number of hot air risk levels; determining a third reference simulation heat dissipation parameter corresponding to each chip in the third set, wherein each chip is respectively provided with a heat dissipation boss; and determining a first target simulated heat dissipation parameter based on the third preset hot air risk level and the third reference simulated heat dissipation parameter.
In an alternative example, the second determination submodule 8203 includes:
a third determining unit, configured to determine a fourth reference simulated heat dissipation parameter corresponding to the heat dissipation boss is not set in all chips in the plurality of chips;
the simulation unit is used for simulating the plurality of chips based on the fourth reference simulation heat dissipation parameters determined by the third determination unit by taking the circuit board as a simulation object to obtain third reference simulation junction temperatures corresponding to the chips respectively;
a fourth determining unit, configured to determine, based on the third reference simulated junction temperatures corresponding to the plurality of chips obtained by the simulation unit and the maximum junction temperatures corresponding to the plurality of chips, a chip that meets a preset overtemperature condition in the first set determined by the first determining submodule 8201;
a fifth determining unit, configured to determine that chips meeting the preset overtemperature condition in the first set determined by the first determining submodule 8201 are respectively provided with a first reference simulated heat dissipation parameter corresponding to the heat dissipation boss.
In an alternative example, as shown in fig. 10, the third determining module 840 includes:
a sixth determining submodule 8401, configured to determine a fourth set of chips that satisfy a preset overtemperature condition among the plurality of chips based on the first target simulated junction temperatures corresponding to the plurality of chips and the maximum junction temperatures corresponding to the plurality of chips obtained by the simulation module 830;
A seventh determining submodule 8403, configured to determine second target simulation heat dissipation parameters corresponding to the heat dissipation bosses respectively set by each chip in the fourth set determined by the sixth determining submodule 8401;
the second simulation submodule 8405 is configured to simulate the plurality of chips based on the second target simulation heat dissipation parameter determined by the seventh determination submodule 8403 by using the circuit board as a simulation object, so as to obtain second target simulation junction temperatures corresponding to the plurality of chips;
an eighth determining submodule 8407 configured to determine, for each of the plurality of chips, a first temperature difference between a maximum junction temperature corresponding to the chip and a second target simulated junction temperature corresponding to the chip determined by the second simulation submodule 8405;
the ninth determining submodule 8409 is configured to determine a target heat dissipation mode of the circuit board based on the first temperature difference determined by the eighth determining submodule 8407 and the fourth set determined by the sixth determining submodule 8401.
In an alternative example, as shown in fig. 11, the first determining module 810 includes:
a tenth determination submodule 8101, configured to determine theoretical junction temperatures corresponding to each of a plurality of chips included in the circuit board;
an eleventh determining submodule 8103, configured to determine a maximum junction temperature corresponding to each of the plurality of chips;
And a twelfth determining submodule 8105, configured to determine a hot air risk level corresponding to each of the plurality of chips based on the theoretical junction temperature corresponding to each of the plurality of chips determined by the tenth determining submodule 8101 and the maximum junction temperature corresponding to each of the plurality of chips determined by the eleventh determining submodule 8103.
In an alternative example, twelfth determination submodule 8105 includes:
a sixth determining unit, configured to determine, for each of the plurality of chips, a second temperature difference between a maximum junction temperature corresponding to the chip determined by the tenth determining submodule 8101 and a theoretical junction temperature corresponding to the chip determined by the eleventh determining submodule 8103;
a seventh determining unit, configured to determine, for each of the plurality of chips, a temperature difference range to which the second temperature difference corresponding to the chip determined by the sixth determining unit belongs, where different temperature difference ranges correspond to different hot air risk levels;
and an eighth determining unit, configured to determine a hot air risk level corresponding to each of the plurality of chips based on the temperature difference ranges to which the second temperature differences corresponding to the plurality of chips determined by the seventh determining unit belong.
In an alternative example, tenth determination submodule 8101 includes:
a ninth determining unit, configured to determine a cooling mode of the circuit board, a chip junction temperature calculation safety coefficient, and a third temperature difference between the circuit board and an ambient temperature;
A tenth determination unit configured to determine a cooling medium temperature corresponding to the cooling manner determined by the ninth determination unit;
an eleventh determining unit configured to determine a sum of the cooling medium temperature and the third temperature difference determined by the tenth determining unit;
a twelfth determining unit for calculating, for each of the plurality of chips, a product of the chip junction temperature calculation safety coefficient determined by the ninth determining unit, the heating power of the chip, and the hardening heat resistance of the chip, and determining a theoretical junction temperature corresponding to the chip based on the product, a sum of the cooling medium temperature and the sum value determined by the ninth determining unit.
In an alternative example, as shown in fig. 12, an apparatus provided by an embodiment of the present disclosure further includes:
a fourth determining module 850, configured to determine an area simulation temperature corresponding to each of the plurality of chips on the circuit board after simulating the plurality of chips;
a fifth determining module 860, configured to determine, for each of the plurality of chips, a fourth temperature difference between the region simulation temperature corresponding to the chip and the ambient temperature determined by the fourth determining module 850;
the updating module 870 is configured to update the theoretical junction temperatures corresponding to the chips based on the fourth temperature differences corresponding to the chips determined by the fifth determining module 860, and trigger the twelfth determining sub-module 8105.
In an alternative example, as shown in fig. 13, a first determining module 810 includes;
a thirteenth determination submodule 8107 for determining the respective crusting thermal resistances of all the chips included in the circuit board;
a screening submodule 8109, configured to screen, from all the chips included in the circuit board, a plurality of chips whose crusting thermal resistance determined by the thirteenth determination submodule 8107 is smaller than a preset thermal resistance;
the fourteenth determination submodule 8111 is configured to determine a hot air risk level corresponding to each of the plurality of chips that are screened by the screening submodule 8109 and have a crusting thermal resistance less than a preset thermal resistance.
In the apparatus of the present disclosure, various optional embodiments, optional implementations, and optional examples of the disclosure may be flexibly selected and combined as needed to achieve corresponding functions and effects, which are not listed in one-to-one.
Exemplary electronic device
Next, an electronic device according to an embodiment of the present disclosure is described with reference to fig. 14. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent thereof, which may communicate with the first device and the second device to receive the acquired input signals therefrom.
Fig. 14 illustrates a block diagram of an electronic device 1400 in accordance with an embodiment of the disclosure.
As shown in fig. 14, the electronic device 1400 includes one or more processors 1410 and a memory 1420.
The processor 1410 may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.
In one example, the electronic device 1400 may further include: an input device 1430 and an output device 1440, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).
For example, where the electronic device 1400 is a first device or a second device, the input means 1430 may be a microphone or an array of microphones. When the electronic device 1400 is a stand-alone device, the input means 1430 may be a communication network connector for receiving the acquired input signals from the first device and the second device.
In addition, the input device 1430 may also include, for example, a keyboard, a mouse, and the like.
The output device 1440 can output various information to the outside. The output device 1440 may include, for example, a display, speakers, a printer, and a communication network and its connected remote output devices, etc.
Of course, only some of the components of the electronic device 1400 that are relevant to the present disclosure are shown in fig. 14 for simplicity, components such as buses, input/output interfaces, etc. are omitted. In addition, electronic device 1400 may include any other suitable components depending on the particular application.
Exemplary computer program product and computer readable storage Medium
In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the steps in a heat dissipation manner determination method according to various embodiments of the present disclosure described in the above "exemplary methods" section of this specification.
The computer program product may write program code for performing the operations of embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present disclosure may also be a computer-readable storage medium, having stored thereon computer program instructions, which when executed by a processor, cause the processor to perform steps in a heat dissipation manner determination method according to various embodiments of the present disclosure described in the above "exemplary method" section of the present disclosure.
The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The basic principles of the present disclosure have been described above in connection with specific embodiments, but the advantages, benefits, effects, etc. mentioned in this disclosure are merely examples and are not to be considered as necessarily possessed by the various embodiments of the present disclosure. The specific details disclosed herein are merely for purposes of example and understanding, and are not intended to limit the disclosure to the specific details described above.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.
The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.
The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the sequence specifically described above unless specifically stated otherwise. Furthermore, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.
It is also noted that in the apparatus, devices and methods of the present disclosure, components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered equivalent to the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. The present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.
Claims (13)
1. A heat dissipation mode determining method includes:
determining the hot air risk level corresponding to each of a plurality of chips included in the circuit board;
determining first target simulation heat dissipation parameters corresponding to heat dissipation bosses respectively arranged on at least part of the chips based on the hot air risk grades corresponding to the chips respectively;
taking the circuit board as a simulation object, and simulating the plurality of chips based on the first target simulation heat dissipation parameters to obtain first target simulation junction temperatures corresponding to the plurality of chips respectively;
and determining a target heat dissipation mode of the circuit board based on the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips.
2. The method of claim 1, wherein the determining, based on the hot air risk levels corresponding to the plurality of chips, that at least some of the plurality of chips are respectively provided with the first target simulated heat dissipation parameters corresponding to the heat dissipation bosses comprises:
Determining a first set of chips, corresponding to the hot air risk level, of the plurality of chips;
determining first reference simulation heat dissipation parameters corresponding to heat dissipation bosses respectively arranged on at least part of chips in the first set;
taking the circuit board as a simulation object, and simulating the plurality of chips based on the first reference simulation heat dissipation parameters to obtain first reference simulation junction temperatures corresponding to the plurality of chips respectively;
determining, based on the first reference simulated junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips, a second set of chips in which the corresponding hot air risk level is between the first preset thermal risk level and a second preset thermal risk level and a preset overtemperature condition is satisfied, the second preset thermal risk level being lower than the first preset hot air risk level and being spaced apart from the first preset hot air risk level by a preset number of hot air risk levels;
determining second reference simulation heat dissipation parameters corresponding to the heat dissipation bosses respectively arranged on each chip in the second set;
And determining the first target simulated heat dissipation parameter based on the second preset thermal risk level and the second reference simulated heat dissipation parameter.
3. The method of claim 2, wherein the determining the first target simulated heat dissipation parameter based on the second preset thermal risk level and the second reference simulated heat dissipation parameter comprises:
determining the second reference simulated heat dissipation parameter as the first target simulated heat dissipation parameter in response to the second preset hot air risk level being the hot air risk level with the lowest level;
responding to the hot air risk level with the second preset hot air risk level not being the lowest level, taking the circuit board as a simulation object, and simulating the plurality of chips based on the second reference simulation heat dissipation parameters to obtain second reference simulation junction temperatures corresponding to the plurality of chips; determining a third set of chips, corresponding to the hot air risk levels, from the first preset hot air risk level to a third preset hot air risk level, based on the second reference simulated junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips, wherein the third preset hot air risk level is lower than the second preset hot air risk level and is spaced from the second preset hot air risk level by a preset number of hot air risk levels; determining a third reference simulation heat dissipation parameter corresponding to each chip in the third set, wherein each chip is respectively provided with a heat dissipation boss; and determining the first target simulation heat dissipation parameter based on the third preset hot air risk level and the third reference simulation heat dissipation parameter.
4. The method of claim 2, wherein the determining that at least some chips in the first set are respectively provided with first reference simulated heat dissipation parameters corresponding to heat dissipation bosses comprises:
determining a fourth reference simulation heat dissipation parameter corresponding to a heat dissipation boss which is not arranged on all chips in the plurality of chips;
taking the circuit board as a simulation object, and simulating the plurality of chips based on the fourth reference simulation heat dissipation parameters to obtain third reference simulation junction temperatures corresponding to the plurality of chips respectively;
determining a chip meeting a preset overtemperature condition in the first set based on the third reference simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips;
and determining that the chips meeting the preset overtemperature condition in the first set are respectively provided with first reference simulation heat dissipation parameters corresponding to the heat dissipation bosses.
5. The method of claim 1, wherein the determining the target heat dissipation pattern of the circuit board based on the first target simulated junction temperature for each of the plurality of chips and the maximum junction temperature for each of the plurality of chips comprises:
Determining a fourth set of chips meeting a preset overtemperature condition in the plurality of chips based on the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips;
determining second target simulation heat dissipation parameters corresponding to the heat dissipation bosses respectively arranged on each chip in the fourth set;
taking the circuit board as a simulation object, and simulating the plurality of chips based on the second target simulation heat dissipation parameters to obtain second target simulation junction temperatures corresponding to the plurality of chips respectively;
for each chip in the plurality of chips, determining a first temperature difference between the maximum junction temperature corresponding to the chip and the second target simulation junction temperature;
and determining a target heat dissipation mode of the circuit board based on the first temperature difference corresponding to each of the plurality of chips and the fourth set.
6. The method of claim 1, wherein the determining the hot risk level for each of the plurality of chips included in the circuit board comprises:
determining theoretical junction temperatures corresponding to a plurality of chips included in the circuit board;
determining the respective maximum junction temperatures of the plurality of chips;
And determining the hot air risk level corresponding to each of the plurality of chips based on the theoretical junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips.
7. The method of claim 6, wherein the determining the respective hot air risk level for the plurality of chips based on the theoretical junction temperature for the respective plurality of chips and the maximum junction temperature for the respective plurality of chips comprises:
determining, for each of the plurality of chips, a second temperature difference between the maximum junction temperature and the theoretical junction temperature corresponding to the chip;
determining a temperature difference range to which the second temperature difference corresponding to each of the plurality of chips belongs, wherein different temperature difference ranges correspond to different hot air risk levels;
and determining the hot air risk level corresponding to each of the plurality of chips based on the temperature difference range to which each of the plurality of second temperature differences corresponding to the plurality of chips belongs.
8. The method of claim 6, wherein determining theoretical junction temperatures for each of a plurality of chips included in the circuit board comprises:
determining a cooling mode of the circuit board, a chip junction temperature calculation safety coefficient and a third temperature difference between the circuit board and the ambient temperature;
Determining the temperature of a cooling medium corresponding to the cooling mode;
determining a sum of the cooling medium temperature and the third temperature difference;
and calculating the product of the chip junction temperature calculation safety coefficient, the heating power of the chip and the hardening thermal resistance of the chip for each chip in the plurality of chips, and determining the theoretical junction temperature corresponding to the chip based on the sum of the product, the cooling medium temperature and the sum value.
9. The method of claim 6, further comprising:
after simulating the plurality of chips, determining the region simulation temperature corresponding to each chip in the plurality of chips on the circuit board;
for each chip in the plurality of chips, determining a fourth temperature difference between the area simulation temperature corresponding to the chip and the environment temperature;
updating the theoretical junction temperature corresponding to each of the plurality of chips based on the fourth temperature differences corresponding to the plurality of chips, and executing the step of determining the hot air risk level corresponding to each of the plurality of chips based on the theoretical junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips again.
10. The method of any one of claims 1-9, the determining a hot air risk level for each of a plurality of chips included in a circuit board, comprising;
determining the respective crusting thermal resistances of all chips included in the circuit board;
screening a plurality of chips with the crust thermal resistance smaller than a preset thermal resistance from all the chips included in the circuit board;
and determining the hot air risk level corresponding to each of the chips with the crusting heat resistance smaller than the preset heat resistance.
11. A heat dissipation manner determining apparatus, comprising:
the first determining module is used for determining hot air risk levels corresponding to a plurality of chips included in the circuit board;
the second determining module is used for determining first target simulation heat dissipation parameters corresponding to heat dissipation bosses respectively arranged on at least part of the chips based on the hot air risk levels corresponding to the chips determined by the first determining module;
the simulation module is used for simulating the plurality of chips based on the first target simulation heat dissipation parameters determined by the second determination module by taking the circuit board as a simulation object to obtain first target simulation junction temperatures corresponding to the plurality of chips;
And the third determining module is used for determining a target heat dissipation mode of the circuit board based on the first target simulation junction temperature corresponding to each of the plurality of chips and the maximum junction temperature corresponding to each of the plurality of chips, which are obtained by the simulation module.
12. A computer-readable storage medium storing a computer program for executing the heat radiation pattern determination method according to any one of the preceding claims 1 to 10.
13. An electronic device, the electronic device comprising:
a processor;
a memory for storing the processor-executable instructions;
the processor is configured to read the executable instructions from the memory and execute the instructions to implement the heat dissipation mode determining method according to any one of the preceding claims 1-10.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320362A (en) * | 2023-11-29 | 2023-12-29 | 四川赛狄信息技术股份公司 | Heat dissipation case, determination method of heat dissipation part and signal processing equipment |
| CN117438389A (en) * | 2023-09-27 | 2024-01-23 | 杭州思拓瑞吉科技有限公司 | Uniform heat dissipation device and method for parallel connection of multiple IGBT modules |
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2023
- 2023-03-15 CN CN202310270027.1A patent/CN116301260A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117438389A (en) * | 2023-09-27 | 2024-01-23 | 杭州思拓瑞吉科技有限公司 | Uniform heat dissipation device and method for parallel connection of multiple IGBT modules |
| CN117438389B (en) * | 2023-09-27 | 2024-05-03 | 杭州思拓瑞吉科技有限公司 | Uniform heat dissipation device and method for parallel connection of multiple IGBT modules |
| CN117320362A (en) * | 2023-11-29 | 2023-12-29 | 四川赛狄信息技术股份公司 | Heat dissipation case, determination method of heat dissipation part and signal processing equipment |
| CN117320362B (en) * | 2023-11-29 | 2024-02-13 | 四川赛狄信息技术股份公司 | Heat dissipation case, determination method of heat dissipation part and signal processing equipment |
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