CN116301180A - Trimming circuit and trimming method - Google Patents
Trimming circuit and trimming method Download PDFInfo
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Abstract
The invention provides a trimming circuit and a trimming method, wherein the trimming circuit comprises: the enabling control module is used for generating and outputting a clock enabling signal according to the trimming enabling signal and the enabling off signal; a clock generation module for generating and outputting a clock signal according to the clock enable signal; the clock frequency division module is used for dividing the frequency of the clock signal and generating and outputting (n+1) bit trimming control bits; the fuse control module is used for controlling the fuse array according to the (n+1) bit trimming control bit and generating and outputting the (n+2) bit trimming bit; the reference voltage generation module is used for generating and outputting a reference voltage corresponding to the (n+2) bit trimming bit; and the comparison module is used for comparing the reference voltage with the target voltage and generating and outputting an enable turn-off signal when the reference voltage reaches the target voltage. The trimming circuit and the trimming method solve the problem that the trimming code cannot be accurately acquired by a calculation method or a table lookup method in the prior art.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a trimming circuit and a trimming method.
Background
In the field of integrated circuits, due to the influence of the distribution of the process, the parameters of the produced chips are distributed to a certain extent, and in the application with the requirement on the parameter precision, the influence of the parameter distribution is reduced by using a trimming method, so that the consistency of the parameter precision is improved, and the application requirement is met. As shown in fig. 1 and 2, the parameter value distribution before trimming is wide, and the parameter value concentration after trimming is greatly improved.
Currently known trimming means mainly include electric trimming, laser trimming, eFuse (electronic fuse) or EEROM (electrically erasable programmable read only memory) code writing trimming, in which trimming codes are generally obtained through calculation or table look-up, and then trimming is performed on the fuse through the obtained trimming codes.
The principle of the calculation method is that firstly, the measurement voltage to be trimmed is measured, the trimming step number is calculated according to the following formula, then the trimming code corresponding to the step number is obtained by looking up a table, and trimming operation is carried out; after rounding, the calculated trimming number NUM obtains trimming codes corresponding to the trimming number through table lookup, and trimming operation is performed on the fuse through the trimming codes.
Wherein NUM is the trimming step number, VREF (CP) is the measured voltage, VREF 0 For reference voltage, V STEP Is the minimum step size.
The method is simple and easy to operate, but the method is simple and easy to operate, and the method is applied to the minimum step length V STEP The consistency requirement of the formula is very high, i.e. the condition that the formula is satisfied is that the minimum step length V is the same every time trimming STEP The values of (2) are kept as consistent as possible in order to obtain an accurate trimming step number, which is difficult to handle in integrated circuit manufacturing processes.
The table look-up method is used for sorting the trimming range corresponding to each trimming code into a table through big data statistics, the trimming code is selected to trim when the measured value falls in the trimming range corresponding to the designated trimming code, compared with the calculation method, the table look-up method is used for solving the process distribution problem to a certain extent, the calculation process is omitted by directly looking up the table, and the program execution efficiency is high.
Although the table look-up method reduces the minimum step length V caused by the process distribution to a certain extent through big data statistics STEP Distribution influence of (c), but minimum step length V STEP Is always presentThe method comprises the steps of carrying out a first treatment on the surface of the When the trimming deviation is large, on one hand, the corresponding chips are few, and the trimming range lacks a statistical basis; on the other hand, due to the influence of accumulated errors, the trimming and adjusting minimum bit precision is directly covered by the errors under the condition, and under the high-precision application scene, namely, when the parameter precision is higher, the table look-up method has limitation; in addition, the condition for the table look-up is that the reference voltage VREF is used for each trimming 0 All have to be fixed when the reference voltage VREF 0 When the change is carried out, the trimming meter needs to be manufactured again, and the flexibility is greatly limited, so that the trimming meter has great limitation in the application occasions of LDO (low dropout linear voltage regulator) multi-voltage trimming or the lithium battery protection system has various protection voltages.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a trimming circuit and a trimming method for solving the problem that the trimming code cannot be accurately obtained by the calculation method or the table lookup method.
To achieve the above and other related objects, the present invention provides a trimming circuit comprising: an enabling control module, a clock generation module, a clock frequency division module, a fuse control module, a reference voltage generation module and a comparison module,
the enabling control module is used for generating and outputting a clock enabling signal according to the trimming enabling signal and the enabling off signal;
the clock generation module is connected with the output end of the enabling control module and is used for generating and outputting a clock signal according to the clock enabling signal;
the clock frequency division module is connected with the output end of the clock generation module and is used for dividing the frequency of the clock signal to generate and output (n+1) bit trimming control bits;
the fuse control module is connected with the output end of the clock frequency division module and is used for controlling the fuse array according to the (n+1) bit trimming control bit to generate and output the (n+2) bit trimming bit;
the reference voltage generation module is connected with the output end of the fuse control module and is used for generating and outputting a reference voltage corresponding to the trimming bit of the (n+2) bit;
the comparison module is connected with the output end of the reference voltage generation module and is used for comparing the reference voltage with a target voltage and generating and outputting the enabling turn-off signal when the reference voltage reaches the target voltage;
wherein n is a positive integer greater than or equal to 1.
Optionally, the clock frequency dividing module includes: (n+1) D flip-flops; the reset ends of the (n+1) D flip-flops are connected with the trimming enabling signal, the clock end of the first D flip-flop is connected with the clock signal, the clock end of the last n D flip-flops is connected with the output in-phase end of the previous D flip-flop, the data input ends of the (n+1) D flip-flops are connected with the respective output anti-phase ends, and the output in-phase end of the (n+1) D flip-flops serves as the output end of the clock frequency dividing module.
Optionally, output inverting terminals of (n+1) D flip-flops are adopted as output terminals of the clock frequency dividing module.
Optionally, the fuse control module includes: (n+1) AND gates and (n+1) fuse arrays, the fuse arrays comprising 1 fuse and 1 switch, the fuses being in series with the switches; the first input ends of the (n+1) AND gates are correspondingly connected with the (n+1) bit trimming control bit, the second input ends of the (n+1) AND gates are connected with the trimming enabling signal, and the output ends of the (n+1) AND gates are correspondingly connected with the control ends of the (n+1) switches; the (n+1) fuse arrays are connected in series and form (n+2) nodes, and the (n+2) nodes serve as output ends of the fuse control module.
Optionally, the reference voltage generating module includes a first voltage dividing resistor, a second voltage dividing resistor and (n+1) trimming resistors; the first voltage dividing resistor, (n+1) trimming resistors and the second voltage dividing resistor are connected in series between the reference voltage and the reference ground voltage to form (n+2) connecting nodes, the (n+2) connecting nodes are correspondingly connected with the trimming bit in an access mode, and the connecting node between the first voltage dividing resistor and the first trimming resistor serves as an output end of the reference voltage generating module.
Optionally, the comparison module is implemented with a comparator; the first input end of the comparator is connected with the target voltage, the second input end of the comparator is connected with the reference voltage, and the output end of the comparator is used as the output end of the comparison module.
Optionally, the trimming circuit further includes: and the target voltage generation module is used for generating and outputting the target voltage.
The invention also provides a trimming method, which comprises the following steps:
1) Generating a clock enable signal when the trimming enable signal is valid, and stopping outputting the clock enable signal when the enable off signal is valid;
2) Generating a clock signal based on the clock enable signal, dividing the clock signal and generating (n+1) bit trim control bits;
3) Performing fuse control based on the (n+1) bit and the trimming control bit to generate an (n+2) bit trimming bit, and generating a reference voltage corresponding to the trimming bit based on the (n+2) bit;
4) Comparing a reference voltage with a target voltage, generating the enable turn-off signal when the reference voltage reaches the target voltage, and obtaining a trimming code according to the enable turn-off signal, wherein the trimming code is the ratio of the effective duration of the clock enable signal to the frequency of the clock signal;
wherein n is a positive integer greater than or equal to 1.
Optionally, in the trimming process, the reference voltage is changed in a monotonically increasing manner in a descending order, or the reference voltage is changed in a monotonically decreasing manner in a descending order.
Optionally, the trimming method further includes: 5) And trimming and solidifying the fuse wire based on the trimming code.
As described above, the trimming circuit and the trimming method of the invention adopt the self-adaptive principle and the successive approximation principle to trim the reference voltage, can trim any voltage in the trimming range without trimming a table, and can completely ignore the minimum step length V STEP The accumulated error influence caused by the deviation distribution ensures that the trimming precision reaches +/-0.5V STEP The method comprises the steps of carrying out a first treatment on the surface of the Also, repairThe code tuning is determined by the ratio of the effective duration of the clock enable signal to the frequency of the clock signal, is independent of the precision of the clock signal, and can meet the high-precision system trimming requirement. The invention has simple operation, and the final trimming code can be obtained only by continuously giving out clock signals; the partial circuit can be reused as a chip circuit, only the partial circuit is needed to be additionally added, the circuit is simple, and excessive layout area is not increased.
Drawings
Fig. 1 is a schematic diagram showing a parameter value distribution before chip trimming.
Fig. 2 is a schematic diagram showing the distribution of the parameter values after the chip trimming.
Fig. 3 is a schematic diagram of the trimming circuit according to the present invention.
Fig. 4 is a schematic diagram of a clock dividing module according to the present invention.
Fig. 5 is a schematic diagram of another clock dividing module according to the present invention.
Fig. 6 is a schematic diagram of the fuse control module and the reference voltage generating module according to the present invention.
Fig. 7 is a timing chart showing related signals of the trimming circuit in the trimming process according to the present invention.
Description of element reference numerals
10. Trimming circuit
100. Enabling control module
200. Clock generating module
300. Clock frequency dividing module
400. Fuse control module
401. Fuse array
500. Reference voltage generating module
600. Comparison module
700. Target voltage generating module
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 3 to fig. 7. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 3, the present embodiment provides a trimming circuit, and the trimming circuit 10 includes: the system comprises an enabling control module 100, a clock generation module 200, a clock frequency division module 300, a fuse control module 400, a reference voltage generation module 500 and a comparison module 600. Further, the trimming circuit 10 further includes: the target voltage generation module 700.
The enable control module 100 is configured to generate and output a clock enable signal EN according to a trim enable signal TrimEN and an enable off signal SC.
Specifically, the enable control module 100 is configured to generate and output the clock enable signal EN when the trim enable signal TrimEN is valid; when the enable off signal SC is active, the output of the clock enable signal EN is stopped. In practical applications, any circuit capable of implementing the above functions is suitable for the present embodiment, and the specific circuit implementation manner of the enabling control module 100 is not limited in this embodiment.
The clock generation module 200 is connected to the output terminal of the enable control module 100, and is configured to generate and output a clock signal CLK according to the clock enable signal EN.
Specifically, the clock generation module 200 is implemented by an oscillator; the oscillator is controlled by the clock enable signal EN, and generates and outputs a clock signal CLK of a stable frequency when the clock enable signal EN is active. In practical applications, the oscillator can be multiplexed with the oscillator of the chip without additional settings.
The clock frequency division module 300 is connected to the output end of the clock generation module 200, and is configured to divide the clock signal CLK, and generate and output (n+1) bit trimming control bits CLK0-clkn; where n is a positive integer greater than or equal to 1, the value of n is determined by the number of fuses in the trimming circuit 10, that is, n=the number of fuses-1. In practical applications, the clock dividing module 300 may fully or partially multiplex the clock dividing circuit of the chip, depending on the number of dividing bits of the clock dividing circuit of the chip, and may fully multiplex if the number of dividing bits is the same, and may partially multiplex if the number of dividing bits is insufficient.
Specifically, in one example, the clock dividing module 300 includes: (n+1) D flip-flops DFF0-DFFn; wherein the reset terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the trimming enable signal TrimEN, the clock terminal of the first D flip-flop DFF0 is connected to the clock signal CLK, the clock terminals of the last n D flip-flops DFF1-DFFn are connected to the output in-phase terminal of the previous D flip-flop, the data input terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the respective output inverting terminals, and the output in-phase terminals of the (n+1) D flip-flops DFF0-DFFn are used as the output terminals of the clock frequency dividing module 300 to output (n+1) bit trimming control bits CLK0-clkn (as shown in fig. 4).
For the clock frequency division module 300 of this example, when the clock frequency division module performs multiple outputs, the plurality of trimming control bits sequentially output are monotonically and incrementally changed in order from small to large, so that the reference voltage Vref generated by the reference voltage generating module 500 subsequently is also monotonically and incrementally changed in order from small to large, so that the comparing module 600 performs the comparing operation based on the successive approximation principle.
In another example, the clock divide module 300 includes: (n+1) D flip-flops DFF0-DFFn; the reset terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the trimming enable signal TrimEN, the clock terminal of the first D flip-flop DFF0 is connected to the clock signal CLK, the clock terminal of the last n D flip-flops DFF1-DFFn is connected to the output in-phase terminal of the previous D flip-flop, the output in-phase terminal of the nth D flip-flop DFFn is suspended (i.e., not connected), the data input terminals of the (n+1) D flip-flops DFF0-DFFn are connected to the respective output inverting terminals, and the output inverting terminals of the (n+1) D flip-flops DFF0-DFFn are used as the output terminals of the clock frequency dividing module 300 to output the (n+1) bit trimming control bits CLK0-clkn (as shown in fig. 5).
For the clock frequency division module 300 of this example, when the clock frequency division module is output for multiple times, the plurality of trimming control bits output sequentially change in a monotonically decreasing manner in the order from large to small, so that the reference voltage Vref generated by the reference voltage generating module 500 subsequently also changes in a monotonically decreasing manner in the order from large to small, so that the comparing module 600 performs the comparing operation based on the successive approximation principle.
The fuse control module 400 is connected to the output end of the clock frequency division module 300, and is configured to control the fuse array 401 according to the (n+1) bits of the trimming control bits clk0-clkn, and generate and output (n+2) bits of trimming bits Fb0-Fb (n+1).
Specifically, the fuse control module 400 includes: (n+1) AND gates AND0-ANDn AND (n+1) fuse arrays 401, the fuse arrays 401 comprising 1 fuse AND 1 switch, the fuses being in series with the switches; wherein, the first input ends of the (n+1) AND gates AND0-ANDn are correspondingly connected with the (n+1) bits of the trimming control bits clk0-clkn, the second input ends of the (n+1) AND gates AND0-ANDn are connected with the trimming enabling signal TrimEN, AND the output ends of the (n+1) AND gates AND0-ANDn are correspondingly connected with the control ends of the (n+1) switches S0-Sn; the (n+1) fuse arrays 401 are connected in series and form (n+2) nodes, and the (n+2) nodes are used as the output terminals of the fuse control module 400 to output the trimming bits Fb0-Fb (n+1) (as shown in fig. 6).
In this embodiment, the and gate performs a logical and operation on the corresponding trimming control bit and trimming enable signal TrimEN, and controls the opening and closing of the corresponding switch according to the result of the logical operation, so as to simulate the programming behavior of the fuse, for example, when the corresponding switch is opened, the corresponding fuse is not connected to the subsequent reference voltage generating module 500, which corresponds to the fuse blowing behavior, and when the corresponding switch is closed, the corresponding fuse is connected to the subsequent reference voltage generating module 500, which corresponds to the fuse not blowing behavior, so as to output (n+2) bits Fb0-Fb (n+1).
The reference voltage generating module 500 is connected to the output end of the fuse control module 400, and is configured to generate and output a reference voltage Vref corresponding to the trimming bits Fb0-Fb (n+1) of the (n+2) bits.
Specifically, the reference voltage generating module 500 includes a first voltage dividing resistor R1, a second voltage dividing resistor R2, and (n+1) trimming resistors 2 0 *Rtrim-2 n * Rtrim; wherein the first voltage dividing resistor R1, (n+1) the trimming resistors 2 0 *Rtrim-2 n * Rtrim and the second voltage dividing resistor R2 are connected in series between the reference voltage Vr and the reference ground voltage VSS to form (n+2) connection nodes, the (n+2) connection nodes are correspondingly connected with the (n+2) bits of trimming bits Fb0-Fb (n+1), and the first voltage dividing resistor R1 and the first trimming resistor 2 0 * The connection node between Rtrim is used as the output terminal of the reference voltage generating module 500 for outputting the corresponding reference voltage Vref (as shown in fig. 6). More specifically, (n+1) trimming resistors have resistance values raised in an exponential power of 2, satisfying equation 2 m-1 * Rtrim, wherein m is the mth trimming resistor in the (n+1) trimming resistors, and Rtrim is a set trimming resistor value.
In this embodiment, the reference voltage generating module 500 is a resistor voltage dividing circuit, and the trimming bits Fb0-Fb (n+1) of the (n+2) bits output by the fuse control module 400 are used to control the voltage dividing ratio of the resistor voltage dividing circuit, so as to generate the reference voltage Vref corresponding to the voltage dividing ratio; wherein the minimum step length satisfies the formula
Vr is the reference voltage, R1 is the resistance of the first voltage dividing resistor, R2 is the resistance of the second voltage dividing resistor, rtrim is the set trimming resistance, and K=2 0 +2 1 +…+2 n 。
The comparison module 600 is connected to the output end of the reference voltage generation module 500, and is configured to compare a reference voltage Vref with a target voltage VS, and generate and output the enable off signal SC when the reference voltage Vref reaches the target voltage VS.
Specifically, the comparison module 600 is implemented by a comparator; the first input end of the comparator is connected to the target voltage VS, the second input end of the comparator is connected to the reference voltage Vref, and the output end of the comparator is used as the output end of the comparison module 600. Optionally, the first input terminal is a non-inverting input terminal of the comparator, and the second input terminal is an inverting input terminal of the comparator.
In this embodiment, for the case where the reference voltage Vref is monotonically increasing in order from small to large, the comparator always outputs a high level when the reference voltage Vref does not reach the target voltage VS, and the output of the comparator is inverted when the reference voltage Vref reaches the target voltage VS, that is, the output of the comparator changes from the high level to the low level, and at this time, the enable off signal SC is active. For the case that the reference voltage Vref is changed in a monotonically decreasing order from large to small, the comparator always outputs a low level when the reference voltage Vref does not reach the target voltage VS, and the output of the comparator is inverted when the reference voltage Vref reaches the target voltage VS, that is, the output of the comparator is inverted from a low level to a high level, and at this time, the enable off signal SC is valid.
The output end of the target voltage generating module 700 is connected to an input end of the comparing module 600, and is used for generating and outputting the target voltage VS.
Specifically, the target voltage generating module 700 may be implemented using a resistor divider circuit, such as in a battery management system, which may be a division of the battery voltage.
In practical applications, for the trimming circuit 10 of the present embodiment, in order to read the clock enable signal EN and the clock signal CLK to calculate a trimming code, the readout pins of the corresponding signals, such as EN pin and CLK pin, may be set; meanwhile, in order to input the trim enable signal TrimEN and generate the target voltage VS, input pins of the corresponding signals, such as the TrimEN pin and the VIN pin, may be set.
Correspondingly, the embodiment also provides a trimming method, which comprises the following steps:
1) The clock enable signal is generated when the trimming enable signal is valid, and the output of the clock enable signal is stopped when the enable off signal is valid.
2) Generating a clock signal based on the clock enable signal, dividing the clock signal and generating (n+1) bit trim control bits; wherein n is a positive integer greater than or equal to 1.
Specifically, an oscillator is used to generate a clock signal with a stable frequency; the D flip-flop is used to implement clock division to generate the (n+1) bit trim control bits. In the trimming process, when the trimming control bits are generated for a plurality of times, the trimming control bits which are sequentially generated change in a monotonically increasing way according to the sequence from small to large, or change in a monotonically decreasing way according to the sequence from large to small.
3) And performing fuse control based on the (n+1) bit and generating an (n+2) bit trimming bit, and generating a reference voltage corresponding to the trimming bit based on the (n+2) bit.
Specifically, the method for generating the reference voltage comprises the following steps: performing logic AND operation on the (n+1) bit trimming control bits and trimming enabling signals respectively, and generating (n+1) switch control signals; and controlling the opening and closing of corresponding switches in the fuse array based on the (n+1) switch control signals, so as to control whether the corresponding fuses are connected to the resistor voltage dividing circuit or not, and generating corresponding reference voltages based on resistor voltage division. In the trimming process, the reference voltage is monotonically increased in the order from small to large, or the reference voltage is monotonically decreased in the order from large to small.
4) Comparing a reference voltage with a target voltage, generating the enable-off signal when the reference voltage reaches the target voltage, and obtaining a trimming code according to the enable-off signal, wherein the trimming code is the ratio of the effective duration of the clock enable signal to the frequency of the clock signal.
Further, the trimming method further includes: 5) And trimming and solidifying the fuse wire based on the trimming code. In practical application, the trimming and fixing of the fuse wire can be realized by adopting modes such as laser, electric burning and the like.
Referring to fig. 7, a specific trimming process related to the trimming circuit and the trimming method according to the present embodiment is described with reference to fig. 3-6; taking n=3 as an example, the reference voltage monotonically increases in order from small to large.
After the chip is powered on, when the trimming enabling signal TrimEN is valid, the clock enabling signal EN is valid, and a clock signal CLK is generated; clock dividing the clock signal CLK to generate 4-bit trim control bits CLK0-CLK3 (corresponding to trimcode0[0000] -15[1111 ]); fuse control is performed based on 4-bit trimming control bits clk0-clk3, reference voltages V0-V15 are generated, and the reference voltages are compared with target voltages; when the reference voltage V13 is equal to the target voltage VS, an enable-off signal is generated to stop outputting the clock enable signal, and trimming is finished.
The trimming code is obtained by calculating the ratio of the effective duration of the clock enable signal to the frequency of the clock signal, namely, the number of pulses of the clock signal in the effective duration of the clock enable signal is 13, the number is converted into a binary number 1101, and finally, the trimming code is used for curing the fuse to finish trimming.
It should be noted that, because there is signal delay in the signal transmission and processing process, the decimal situation occurs when calculating the trimming code, and at this time, the previous integer is reserved as the trimming code.
In summary, according to the trimming circuit and the trimming method, the self-adaptive principle is combined with the successive approximation principle to trim the reference voltage, any voltage in the trimming range can be trimmed without trimming a table, and the minimum step length V can be completely ignored STEP The accumulated error influence caused by the deviation distribution ensures that the trimming precision reaches +/-0.5V STEP The method comprises the steps of carrying out a first treatment on the surface of the In addition, the trimming code is determined by the ratio of the effective duration of the clock enable signal to the frequency of the clock signal, is irrelevant to the precision of the clock signal, and can meet the high-precision system trimming requirement. The invention has simple operation, and the final trimming code can be obtained only by continuously giving out clock signals; and the partial circuit of the invention can be reused in the chipThe circuit only needs to be added with partial circuits, is simple, and does not increase excessive layout area. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A trimming circuit, the trimming circuit comprising: an enabling control module, a clock generation module, a clock frequency division module, a fuse control module, a reference voltage generation module and a comparison module,
the enabling control module is used for generating and outputting a clock enabling signal according to the trimming enabling signal and the enabling off signal;
the clock generation module is connected with the output end of the enabling control module and is used for generating and outputting a clock signal according to the clock enabling signal;
the clock frequency division module is connected with the output end of the clock generation module and is used for dividing the frequency of the clock signal to generate and output (n+1) bit trimming control bits;
the fuse control module is connected with the output end of the clock frequency division module and is used for controlling the fuse array according to the (n+1) bit trimming control bit to generate and output the (n+2) bit trimming bit;
the reference voltage generation module is connected with the output end of the fuse control module and is used for generating and outputting a reference voltage corresponding to the trimming bit of the (n+2) bit;
the comparison module is connected with the output end of the reference voltage generation module and is used for comparing the reference voltage with a target voltage and generating and outputting the enabling turn-off signal when the reference voltage reaches the target voltage;
wherein n is a positive integer greater than or equal to 1.
2. The trimming circuit of claim 1, wherein the clock divider module comprises: (n+1) D flip-flops; the reset ends of the (n+1) D flip-flops are connected with the trimming enabling signal, the clock end of the first D flip-flop is connected with the clock signal, the clock end of the last n D flip-flops is connected with the output in-phase end of the previous D flip-flop, the data input ends of the (n+1) D flip-flops are connected with the respective output anti-phase ends, and the output in-phase end of the (n+1) D flip-flops serves as the output end of the clock frequency dividing module.
3. The trimming circuit of claim 2, wherein the output inverting terminals of the (n+1) D flip-flops are used as the output terminals of the clock dividing module.
4. The trimming circuit of claim 1, wherein the fuse control module comprises: (n+1) AND gates and (n+1) fuse arrays, the fuse arrays comprising 1 fuse and 1 switch, the fuses being in series with the switches; the first input ends of the (n+1) AND gates are correspondingly connected with the (n+1) bit trimming control bit, the second input ends of the (n+1) AND gates are connected with the trimming enabling signal, and the output ends of the (n+1) AND gates are correspondingly connected with the control ends of the (n+1) switches; the (n+1) fuse arrays are connected in series and form (n+2) nodes, and the (n+2) nodes serve as output ends of the fuse control module.
5. The trimming circuit of claim 1, wherein the reference voltage generating module comprises a first voltage dividing resistor, a second voltage dividing resistor, and (n+1) trimming resistors; the first voltage dividing resistor, (n+1) trimming resistors and the second voltage dividing resistor are connected in series between the reference voltage and the reference ground voltage to form (n+2) connecting nodes, the (n+2) connecting nodes are correspondingly connected with the trimming bit in an access mode, and the connecting node between the first voltage dividing resistor and the first trimming resistor serves as an output end of the reference voltage generating module.
6. The trimming circuit of claim 1, wherein the comparison module is implemented with a comparator; the first input end of the comparator is connected with the target voltage, the second input end of the comparator is connected with the reference voltage, and the output end of the comparator is used as the output end of the comparison module.
7. The trimming circuit according to any one of claims 1-6, wherein the trimming circuit further comprises: and the target voltage generation module is used for generating and outputting the target voltage.
8. A trimming method, characterized in that the trimming method comprises:
1) Generating a clock enable signal when the trimming enable signal is valid, and stopping outputting the clock enable signal when the enable off signal is valid;
2) Generating a clock signal based on the clock enable signal, dividing the clock signal and generating (n+1) bit trim control bits;
3) Performing fuse control based on the (n+1) bit and the trimming control bit to generate an (n+2) bit trimming bit, and generating a reference voltage corresponding to the trimming bit based on the (n+2) bit;
4) Comparing a reference voltage with a target voltage, generating the enable turn-off signal when the reference voltage reaches the target voltage, and obtaining a trimming code according to the enable turn-off signal, wherein the trimming code is the ratio of the effective duration of the clock enable signal to the frequency of the clock signal;
wherein n is a positive integer greater than or equal to 1.
9. The trimming method according to claim 8, wherein the reference voltage is changed in a monotonically increasing order from small to large or the reference voltage is changed in a monotonically decreasing order from large to small during trimming.
10. The trimming method according to claim 8, wherein the trimming method further comprises: 5) And trimming and solidifying the fuse wire based on the trimming code.
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| CN202111492438.2A CN116301180A (en) | 2021-12-08 | 2021-12-08 | Trimming circuit and trimming method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117170451A (en) * | 2023-09-27 | 2023-12-05 | 深圳市迪浦电子有限公司 | Circuit and method for automatically tracking reference voltage of chip and outputting trimming code |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117170451A (en) * | 2023-09-27 | 2023-12-05 | 深圳市迪浦电子有限公司 | Circuit and method for automatically tracking reference voltage of chip and outputting trimming code |
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