CN116266760A - Polarization code encoding method and device, decoding method and device, and encoding and decoding system - Google Patents
Polarization code encoding method and device, decoding method and device, and encoding and decoding system Download PDFInfo
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Abstract
The disclosure provides a polarization code encoding method and device, a decoding method and device and a coding and decoding system, and relates to the field of coding and decoding. The present disclosure proposes an SCL decoding method based on a and v bit space dual check assist, in which a bit space executes parallel sub-segment check assist SCL decoding, when a decoding path is selected from a plurality of decoding paths to be selected, the decoding path is selected with the aid of a check code of v bit space, so that the decoding performance is prevented from being greatly reduced due to the error bit amplification effect of sub-segment transformation due to the error decoding path being selected, and the decoding performance is improved.
Description
Technical Field
The disclosure relates to the technical field of encoding and decoding, and in particular relates to a method and a device for encoding a polarization code, a method and a device for decoding the polarization code, and a polarization code encoding and decoding system.
Background
Related art proposes a sub-segment independent parallel CRC (Cyclic Redundancy Check ) assisted SCL (sequential-Cancellation List, list continuous erasure) decoding method for a polar code, dividing the polar code to be decoded into a plurality of sub-segments with equal length, performing independent SCL decoding on each sub-segment, and performing sub-segment transformation processing on each sub-segment through a decoding path (set as a bit space) selected by checking to obtain a decoding output result (set as v bit space) of the polar code. After each sub-segment is subjected to independent SCL decoding, a CRC check code is utilized to carry out sub-segment check, and after the sub-segment check, if only one alternative path passes the check, the alternative path passing the check is the sub-segment SCL decoding output; if the multiple alternative paths pass the verification, selecting the alternative path with the largest occurrence probability among the alternative paths passing the verification as sub-segment SCL decoding output; if no alternative path passes the verification, decoding and outputting the sub-segment SCL by using the alternative path with the largest occurrence probability, or starting a retransmission mechanism. Obviously, the alternative path with the largest occurrence probability is selected as the decoding output of the sub-segment SCL, and is not necessarily the correct output, and the possibility of the wrong sub-segment still exists.
It has been found that in CRC-aided SCL decoding based on the whole bit sequence, it is feasible to choose the decoding output according to the probability of occurrence. However, in sub-segment parallel based CRC-aided SCL decoding, since the a- & gtv sub-segment transform has an error bit amplification effect, once the sub-segment is selected to be erroneous, the number of error bits is multiplied.
Disclosure of Invention
The embodiment of the disclosure provides an SCL decoding method based on a and v bit space double check assistance, wherein the a bit space executes parallel sub-segment check assistance SCL decoding, when a decoding path is selected from a plurality of decoding paths to be selected, the decoding path is selected by the check code assistance of the v bit space, so that the decoding performance is greatly reduced and the decoding performance is improved due to the fact that an error decoding path is selected and the error bit amplified effect of sub-segment transformation is avoided.
Some embodiments of the present disclosure provide a polar code decoding method, including:
dividing a received bit sequence to be decoded with the length of N into m sub-segments to be decoded with the length of N, wherein N, m and N are the whole powers of 2;
respectively and independently performing list continuous deletion SCL decoding on m sub-segments to be decoded to obtain first decoding results of m a sub-segments, wherein the first decoding results of each a sub-segment have L alternative paths;
respectively carrying out a-subsection verification on L alternative paths of m a-subsections according to the verification codes in the a-subsection, screening out m groups of decoding paths to be selected, wherein each group of decoding paths to be selected comprises at least one decoding path to be selected;
each path combination consisting of one decoding path to be selected in each group in m groups of decoding paths to be selected is subjected to a-v sub-segment transformation to obtain m v sub-segments to be checked respectively;
and according to the check code of the v bit space, checking the v bit space of a v bit sequence consisting of m v subsections to be checked, and screening the v bit sequence passing the check as decoding output.
In some embodiments, the a- > v sub-segment transform on the coding side and the b- > w sub-segment transform on the coding side have the same transform form.
In some embodiments, the a→v sub-segment transform implements the sub-segment transform by an exclusive-or operation.
In some embodiments, according to the check code in the a sub-segment, a sub-segment check is performed on the L alternative paths of the m a sub-segments, and m groups of decoding paths to be selected are screened, including: and respectively carrying out a-subsection verification on L alternative paths of m a-subsections, wherein the alternative paths passing the verification are decoding paths to be selected, and if no alternative paths pass the verification, the L alternative paths of the a-subsections are all decoding paths to be selected.
In some embodiments, the a-subsection verification at the decoding side adopts a verification method corresponding to the first verification code generation operation at the encoding side; the verification of the v bit space at the decoding side adopts a verification method corresponding to the second verification code generation operation at the encoding side.
In some embodiments, the decoding side adopts the same bit sequence dividing method as the encoding side to divide the received bit sequence to be decoded with the length of N into m sub-segments to be decoded with the length of N.
Some embodiments of the present disclosure provide a polarization code encoding method, including:
dividing a first bit sequence to be coded with the length of N and containing an initial check code into m first w subsections with the length of N of w bit spaces, wherein N and m are the whole powers of 2, and n=N/m;
carrying out w-b sub-segment transformation on m first w sub-segments to obtain b sub-segments of m b bit spaces;
performing first check code generation operation on the m b sub-segments to obtain check codes of the m b sub-segments;
the check codes of m b sub-segments are respectively combined with m first w sub-segments after b-w sub-segment conversion to obtain m second w sub-segments in w bit spaces, and the a-v sub-segment conversion on the decoding side and the b-w sub-segment conversion on the encoding side have the same conversion form;
performing second check code generation operation on a w-bit sequence formed by m second w subsections to obtain a check code of the w-bit sequence;
combining the check code of the w bit sequence and the w bit sequence to obtain a second bit sequence to be coded;
and carrying out polarization code encoding on the second bit sequence to be encoded to obtain an encoded bit sequence and transmitting the encoded bit sequence.
In some embodiments, the w→b sub-segment transform and the b→w sub-segment transform implement the sub-segment transform by exclusive or operations; the b→w sub-segment transform is the inverse of the w→b sub-segment transform.
In some embodiments, the first check code generation operation or the second check code generation operation comprises a cyclic redundancy check code generation operation, a parity check code generation operation, or a cyclic redundancy check code in combination with a parity check code generation operation.
In some embodiments, the initial check code bit is 0.
In some embodiments, the b→w sub-segment conversion of the check code of the m b sub-segments and the m first w sub-segments are respectively combined to obtain the second w sub-segments of the m w bit spaces, which includes: after the check code of each b sub-segment is subjected to b-w sub-segment transformation, replacing the initial check code in the first w sub-segment corresponding to the b sub-segment to obtain a second w sub-segment.
Some embodiments of the present disclosure provide a polar code decoding apparatus, including: a memory; and a processor coupled to the memory, the processor configured to perform a polar code decoding method based on instructions stored in the memory.
Some embodiments of the present disclosure provide a polarization code encoding apparatus, including: a memory; and a processor coupled to the memory, the processor configured to perform a polar code encoding method based on instructions stored in the memory.
Some embodiments of the present disclosure provide a polarization code encoding and decoding system, including: polarization code decoding device and polarization code encoding device.
Some embodiments of the present disclosure propose a non-transitory computer readable storage medium, on which a computer program is stored, which program when being executed by a processor implements the steps of a polar code decoding method or/and a polar code encoding method.
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The drawings that are required for use in the description of the embodiments or the related art will be briefly described below. The present disclosure will be more clearly understood from the following detailed description with reference to the accompanying drawings.
It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without inventive faculty.
Fig. 1 illustrates a flow diagram of a polar code encoding method of some embodiments of the present disclosure.
Fig. 2 illustrates a flow diagram of a polar code decoding method according to some embodiments of the present disclosure.
Fig. 3 is a schematic diagram of a polarization encoding and decoding system according to some embodiments of the present disclosure.
Fig. 4 is a schematic diagram of a polarization code encoding apparatus according to some embodiments of the present disclosure.
Fig. 5 is a schematic diagram of a polar code decoding apparatus according to some embodiments of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure.
Unless specifically stated otherwise, the descriptions of "first," "second," and the like in this disclosure are used for distinguishing between different objects and are not used for indicating a meaning of size or timing, etc.
Fig. 1 illustrates a flow diagram of a chemical code encoding method of some embodiments of the present disclosure.
As shown in fig. 1, the code encoding method of this embodiment includes the following steps.
In step 110, a first bit sequence to be encoded of length N containing an initial check code is divided into m first w sub-segments of length N of w bit spaces, N and m being the whole powers of 2, n=n/m.
The first bit sequence to be encoded comprises, in addition to the initial check code, information bits to be transmitted and freeze bits. Typically, the initial check code bit is 0.
For example, a first bit sequence u to be encoded of length N containing an initial check code 1，1 N Dividing to obtain a first w sub-segment w of m w bit spaces 1，1 n， ，w 2，1 n ，w 3，1 n ，...，W m，1 n 。
In step 120, the w→b sub-segment transformation is performed on the m first w sub-segments to obtain b sub-segments of m b bit spaces.
For example, the w- > b sub-segment transformation is performed on m first w sub-segments to obtain b sub-segments b of m b bit spaces 1 n ，b 2 n ，b 3 n ，...，b m n 。
The w- & gt b sub-segment transformation and the subsequent b- & gt w sub-segment transformation realize the sub-segment transformation through exclusive OR operation. The b→w sub-segment transform is the inverse of the w→b sub-segment transform.
The w- & gt b sub-segment transformation formula is as follows:
where j=1, 2,3, n,
representing exclusive or operation, w 1j Represents the j-th bit, b, in the 1 st w-th subsection 3j The meaning of the j-th bit in the 3 rd sub-segment and the other symbols are similar and will not be explained here.
In step 130, a first check code generation operation is performed on the m b sub-segments to obtain check codes of the m b sub-segments (actual check codes of the b sub-segments).
The first check code generation operation includes a cyclic redundancy check code generation operation, a parity check code generation operation, or a cyclic redundancy check code in combination with a parity check code generation operation, and embodiments of the present disclosure are not limited to a particular check code generation operation.
In step 140, after the check codes of the m b sub-segments are transformed from the b to the w sub-segments, the check codes are respectively combined with the m first w sub-segments to obtain m second w sub-segments in w bit spaces.
After b-w sub-segment transformation is carried out on the check codes of m b sub-segments, replacing the initial check codes in the first w sub-segments corresponding to the b sub-segments to obtain a second w sub-segment w 1,2 n ,w 2,2 n ,w 3,2 n ,…,w m,2 n . The w sub-segment at this time contains the actual check code information of the b sub-segment.
In step 150, a second check code generating operation is performed on the w-bit sequence formed by the m second w sub-segments to obtain a check code of the w-bit sequence.
The second check code generation operation includes a cyclic redundancy check code generation operation, a parity check code generation operation, or a cyclic redundancy check code in combination with a parity check code generation operation, and embodiments of the present disclosure are not limited to a particular check code generation operation.
The w-bit space at this time contains w-bit space check code and b-bit space check code information.
In step 160, the check code of the w-bit sequence and the w-bit sequence are combined to obtain a second bit sequence u to be encoded 1,2 N 。
In step 170, performing polar code encoding on the second bit sequence to be encoded to obtain an encoded bit sequence x 1 N And transmits.
The embodiment of the disclosure obtains the check code of the b bit space and the check code of the w bit space, so that the check codes in two different bit spaces of b and w are obtained at the encoding side and are not in cascade connection.
The coded bit sequence at the coding side is transmitted to the decoding side through a channel, and the bit sequence to be decoded received by the decoding side is the coded bit sequence transmitted through the channel, so the bit sequence to be decoded is usually a log likelihood ratio sequence. Channel noise may be mixed in during channel transmission. Thus, the decoding side does not directly use the naming of the b/w bit space of the encoding side, but rather the naming of the a/v bit space, but it should be understood that the b bit space corresponds to the a bit space and the w bit space corresponds to the v bit space.
Fig. 2 is a flow chart illustrating a method of code decoding according to some embodiments of the disclosure.
As shown in fig. 2, the polar code decoding method of this embodiment includes the following steps.
In step 210, the received bit sequence to be decoded having a length N is divided into m sub-segments to be decoded having a length N, where N, m, N are the whole powers of 2.
The decoding side adopts the same bit sequence dividing method as the encoding side to divide the received bit sequence to be decoded with the length of N into m sub-segments to be decoded with the length of N.
For example, a bit sequence y to be decoded of length N 1 N Divided into m subsections y to be decoded 1 n ,y 2 n ,y 3 n ,…,y m n The length of each subsection to be decoded is n, and the dividing method is the same as that of the encoder side.
In step 220, the m sub-segments to be decoded are respectively and independently subjected to list continuous deletion SCL decoding, so as to obtain m first decoding results of a sub-segments, wherein each first decoding result of a sub-segment has L alternative paths.
m sub-segments to be decoded are independently decoded in parallel by m SCL decoders respectively, and L alternative paths of each a sub-segment are obtained, so that the decoding is completed in the shortest time.
In step 230, according to the check codes in the a sub-segments, a sub-segment check is performed on the L candidate paths of the m a sub-segments, and m groups of decoding paths to be selected are screened out, where each group of decoding paths to be selected includes at least one decoding path to be selected.
And respectively carrying out a-subsection verification on L alternative paths of m a-subsections, wherein the alternative paths passing the verification are decoding paths to be selected, and if no alternative paths pass the verification, the L alternative paths of the a-subsections are all decoding paths to be selected.
The a sub-segment verification of the decoding side adopts a verification method corresponding to the first verification code generation operation of the encoding side. For example, if the first check code generation operation on the encoding side is the CRC check code generation operation, the a-subsection on the decoding side is checked as the CRC check.
If more than one alternative path passes the CRC check, indicating that error detection occurs; if the correct alternative path exists in the L alternative paths but fails the CRC check, the detection omission is indicated. In general, the probability of false detection and missing detection is very small, so the number of decoding paths to be selected by m SCL decoders is not large. If the decoding paths to be selected of more than one sub-segment SCL decoder are larger than 1, respectively combining a plurality of decoding paths to be selected of different sub-segment SCL decoders, and then carrying out a sub-segment transformation and v bit sequence verification.
In step 240, each path combination consisting of one decoding path to be selected in each group in m decoding paths to be selected is subjected to a→v sub-segment transformation to obtain m v sub-segments to be checked, wherein the a→v sub-segment transformation on the decoding side and the b→w sub-segment transformation on the encoding side have the same transformation form.
The a- & gt v sub-segment transformation realizes the sub-segment transformation through exclusive OR operation.
The a- & gt v sub-segment transformation formula is as follows:
where j=1, 2,3, …, n,
representing exclusive or operation, v 1j Represents the jth bit, a, in the 1 st v subsection 3j The meaning of the j-th bit in the 3 rd sub-segment, other symbols are similar and will not be explained here.
In step 250, according to the check code of the v bit space, the v bit space is checked on the v bit sequence consisting of m v subsections to be checked, and the v bit sequence passing the check is screened out as the decoding output.
The verification of the v bit space at the decoding side adopts a verification method corresponding to the second verification code generation operation at the encoding side. For example, if the second check code generation operation on the encoding side is a CRC check code generation operation, the v-segment on the decoding side is checked as a CRC check.
According to the polarization code coding and decoding scheme of the related technology, two CRC check codes are arranged, one is used for transmission check, the other is used for auxiliary SCL decoding, and the two CRC check codes are in cascade connection and check the same bit sequence.
Unlike the related art, two check codes of the embodiments of the present disclosure are located in two different bit spaces of b and w on the encoding side, and are not in a cascade relationship, and correspondingly, are located in two different bit spaces of a and v on the decoding side, where one check code is used to assist in SCL decoding, and the other check code is used to assist in selecting the correct decoding path. Therefore, an SCL decoding method based on the double check assistance of a bit space and v bit space is realized, parallel sub-segment check assistance SCL decoding is carried out by the a bit space, when a decoding path is selected from a plurality of decoding paths to be selected, the decoding path is selected by the check assistance of the v bit space, the error decoding path is prevented from being selected, the decoding performance is greatly reduced due to the error bit amplifying effect of sub-segment transformation, and the decoding performance is improved.
Fig. 3 is a schematic diagram of a polarization encoding and decoding system according to some embodiments of the present disclosure.
As shown in fig. 3, the polarization encoding and decoding system 300 of this embodiment includes: a polarization code encoding apparatus 400 configured to perform the polarization code encoding method of each embodiment; and a polarization code decoding device 500 configured to perform the polarization code decoding method of each embodiment.
Fig. 4 is a schematic diagram of a polarization code encoding apparatus according to some embodiments of the present disclosure.
As shown in fig. 4, the polarization code encoding apparatus 400 of this embodiment includes: the memory 410 and the processor 420 coupled to the memory 410, the processor 420 is configured to execute the polarization code encoding method in any of the foregoing embodiments based on the instructions stored in the memory 410, which is not described herein.
The memory 410 may include, for example, system memory, fixed nonvolatile storage media, and the like. The system memory stores, for example, an operating system, application programs, boot Loader (Boot Loader), and other programs.
The processor 420 may be implemented as a discrete hardware component such as a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA), or other programmable logic device, discrete gates, or transistors.
The apparatus 400 may also include an input-output interface 430, a network interface 440, a storage interface 450, and the like. These interfaces 430, 440, 450 and the memory 410 and the processor 420 may be connected, for example, by a bus 460. The input/output interface 430 provides a connection interface for input/output devices such as a display, a mouse, a keyboard, a touch screen, and the like. Network interface 440 provides a connection interface for various networking devices. Storage interface 450 provides a connection interface for external storage devices such as SD cards, U-discs, and the like. Bus 460 may employ any of a variety of bus architectures. For example, bus structures include, but are not limited to, an industry standard architecture (Industry Standard Architecture, ISA) bus, a micro channel architecture (Micro Channel Architecture, MCA) bus, and a peripheral component interconnect (Peripheral Component Interconnect, PCI) bus.
Fig. 5 is a schematic diagram of a polar code decoding apparatus according to some embodiments of the present disclosure.
As shown in fig. 5, the polar code decoding apparatus 500 of this embodiment includes: the memory 510 and the processor 520 coupled to the memory 510, the processor 520 is configured to perform the polar code decoding method in any of the foregoing embodiments based on the instructions stored in the memory 510, which is not described herein.
The memory 510 may include, for example, system memory, fixed nonvolatile storage media, and the like. The system memory stores, for example, an operating system, application programs, boot Loader (Boot Loader), and other programs.
The processor 520 may be implemented as discrete hardware components such as a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA), or other programmable logic device, discrete gates, or transistors.
The apparatus 500 may also include an input-output interface 530, a network interface 540, a storage interface 550, and the like. These interfaces 530, 540, 550, as well as the memory 510 and the processor 520, may be connected by a bus 560, for example. The input/output interface 530 provides a connection interface for input/output devices such as a display, a mouse, a keyboard, a touch screen, etc. Network interface 540 provides a connection interface for various networking devices. The storage interface 550 provides a connection interface for external storage devices such as SD cards, U discs, and the like. Bus 560 may employ any of a variety of bus architectures. For example, bus structures include, but are not limited to, an industry standard architecture (Industry Standard Architecture, ISA) bus, a micro channel architecture (Micro Channel Architecture, MCA) bus, and a peripheral component interconnect (Peripheral Component Interconnect, PCI) bus.
Some embodiments of the present disclosure propose a non-transitory computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the polarization code encoding method of the embodiments or the polarization code decoding method of the embodiments.
It will be appreciated by those skilled in the art that embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more non-transitory computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer program code embodied therein.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flowchart and/or block of the flowchart illustrations and/or block diagrams, and combinations of flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the disclosure, but rather to enable any modification, equivalent replacement, improvement or the like, which fall within the spirit and principles of the present disclosure.
Claims (14)
1. A polar code decoding method comprising:
dividing a received bit sequence to be decoded with the length of N into m sub-segments to be decoded with the length of N, wherein N, m and N are the whole powers of 2;
respectively and independently performing list continuous deletion SCL decoding on m sub-segments to be decoded to obtain first decoding results of m a sub-segments, wherein the first decoding results of each a sub-segment have L alternative paths;
respectively carrying out a-subsection verification on L alternative paths of m a-subsections according to the verification codes in the a-subsection, screening out m groups of decoding paths to be selected, wherein each group of decoding paths to be selected comprises at least one decoding path to be selected;
each path combination consisting of one decoding path to be selected in each group in m groups of decoding paths to be selected is subjected to a-v sub-segment transformation to obtain m v sub-segments to be checked respectively;
and according to the check code of the v bit space, checking the v bit space of a v bit sequence consisting of m v subsections to be checked, and screening the v bit sequence passing the check as decoding output.
2. The method of claim 1, wherein the a- > v sub-segment transform on the decoding side and the b- > w sub-segment transform on the encoding side have the same transform form;
alternatively, the a→v sub-segment transform implements the sub-segment transform by exclusive or operation.
3. The method of claim 1, wherein the checking the a sub-segments for the L candidate paths of the m a sub-segments according to the check code in the a sub-segments, and the screening out m groups of decoding paths to be selected, includes:
and respectively carrying out a-subsection verification on L alternative paths of m a-subsections, wherein the alternative paths passing the verification are decoding paths to be selected, and if no alternative paths pass the verification, the L alternative paths of the a-subsections are all decoding paths to be selected.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the a sub-segment verification of the decoding side adopts a verification method corresponding to the first verification code generation operation of the encoding side;
the verification of the v bit space at the decoding side adopts a verification method corresponding to the second verification code generation operation at the encoding side.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the decoding side adopts the same bit sequence dividing method as the encoding side to divide the received bit sequence to be decoded with the length of N into m sub-segments to be decoded with the length of N.
6. A method of encoding a polarization code, comprising:
dividing a first bit sequence to be coded with the length of N and containing an initial check code into m first w subsections with the length of N of w bit spaces, wherein N and m are the whole powers of 2, and n=N/m;
carrying out w-b sub-segment transformation on m first w sub-segments to obtain b sub-segments of m b bit spaces;
performing first check code generation operation on the m b sub-segments to obtain check codes of the m b sub-segments;
the check codes of m b sub-segments are respectively combined with m first w sub-segments after b-w sub-segment conversion to obtain m second w sub-segments in w bit spaces, and the a-v sub-segment conversion on the decoding side and the b-w sub-segment conversion on the encoding side have the same conversion form;
performing second check code generation operation on a w-bit sequence formed by m second w subsections to obtain a check code of the w-bit sequence;
combining the check code of the w bit sequence and the w bit sequence to obtain a second bit sequence to be coded;
and carrying out polarization code encoding on the second bit sequence to be encoded to obtain an encoded bit sequence and transmitting the encoded bit sequence.
7. The method of claim 6, wherein the step of providing the first layer comprises,
the w-b sub-segment transformation and the b-w sub-segment transformation realize the sub-segment transformation through exclusive or operation;
the b→w sub-segment transform is the inverse of the w→b sub-segment transform.
8. The method of claim 6, wherein the step of providing the first layer comprises,
the first check code generation operation or the second check code generation operation includes a cyclic redundancy check code generation operation, a parity check code generation operation, or a cyclic redundancy check code combined with parity check code generation operation.
9. The method of claim 6, wherein the initial check code bit is 0.
10. The method of claim 6, wherein the combining the m b sub-segment check codes after b→w sub-segment conversion with the m first w sub-segments to obtain m w sub-segments of w bit spaces respectively comprises:
after the check code of each b sub-segment is subjected to b-w sub-segment transformation, replacing the initial check code in the first w sub-segment corresponding to the b sub-segment to obtain a second w sub-segment.
11. A polar code decoding apparatus comprising:
a memory; the method comprises the steps of,
a processor coupled to the memory, the processor configured to perform the polar code decoding method of any of claims 1-5 based on instructions stored in the memory.
12. A polarization code encoding apparatus comprising:
a memory; the method comprises the steps of,
a processor coupled to the memory, the processor configured to perform the polarization code encoding method of any one of claims 6-10 based on instructions stored in the memory.
13. A polarization code encoding and decoding system, comprising: the polarization code decoding device according to claim 11, and the polarization code encoding device according to claim 12.
14. A non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the polar code decoding method of any of claims 1-5 or/and the polar code encoding method of any of claims 6-10.
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