CN116266746A - Amplifying circuit with low parasitic pole effect and buffer circuit therein - Google Patents
Amplifying circuit with low parasitic pole effect and buffer circuit therein Download PDFInfo
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- CN116266746A CN116266746A CN202211232242.4A CN202211232242A CN116266746A CN 116266746 A CN116266746 A CN 116266746A CN 202211232242 A CN202211232242 A CN 202211232242A CN 116266746 A CN116266746 A CN 116266746A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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Abstract
An amplifying circuit with low parasitic pole effect and a buffer circuit therein. The amplifying circuit with low parasitic pole effect comprises: a pre-amplifier, an output transistor and a buffer circuit. The buffer circuit is used for generating a driving signal according to a pre-amplification signal generated by the pre-amplifier so as to control the output transistor. The buffer circuit includes: the buffer input transistor is used for generating a driving signal at the in-phase output end, and the input impedance of the control end of the buffer input transistor is smaller than that of the control end of the output transistor; a low output impedance circuit having an output impedance less than an inverted output impedance of the inverted output terminal of the buffer input transistor; an amplifying transistor for generating an amplified signal at an inverting output terminal thereof; the amplifying stage circuit is used for amplifying the amplified signal by an amplifying rate so that the equivalent output impedance of the in-phase output end of the buffer input transistor is smaller than or equal to the product of the intrinsic output impedance and the inverse of the amplifying rate.
Description
Technical Field
The present invention relates to an amplifying circuit, and more particularly, to an amplifying circuit with low parasitic pole effect. The invention also relates to a snubber circuit for reducing parasitic pole effects.
Background
Referring to FIG. 1, FIG. 1 shows a Low dropout linear regulator (Low-dropout regulator, LDO) of the prior art. As shown in fig. 1, in the low dropout linear regulator 1000, the amplifier 11 generates an amplified signal SA according to an input signal and a feedback loop to regulate the output voltage Vout. The amplified signal SA is used to drive the transistor M1, and when the load RL is required to have a large current I1, the actual size of the transistor M1 is also required to be large enough to generate a drain current large enough to generate a current I1 for supplying the load RL. However, the present prior art has a disadvantage in that, in order to provide the output voltage Vout with high accuracy, the gain of the amplifier 11 is relatively high, and thus the output resistance thereof is also high (the gain is proportional to the product of the conductance of the amplifier 11 and the output resistance), and the gate capacitance (input capacitance) of the transistor M1 is also relatively high because the actual size of the transistor M1 is large. When the LDO 1000 is a multi-pole system, a relatively high pole effect (i.e., a low pole frequency) is generated at the node Nm1 due to the large output resistance of the amplifier 11 and the high input capacitance of the transistor M1, which results in the problems of poor stability, difficult compensation, and poor transient response of the LDO 1000.
Compared with the prior art, the amplifying circuit with low parasitic pole effect of the invention not only can effectively reduce the parasitic pole effect, but also has the advantages of high bandwidth and high power supply rejection ratio (power supply rejection ratio, PSRR) and can realize the requirement of high system stability through the design of the buffer circuit.
Disclosure of Invention
In one aspect, the present invention provides an amplifying circuit with low parasitic pole effect, comprising: a pre-amplifier for generating a pre-amplified signal according to an input signal; an output transistor for generating an output signal according to a driving signal applied to a control terminal of the output transistor; a buffer circuit for generating the driving signal according to the pre-amplification signal, the buffer circuit comprising: a buffer input transistor configured as an in-phase follower, wherein a control terminal of the buffer input transistor is controlled by the pre-amplification signal to generate the driving signal at an in-phase output terminal of the buffer input transistor, and an inverse control signal is generated at an inverse output terminal of the buffer input transistor, and an input impedance of the control terminal of the buffer input transistor is smaller than an input impedance of the control terminal of the output transistor; a first low output impedance circuit coupled to an inverted output terminal of the buffer input transistor, wherein an output impedance of the first low output impedance circuit is smaller than an inverted output impedance of the inverted output terminal of the buffer input transistor; a first amplifying transistor controlled by the inversion control signal to generate a first amplified signal at an inversion output terminal of the first amplifying transistor; the amplifying stage circuit is used for amplifying the first amplified signal to generate a second amplified signal, wherein an amplifying rate is arranged between the second amplified signal and the reverse phase control signal, and the second amplified signal is coupled with the driving signal, so that an equivalent output impedance of the in-phase output end of the buffer input transistor is smaller than or equal to a product of an intrinsic output impedance of the in-phase output end of the buffer input transistor and the inverse of the amplifying rate.
In a preferred embodiment, a gate capacitance of the buffer input transistor is smaller than a gate capacitance of the output transistor.
In a preferred embodiment, the gate capacitance of the buffer input transistor is less than one percent of the gate capacitance of the output transistor.
In a preferred embodiment, the first low output impedance circuit is a transistor having a diode-coupled form.
In a preferred embodiment, the first amplifying transistor is a Metal-Oxide-Semiconductor (MOS) transistor or a bipolar junction transistor (bipolar junction transistor, BJT).
In a preferred embodiment, the buffer circuit further includes a second amplifying transistor, wherein the second amplifying transistor and the first amplifying transistor are of the same conductivity type or complementary conductivity type, and the first amplifying transistor and the second amplifying transistor are coupled as a homodarlington pair or a heterodarlington pair.
In a preferred embodiment, the amplifier stage circuit has an even number of inverting amplifier transistors connected in series with each other.
In a preferred embodiment, the buffer circuit further includes a second low output impedance circuit coupled to the inverting output terminal of the first amplifying transistor, wherein the output impedance of the second low output impedance circuit is smaller than an intrinsic output impedance of the inverting output terminal of the first amplifying transistor.
In a preferred embodiment, the second low output impedance circuit is a transistor having a diode-coupled form.
In a preferred embodiment, the buffer circuit further includes a first current source circuit and a second current source circuit for biasing the buffer input transistor, wherein the first current source circuit adjusts the current level of the first current source circuit according to the transient variation of the output signal to accelerate the transient response of the buffer circuit.
In a preferred embodiment, when the current level of the first current source circuit is adjusted to be increased according to the transient variation of the output signal, the output impedance of the first low output impedance circuit is further reduced accordingly, so as to accelerate the transient response and improve the stability of the amplifying circuit with low parasitic pole effect in transient.
In another aspect, the present invention also provides a buffer circuit for reducing parasitic pole effects of an amplifying circuit, for generating a driving signal according to a pre-amplification signal generated by a pre-amplifier of the amplifying circuit, wherein the driving signal is used for controlling a control terminal of an output transistor of the amplifying circuit to generate an output signal, the buffer circuit comprising: a buffer input transistor configured as an in-phase follower, wherein a control terminal of the buffer input transistor is controlled by the pre-amplification signal to generate the driving signal at an in-phase output terminal of the buffer input transistor, and an inverse control signal is generated at an inverse output terminal of the buffer input transistor, and an input impedance of the control terminal of the buffer input transistor is smaller than an input impedance of the control terminal of the output transistor; a first low output impedance circuit coupled to an inverting output of the buffer input transistor, wherein an output impedance of the first low output impedance circuit is smaller than an intrinsic output impedance of the inverting output of the buffer input transistor; a first amplifying transistor controlled by the inversion control signal to generate a first amplified signal at an inversion output terminal of the first amplifying transistor; the amplifying stage circuit is used for amplifying the first amplified signal to generate a second amplified signal, wherein an amplifying rate is arranged between the second amplified signal and the reverse phase control signal, and the second amplified signal is coupled with the driving signal, so that an equivalent output impedance of the in-phase output end of the buffer input transistor is smaller than or equal to a product of an intrinsic output impedance of the in-phase output end of the buffer input transistor and the inverse of the amplifying rate.
The objects, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of specific embodiments.
Drawings
Fig. 1 shows a prior art low dropout linear regulator.
FIG. 2 is a block diagram of an embodiment of an amplifying circuit with low parasitic pole effect according to the present invention.
FIG. 3A shows a schematic diagram of an embodiment of an amplifying circuit with low parasitic pole effect of the present invention.
Fig. 3B and 3C are schematic diagrams showing two embodiments of a first amplifying transistor in an amplifying circuit with low parasitic pole effect according to the present invention.
FIG. 4A shows a schematic diagram of an embodiment of an amplifying circuit with low parasitic pole effect of the present invention.
Fig. 4B and 4C are schematic diagrams showing two coupling embodiments of the first amplifying transistor and the second amplifying transistor in the amplifying circuit with low parasitic pole effect according to the present invention.
Fig. 5 shows a schematic diagram of an embodiment of an amplifying circuit with low parasitic pole effect of the present invention.
Fig. 6 shows a schematic diagram of an embodiment of an amplifying circuit with low parasitic pole effect of the present invention.
Description of the symbols in the drawings
11: amplifier
13: first amplifying transistor
14: second amplifying transistor
102: pre-amplifier
1000: low-dropout linear voltage regulator
24: first low output impedance circuit
25: first low output impedance circuit
202: buffer circuit
203: buffer circuit
204: buffer circuit
205: buffer circuit
206: buffer circuit
2002, 2003, 2004, 2005, 2006: amplifying circuit
34, 35, 36: amplifying stage circuit
305: output dynamic detector
46: second low output impedance circuit
I1: high current
IL: load(s)
M1: transistor with a high-voltage power supply
Mb1: first current source circuit
Mb2: second current source circuit
Mb3: third current source circuit
MN1, MN3, MN4: transistor with a high-voltage power supply
MN2: MOS transistor
Mp: output transistor
Mp2: buffer input transistor
N1: in-phase output terminal
N2: inverted output terminal
And N3: inverted output terminal
Nm1: node
Q1, Q1': BJT transistor
RL: load(s)
SA: amplifying a signal
Va1: first amplified signal
Va2: second amplified signal
Vb1, vb2: control signal
Vdynb: control signal
VEA: pre-amplification signal
Vfb: feedback signal
VG: drive signal
VG3: drive signal
VG4: drive signal
VG5: drive signal
VG6: drive signal
Vn2: inverse control signal
Vo: output signal
Vout: output voltage
Vref: reference signal
Detailed Description
The drawings in the present invention are schematic and are mainly intended to represent coupling relationships between circuits and relationships between signal waveforms, which are not drawn to scale.
Referring to fig. 2, fig. 2 shows a block diagram of an exemplary embodiment of an amplifying circuit with low parasitic pole effect (amplifying circuit 2002) according to the present invention. In one embodiment, the amplifying circuit 2002 includes: a pre-amplifier 102, an output transistor Mp, and a buffer circuit 202. In one embodiment, the pre-amplifier 102 is configured to generate the pre-amplified signal VEA according to an input signal, wherein the input signal is a feedback signal Vfb and a reference signal Vref, and the pre-amplifier 102 generates the pre-amplified signal VEA according to a difference between the feedback signal Vfb and the reference signal Vref. The buffer circuit 202 is used for generating the driving signal VG according to the pre-amplification signal VEA. The output transistor Mp is used for generating the output signal Vo according to the driving signal VG applied to the control terminal of the output transistor Mp, wherein the output transistor Mp has a larger actual size in response to the large current required by the load IL, and thus has a relatively larger input capacitance. The buffer circuit 202 has a characteristic of low input capacitance relative to the input capacitance of the output transistor Mp and low output impedance relative to the output impedance of the pre-stage amplifier 102, so that the amplifying circuit 2002 can be configured by the buffer circuit 202 to match the equivalent impedance at the output end of the pre-stage amplifier 102 with the low input capacitance of the buffer circuit 202, thereby forming a relatively low pole effect between the output end of the pre-stage amplifier 102 and the input end of the buffer circuit 202; in addition, the larger input capacitance at the control end of the output transistor Mp is matched with the relatively lower output resistance at the buffer circuit 202, so that a relatively lower pole effect is formed between the control end of the output transistor Mp and the output end of the buffer circuit 202, and the parasitic pole effect is positively correlated with the product of the capacitance and the resistance, and is negatively correlated with the bandwidth, therefore, the parasitic pole effect of the amplifying circuit 2002 can be greatly reduced, the bandwidth is improved, and the stability of the system is improved through the arrangement of the buffer circuit 202.
Referring to fig. 3A, fig. 3A shows an embodiment of an amplifying circuit with low parasitic pole effect according to the present invention (amplifying circuit 2003). The amplifying circuit 2003 of fig. 3A is similar to the amplifying circuit 2002 of fig. 2, and the buffer circuit 203 of fig. 3A is a more specific embodiment of the buffer circuit 202 of fig. 2. In one embodiment, the buffer circuit 203 is configured to generate the driving signal VG3 according to the pre-amplification signal VEA, and the buffer circuit 203 comprises: the buffer input transistor Mp2, the first amplifying transistor 13, the first current source circuit Mb1, and the third current source circuit Mb3. In one embodiment, the first current source circuit Mb1 and the third current source circuit Mb3 are used to bias the buffer input transistor Mp2 according to the control signal Vdynb and the control signal Vb1, respectively.
In one embodiment, the buffer input transistor Mp2 is configured as a same phase follower, and in the embodiment of fig. 3A, the buffer input transistor Mp2 is a Metal-Oxide-Semiconductor (MOS) transistor and is configured as a source follower. In this embodiment, the control terminal of the buffer input transistor Mp2 is controlled by the pre-amplification signal VEA to generate the driving signal VG3 at the in-phase output terminal N1 of the buffer input transistor Mp2 and generate the inverted control signal Vn2 at the inverted output terminal N2 of the buffer input transistor Mp2, and it should be noted that the in-phase and the inverted phases are correspondingly changed in-phase or inverted phase according to the change of the control terminal. In an embodiment, the actual size of the buffer input transistor Mp2 is configured to be smaller than the actual size of the output transistor Mp, so that the gate capacitance of the buffer input transistor Mp2 is smaller than the gate capacitance of the output transistor Mp, and thus the input impedance of the control terminal of the buffer input transistor Mp2 is smaller than the input impedance of the control terminal of the output transistor Mp. In one embodiment, the gate capacitance of the buffer input transistor Mp2 is much smaller than the gate capacitance of the output transistor Mp, for example, the gate capacitance of the buffer input transistor Mp2 is less than one hundredth of the gate capacitance of the output transistor Mp.
With continued reference to fig. 3A, in one embodiment, the first amplifying transistor 13 is controlled by the inversion control signal Vn2 to generate the first amplifying signal Va1 at the inversion output terminal N3 of the first amplifying transistor 13, where the first amplifying signal Va1 is inverted with respect to the input signal. In this embodiment, since the in-phase output terminal N1 of the buffer input transistor Mp2 has a smaller output resistance, and the cascade amplification of the first amplifying transistor 13 and the buffer input transistor Mp2 can further reduce the output resistance at the inverting output terminal N3 of the first amplifying transistor 13. In summary, since the buffer input transistor Mp2 has a smaller gate capacitance and the inverting output terminal N3 of the first amplifying transistor 13 has a smaller output resistance, the buffer circuit 203 can reduce parasitic pole effect between the output terminal of the pre-amplifier 102 and the control terminal of the output transistor Mp.
Referring to fig. 3B and 3C, fig. 3B and 3C show two embodiments of the first amplifying transistor in the amplifying circuit with low parasitic pole effect according to the present invention. In an embodiment, the first amplifying transistor 13 of fig. 3A may be configured as a BJT transistor Q1 shown in fig. 3B, i.e., a bipolar junction transistor (bipolar junction transistor, BJT), or as a MOS transistor MN2 shown in fig. 3C, i.e., a Metal-Oxide-Semiconductor (MOS) transistor. Specifically, when the first amplifying transistor 13 of fig. 3A is configured as the BJT transistor Q1 of fig. 3B, the equivalent impedance R of the control terminal of the output transistor Mp VG3 The following is shown:
R VG3 ≈1/[gm Mp2 (1+β)]1 (1)
Gm in 1 Mp2 The transduction gain of the input transistor Mp2 is buffered substantially, and β is the current gain of the BJT transistor Q1 substantially. Equivalent impedance R of control end of output transistor Mp shown in FIG. 1 VG3 Less than the input impedance of the control terminal of the output transistor Mp when unregulated by the buffer circuit 203.
On the other hand, when the first amplifying transistor 13 of fig. 3A is configured as the MOS transistor MN2 of fig. 3C, the equivalent impedance R of the control terminal of the output transistor Mp VG3 The following is shown:
R VG3 ≈1/(gm Mp2* gm MN2* ro) type 2
Gm in 2 MN2* ro is substantially the amplification gain of the MOS transistor MN 2. Equivalent impedance R of control end of output transistor Mp shown in fig. 2 VG3 Less than the input impedance of the control terminal of the output transistor Mp when unregulated by the buffer circuit 203.
Referring to fig. 4A, fig. 4A shows an embodiment of an amplifying circuit with low parasitic pole effect according to the present invention (amplifying circuit 2004). The amplifying circuit 2004 of fig. 4A is similar to the amplifying circuit 2003 of fig. 3A, and in one embodiment, the buffer circuit 204 is configured to generate the driving signal VG4 according to the pre-amplified signal VEA. Compared to the buffer circuit 2003, the buffer circuit 204 further includes a first low output impedance circuit 24, an amplifying stage circuit 34, and a second current source circuit Mb2. In one embodiment, the second current source circuit Mb2 is used to bias the buffer input transistor Mp2 according to the control signal Vb 2. In an embodiment, the first low output impedance circuit 24 is coupled to the inverted output terminal N2 of the buffer input transistor Mp2, wherein the output impedance of the first low output impedance circuit 24 is smaller than the inverted output impedance of the inverted output terminal N2 of the buffer input transistor Mp2, thereby reducing parasitic pole effect of the inverted output terminal N2 of the buffer input transistor Mp2 and improving system stability.
In an embodiment, the amplifying stage circuit 34 is configured to amplify the first amplifying signal Va1 to generate the second amplifying signal Va2, wherein the voltage of the first amplifying signal Va1 is in phase with the voltage of the second amplifying signal Va2, and an amplifying ratio is provided between the second amplifying signal Va2 and the inverting control signal Vn2, wherein the second amplifying signal Va2 is coupled to the driving signal VG such that an equivalent output impedance of the in-phase output terminal N1 of the buffer input transistor Mp2 is less than or equal to a product of an intrinsic output impedance of the in-phase output terminal N1 of the buffer input transistor Mp2 and an inverse of the amplifying ratio.
Referring to fig. 4A to 4C, fig. 4B and 4C show two coupling embodiments of the first amplifying transistor and the second amplifying transistor in the amplifying circuit with low parasitic pole effect according to the present invention. In one embodiment, the buffer circuit 204 in the amplifying circuit 2004 further includes the second amplifying transistor 14. As shown in fig. 4B and 4C, the second amplifying transistor 14 may be configured as a BJT transistor Q1', for example. In one embodiment, the BJT transistors Q1' and Q1 are transistors of the same conductivity type as shown in FIG. 4B and are coupled as a homodarlington pair; in another embodiment, the BJT transistors Q1' and Q1 are complementary conductive transistors as shown in FIG. 4C and are coupled as a shaped Darlington pair. In fig. 4B and 4C, the BJT transistor Q1' is used to increase the current gain of the BJT transistor.
Referring to fig. 5, fig. 5 shows an embodiment of an amplifying circuit with low parasitic pole effect according to the present invention (amplifying circuit 2005). The amplifying circuit 2005 of fig. 5 is similar to the amplifying circuit 2004 of fig. 4A. In one embodiment, the amplifying circuit 2005 further includes an output dynamic detector 305, as compared to the amplifying circuit 2004. In an embodiment, the buffer circuit 205 is configured to generate the driving signal VG5 according to the pre-stage amplified signal VEA, the first low output impedance circuit 25 in the buffer circuit 205 is configured to have a diode-coupled transistor MN1, the amplifying stage circuit 35 in the buffer circuit 205 has an even number of inverting amplifying transistors connected in series, and in the embodiment of fig. 5, the even number of inverting amplifying transistors connected in series includes a transistor MN3 and a transistor MN4. In the embodiment, since the equivalent impedance of the transistor MN1 with the diode coupling mode is low, the parasitic pole effect on the inverting output terminal N2 of the buffer input transistor Mp2 can be greatly reduced, and the system stability can be improved.
As shown in fig. 5, in one embodiment, the output dynamic detector 305 is configured to generate the control signal Vdynb according to the transient variation of the output signal Vo, and the first current source circuit Mb1 adjusts the current level of the first current source circuit Mb1 according to the control signal Vdynb, so as to accelerate the transient response of the buffer circuit 205. In an embodiment, when the current level of the first current source circuit Mb1 is adjusted to be increased according to the control signal Vdynb, the output impedance of the first low output impedance circuit 25 is further reduced due to the increase of the drain current of the transistor MN1, so as to accelerate transient response and improve the stability of the amplifying circuit with low parasitic pole effect during transient. In the embodiment of fig. 5, the equivalent impedance R of the control terminal of the output transistor Mp VG5 The following is shown:
R VG5 ≈1/(gm Mp2* gm Q1* ro * gm MN3* ro) type 3
Gm in 3 Q1* ro is substantially the amplification gain, gm, of BJT transistor Q1 MN3* ro is substantially the amplification gain of the transistor MN 3. Compared with equation 1 or equation 2 (as shown in the embodiment of FIG. 3A), the equivalent impedance R of the control terminal of the output transistor Mp shown in equation 3 VG5 It can be seen that the equivalent impedance R of the control terminal of the output transistor Mp can be made by the cascade amplification of the amplifying stage circuit 35 VG5 Greatly reduces parasitic pole effect and improves bandwidth.
Please refer to fig. 6, a diagramFig. 6 shows a schematic diagram of an embodiment of an amplifying circuit with low parasitic pole effect of the present invention (amplifying circuit 2006). The amplifying circuit 2006 of fig. 6 is similar to the amplifying circuit 2005 of fig. 5. In comparison with the amplifying circuit 2005, in an embodiment, the buffer circuit 206 is used for generating the driving signal VG6 according to the pre-amplifying signal VEA. In one embodiment, in the buffer circuit 206, the amplifying stage circuit 36 further includes a second low output impedance circuit 46 coupled to the inverting output terminal of the MOS transistor MN2, wherein the output impedance of the second low output impedance circuit 46 is smaller than the intrinsic output impedance of the inverting output terminal of the MOS transistor MN2 (the first amplifying transistor 13), thereby reducing parasitic pole effect on the first amplifying signal Va 1. In one embodiment, the second low output impedance circuit 46 is a transistor MN5 having a diode-coupled form. In the embodiment of fig. 6, the equivalent impedance R of the control terminal of the output transistor Mp VG6 The following is shown:
R VG6 ≈1/(gm Mp2* gm MN3* ro)
the present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of easily understanding the present invention by those skilled in the art, and is not intended to limit the scope of the claims of the present invention. The embodiments described are not limited to single applications but may be combined, for example, two or more embodiments may be combined, and portions of one embodiment may be substituted for corresponding components of another embodiment. In addition, various equivalent changes and various combinations will be apparent to those skilled in the art, and for example, the term "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the processing or calculating based on the signal itself, but includes performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling conversion of the signal, if necessary, and then processing or calculating based on the converted signal to generate an output result. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described herein, embody the principles of the invention and are thus equally well suited to the particular use contemplated. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations.
Claims (19)
1. An amplifying circuit with low parasitic pole effect, comprising:
a pre-amplifier for generating a pre-amplified signal according to an input signal;
an output transistor for generating an output signal according to a driving signal applied to a control terminal of the output transistor; and
a buffer circuit for generating the driving signal according to the pre-amplification signal, the buffer circuit comprising:
a buffer input transistor configured as an in-phase follower, wherein a control terminal of the buffer input transistor is controlled by the pre-amplification signal to generate the driving signal at an in-phase output terminal of the buffer input transistor, and an inverse control signal is generated at an inverse output terminal of the buffer input transistor, and an input impedance of the control terminal of the buffer input transistor is smaller than an input impedance of the control terminal of the output transistor;
a first low output impedance circuit coupled to an inverted output terminal of the buffer input transistor, wherein an output impedance of the first low output impedance circuit is smaller than an inverted output impedance of the inverted output terminal of the buffer input transistor;
a first amplifying transistor controlled by the inversion control signal to generate a first amplified signal at an inversion output terminal of the first amplifying transistor; and
the amplifying stage circuit is used for amplifying the first amplified signal to generate a second amplified signal, wherein an amplifying rate is arranged between the second amplified signal and the reverse phase control signal, and the second amplified signal is coupled with the driving signal, so that an equivalent output impedance of the in-phase output end of the buffer input transistor is smaller than or equal to a product of an intrinsic output impedance of the in-phase output end of the buffer input transistor and the inverse of the amplifying rate.
2. The amplifying circuit with low parasitic pole effect of claim 1, wherein a gate capacitance of the buffer input transistor is smaller than a gate capacitance of the output transistor.
3. The amplifying circuit with low parasitic pole effect of claim 2, wherein the gate capacitance of the buffer input transistor is less than one percent of the gate capacitance of the output transistor.
4. The amplifying circuit with low parasitic pole effect of claim 1, wherein the first low output impedance circuit is a transistor with diode coupling.
5. The amplifying circuit with low parasitic pole effect according to claim 1, wherein the first amplifying transistor is a metal oxide semiconductor transistor or a bipolar junction transistor.
6. The amplifying circuit with low parasitic pole effect according to claim 1, wherein the buffer circuit further comprises a second amplifying transistor, wherein the second amplifying transistor and the first amplifying transistor are of the same conductivity type or complementary conductivity type, wherein the first amplifying transistor and the second amplifying transistor are coupled as a homodarlington pair or a heterodarlington pair.
7. The amplifying circuit with low parasitic pole effect of claim 1, wherein the amplifying stage circuit has an even number of inverting amplifying transistors connected in series with each other.
8. The amplifying circuit with low parasitic pole effect as in claim 1, wherein the buffer circuit further comprises a second low output impedance circuit coupled to the inverting output of the first amplifying transistor, wherein the output impedance of the second low output impedance circuit is less than an intrinsic output impedance of the inverting output of the first amplifying transistor.
9. The amplifying circuit with low parasitic pole effect of claim 8, wherein the second low output impedance circuit is a transistor with diode coupling.
10. The amplifying circuit with low parasitic pole effect as in claim 1, wherein the buffer circuit further comprises a first current source circuit and a second current source circuit for biasing the buffer input transistor, wherein the first current source circuit adjusts the current level of the first current source circuit according to the transient variation of the output signal to accelerate the transient response of the buffer circuit.
11. The amplifying circuit with low parasitic pole effect as in claim 10, wherein when the current level of the first current source circuit is adjusted to be increased by the first current source circuit according to the transient variation of the output signal, the output impedance of the first low output impedance circuit is further reduced accordingly, thereby accelerating transient response and improving the stability of the amplifying circuit with low parasitic pole effect at transient.
12. A buffer circuit for reducing parasitic pole effects of an amplifying circuit, for generating a driving signal according to a pre-amplification signal generated by a pre-amplifier of the amplifying circuit, wherein the driving signal is used for controlling a control terminal of an output transistor of the amplifying circuit to generate an output signal, the buffer circuit comprising:
a buffer input transistor configured as an in-phase follower, wherein a control terminal of the buffer input transistor is controlled by the pre-amplification signal to generate the driving signal at an in-phase output terminal of the buffer input transistor, and an inverse control signal is generated at an inverse output terminal of the buffer input transistor, and an input impedance of the control terminal of the buffer input transistor is smaller than an input impedance of the control terminal of the output transistor;
a first low output impedance circuit coupled to an inverting output of the buffer input transistor, wherein an output impedance of the first low output impedance circuit is smaller than an intrinsic output impedance of the inverting output of the buffer input transistor;
a first amplifying transistor controlled by the inversion control signal to generate a first amplified signal at an inversion output terminal of the first amplifying transistor; and
the amplifying stage circuit is used for amplifying the first amplified signal to generate a second amplified signal, wherein an amplifying rate is arranged between the second amplified signal and the reverse phase control signal, and the second amplified signal is coupled with the driving signal, so that an equivalent output impedance of the in-phase output end of the buffer input transistor is smaller than or equal to a product of an intrinsic output impedance of the in-phase output end of the buffer input transistor and the inverse of the amplifying rate.
13. The buffer circuit of claim 12, wherein a gate capacitance of the buffer input transistor is less than a gate capacitance of the output transistor.
14. The buffer circuit of claim 12, wherein the first low output impedance circuit is a transistor having a diode-coupled form.
15. The buffer circuit of claim 12, wherein the first amplifying transistor is a metal oxide semiconductor transistor or a bipolar junction transistor.
16. The buffer circuit of claim 12, further comprising a second amplifying transistor, wherein the second amplifying transistor and the first amplifying transistor are of the same conductivity type or complementary conductivity type, wherein the first amplifying transistor and the second amplifying transistor are coupled as a homodarlington pair or a heterodarlington pair.
17. The buffer circuit of claim 12, wherein the amplifier stage circuit has an even number of inverting amplifier transistors connected in series with each other.
18. The buffer circuit of claim 12, further comprising a second low output impedance circuit coupled to the inverting output of the first amplifying transistor, wherein the output impedance of the second low output impedance circuit is less than an intrinsic output impedance of the inverting output of the first amplifying transistor.
19. The buffer circuit of claim 12, further comprising a first current source circuit and a second current source circuit for biasing the buffer input transistor, wherein the first current source circuit adjusts a current level of the first current source circuit according to the transient variation of the output signal to accelerate the transient response of the buffer circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163290648P | 2021-12-16 | 2021-12-16 | |
| US63/290,648 | 2021-12-16 |
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| CN116266746A true CN116266746A (en) | 2023-06-20 |
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| CN202211232242.4A Pending CN116266746A (en) | 2021-12-16 | 2022-10-10 | Amplifying circuit with low parasitic pole effect and buffer circuit therein |
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| Country | Link |
|---|---|
| CN (1) | CN116266746A (en) |
| TW (1) | TWI805500B (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5861736A (en) * | 1994-12-01 | 1999-01-19 | Texas Instruments Incorporated | Circuit and method for regulating a voltage |
| US8179108B2 (en) * | 2009-08-02 | 2012-05-15 | Freescale Semiconductor, Inc. | Regulator having phase compensation circuit |
| TW201530299A (en) * | 2014-01-20 | 2015-08-01 | Richtek Technology Corp | Control method of power management circuit |
| CN104181972B (en) * | 2014-09-05 | 2015-12-30 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with high PSRR characteristic |
| CN207488871U (en) * | 2017-12-08 | 2018-06-12 | 成都市海芯微纳电子科技有限公司 | A kind of CMOS low pressure difference linear voltage regulators using novel buffer |
| US10915121B2 (en) * | 2018-02-19 | 2021-02-09 | Texas Instruments Incorporated | Low dropout regulator (LDO) with frequency-dependent resistance device for pole tracking compensation |
| TWI666538B (en) * | 2018-04-24 | 2019-07-21 | 瑞昱半導體股份有限公司 | Voltage regulator and voltage regulating method |
-
2022
- 2022-09-30 TW TW111137336A patent/TWI805500B/en active
- 2022-10-10 CN CN202211232242.4A patent/CN116266746A/en active Pending
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| Publication number | Publication date |
|---|---|
| TWI805500B (en) | 2023-06-11 |
| TW202327258A (en) | 2023-07-01 |
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