CN116266541A - Wafer bonding structure and forming method thereof - Google Patents

Wafer bonding structure and forming method thereof Download PDF

Info

Publication number
CN116266541A
CN116266541A CN202111541406.7A CN202111541406A CN116266541A CN 116266541 A CN116266541 A CN 116266541A CN 202111541406 A CN202111541406 A CN 202111541406A CN 116266541 A CN116266541 A CN 116266541A
Authority
CN
China
Prior art keywords
wafer
dielectric layer
layer
metal
functional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111541406.7A
Other languages
Chinese (zh)
Inventor
刘清召
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202111541406.7A priority Critical patent/CN116266541A/en
Publication of CN116266541A publication Critical patent/CN116266541A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bonding area, e.g. marks, spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application provides a wafer bonding structure and a forming method thereof, wherein the structure comprises the following components: the bottom wafer is provided with a second dielectric layer on the surface, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer; the third dielectric layer is positioned on the surface of the second dielectric layer, and a first redistribution layer penetrating through the third dielectric layer, extending to the second dielectric layer and electrically connecting the second metal layer is formed in the third dielectric layer; a first dielectric layer is formed on the second surface of the functional wafer, and a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer; the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer are aligned and bonded through the first metal bonding mark and the second metal bonding mark. The wafer bonding structure and the forming method thereof can improve the wafer alignment precision without affecting the process complexity.

Description

Wafer bonding structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a wafer bonding structure and a method for forming the same.
Background
There are generally two wafer alignment schemes in current wafer bonding processes. One solution is pitch alignment, i.e. by using the pitch of the wafer itself as an alignment reference, but this solution has low alignment accuracy, especially the electrical connection between wafers after multi-layer wafer bonding is affected. Another approach is to use specific bond marks for wafer alignment, with higher alignment accuracy, but alignment accuracy is dependent on the sharpness of the alignment marks.
Current alignment marks include metallic bond marks and non-metallic bond marks. The metal bonding mark is completely opaque, so that the contrast ratio is high during bonding, the metal bonding mark is easy to identify, and the alignment precision is high. The nonmetallic binding marks are formed by etching grooves in the dielectric layers, and identifiable marks are formed by utilizing the thickness difference of the dielectric layers. Thus, the definition and alignment accuracy of the non-metallic bond marks are related to their etch depth and dielectric layer thickness.
However, in the bonding requirement of the functional wafer, the thickness difference (Totalthickness variation, TTV) of the wafer surface is required to be as small as possible so as to ensure that the wafer can be bonded smoothly. To reduce the TTV, multiple mechanical lapping (CMP) is required, which reduces the thickness of the dielectric layer, which in turn affects the alignment accuracy of the nonmetallic-bonded-marks. Therefore, there is a need to provide a more efficient and reliable solution.
Disclosure of Invention
The wafer bonding structure and the forming method thereof can improve the wafer alignment precision without affecting the process complexity.
One aspect of the present application provides a method for forming a wafer bonding structure, including: providing a bonded carrier wafer and a functional wafer, wherein a first face of the functional wafer is bonded with a first face of the carrier wafer; forming a first dielectric layer on a second surface of the functional wafer, and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer, wherein the first metal bonding mark is formed in a process of manufacturing the first redistribution layer; providing a bottom wafer, wherein a second dielectric layer is formed on the surface of the bottom wafer, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer; forming a third dielectric layer on the surface of the second dielectric layer; forming a first redistribution layer in the third dielectric layer extending through the third dielectric layer to the second dielectric layer and electrically connecting the second metal layer; aligning the functional wafer and the bottom wafer through the first metal bonding mark and the second metal bonding mark, bonding a first dielectric layer of the functional wafer and a third dielectric layer of the bottom wafer, and electrically connecting the first redistribution layer and the second redistribution layer; and removing the carrier wafer.
In some embodiments of the present application, a method for forming a first dielectric layer on a second side of the functional wafer and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer includes: forming a first dielectric layer on the second surface of the functional wafer; forming a first opening and a second opening in the first dielectric layer; depositing a metal material layer on the surface of the first dielectric layer and in the first opening and the second opening; the metal material layer is polished until the first dielectric layer is exposed, and a second redistribution layer and a first metal bonding mark are formed in the first opening and the second opening, respectively.
In some embodiments of the present application, the second metal bond mark is formed in a process of making the second metal layer.
In some embodiments of the present application, the first metal bond mark is located on the scribe line and the second metal bond mark is located on the scribe line.
In some embodiments of the present application, a buffer layer and an etching stop layer are further formed between the second surface of the functional wafer and the first dielectric layer in sequence.
In some embodiments of the present application, the first side of the functional wafer is further formed with a functional dielectric layer, and the functional dielectric layer is further formed with a first metal layer.
In some embodiments of the present application, the method further comprises: forming a through silicon via structure penetrating the functional dielectric layer and the functional wafer and extending into the first dielectric layer to electrically connect the second redistribution layer; forming a third redistribution layer in the functional dielectric layer electrically connected to the first metal layer; providing a stacked wafer, wherein a first surface of the stacked wafer is provided with a stacked dielectric layer, and a fourth redistribution layer and a third metal bonding mark are formed in the stacked dielectric layer, wherein the third metal bonding mark is formed in a process of manufacturing the fourth redistribution layer; and aligning and bonding the stacked wafer and the functional wafer through the third metal bonding mark and the first metal bonding mark, wherein the fourth redistribution layer is electrically connected with the third redistribution layer and the through silicon via structure.
Another aspect of the present application also provides a wafer bonding structure, including: the bottom wafer is provided with a second dielectric layer on the surface, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer; the third dielectric layer is positioned on the surface of the second dielectric layer, and a first redistribution layer penetrating through the third dielectric layer, extending to the second dielectric layer and electrically connecting the second metal layer is formed in the third dielectric layer; a first dielectric layer is formed on the second surface of the functional wafer, and a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer; the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer are aligned and bonded by the first metal bonding mark and the second metal bonding mark, wherein the first redistribution layer and the second redistribution layer are electrically connected.
In some embodiments of the present application, the first metal bond mark is located on the scribe line and the second metal bond mark is located on the scribe line.
In some embodiments of the present application, a buffer layer and an etching stop layer are further formed between the second surface of the functional wafer and the first dielectric layer in sequence.
In some embodiments of the present application, the first side of the functional wafer is further formed with a functional dielectric layer, and the functional dielectric layer is further formed with a first metal layer.
In some embodiments of the present application, the structure further comprises: a through silicon via structure extending through the functional dielectric layer and the functional wafer into the first dielectric layer to electrically connect the second redistribution layer; a third redistribution layer in the functional dielectric layer electrically connected to the first metal layer; a stacked wafer, wherein a first surface of the stacked wafer is provided with a stacked dielectric layer, and a fourth redistribution layer and a third metal bonding mark are formed in the stacked dielectric layer; the stacked wafer and the functional wafer are aligned and bonded by the third metal bond mark and the first metal bond mark, wherein the fourth redistribution layer electrically connects the third redistribution layer and the through-silicon via structure.
The application provides a wafer bonding structure and a forming method thereof, wherein a first redistribution layer originally positioned on a bottom wafer is formed on a functional wafer, and then a first metal bonding mark is synchronously formed when the first redistribution layer is formed, so that the wafer alignment precision can be improved under the condition of not affecting the process complexity.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale.
Wherein:
FIG. 1 is a flow chart of a method for forming a wafer bonding structure according to an embodiment of the present application;
fig. 2 to 15 are schematic structural diagrams illustrating steps in a method for forming a wafer bonding structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
Fig. 1 is a flowchart of a method for forming a wafer bonding structure according to an embodiment of the present application.
An embodiment of the present application provides a method for forming a wafer bonding structure, as shown in fig. 1, including:
step S1: providing a bonded carrier wafer and a functional wafer, wherein a first face of the functional wafer is bonded with a first face of the carrier wafer;
step S2: forming a first dielectric layer on a second surface of the functional wafer, and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer, wherein the first metal bonding mark is formed in a process of manufacturing the first redistribution layer;
step S3: providing a bottom wafer, wherein a second dielectric layer is formed on the surface of the bottom wafer, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer;
step S4: forming a third dielectric layer on the surface of the second dielectric layer;
step S5: forming a first redistribution layer in the third dielectric layer extending through the third dielectric layer to the second dielectric layer and electrically connecting the second metal layer;
step S6: aligning the functional wafer and the bottom wafer through the first metal bonding mark and the second metal bonding mark, bonding a first dielectric layer of the functional wafer and a third dielectric layer of the bottom wafer, and electrically connecting the first redistribution layer and the second redistribution layer;
step S7: and removing the carrier wafer.
Fig. 2 to 15 are schematic structural diagrams illustrating steps in a method for forming a wafer bonding structure according to an embodiment of the present application. The method for forming the wafer bonding structure according to the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 1 and 2, step S1 provides a bonded carrier wafer 100 and a functional wafer 200, a first side of the functional wafer 200 being bonded to a first side of the carrier wafer 100.
In some embodiments of the present application, the first side of the functional wafer 200 is further formed with a functional dielectric layer 210, and a first metal layer 220 is further formed in the functional dielectric layer 210. The first metal layer 220 is used to electrically connect active devices (not shown) in the functional wafer 200.
In some embodiments of the present application, the carrier wafer 100 is a semiconductor wafer. The carrier wafer 100 is used to carry the functional wafer 200.
In some embodiments of the present application, the functional wafer 200 is a semiconductor wafer. The functional wafer 200 is, for example, a wafer carrying memory chips.
In some embodiments of the present application, the first side of the carrier wafer 100 further forms a carrier dielectric layer (not shown in the figure for the sake of brevity), in which a non-metallic bonding mark (not shown in the figure for the sake of brevity) is formed, and the functional dielectric layer 210 further forms a metallic bonding mark (not shown in the figure for the sake of brevity) corresponding to the non-metallic bonding mark. The first side of the carrier wafer 100 and the first side of the functional wafer 200 are aligned and bonded by the non-metallic bonding marks and the metallic bonding marks. Wherein the metal bonding mark is formed simultaneously with the first metal layer 220.
In some embodiments of the present application, a trimming process is further required to perform the functional wafer 200 and the functional dielectric layer 220 to remove a portion of the edges of the functional wafer 200 and the functional dielectric layer 220. The steps of the trimming process are omitted in the embodiments of the present application for the sake of brevity.
With continued reference to fig. 1 and 3-6, step S2 forms a first dielectric layer 250 on the second side of the functional wafer 200, and forms a second redistribution layer 260 and a first metal bond mark 270 in the first dielectric layer 250, wherein the first metal bond mark 270 is formed during the process of fabricating the first redistribution layer 260.
In some embodiments of the present application, a buffer layer 230 and an etching stop layer 240 are further formed between the second surface of the functional wafer 200 and the first dielectric layer 250 in sequence.
Referring to fig. 3, a buffer layer 230, an etch stop layer 240, and a first dielectric layer 250 are sequentially formed on the second surface of the functional wafer 200.
In some embodiments of the present application, the material of the buffer layer 240 is silicon oxide, and the method for forming the buffer layer 240 includes a chemical vapor deposition process or a physical vapor deposition process. The etch stop layer 240 cannot be formed directly on the second side of the functional wafer 200, and thus the buffer layer 240 is used to grow the etch stop layer 240.
In some embodiments of the present application, the material of the etching stop layer 240 is silicon nitride, and the method for forming the etching stop layer 240 includes a chemical vapor deposition process or a physical vapor deposition process. The etching stop layer 240 is used for etching the first dielectric layer 250 as an etching stop layer in the subsequent steps, so that the depth of the first opening and the second opening formed by etching are uniform.
In some embodiments of the present application, the material of the first dielectric layer 250 is silicon oxide, and the method for forming the first dielectric layer 250 includes a chemical vapor deposition process or a physical vapor deposition process. The first dielectric layer 250 is used to form a second redistribution layer 260 and a first metal bond mark 270.
A first opening 251 and a second opening 252 are formed in the first dielectric layer 250 as shown with reference to fig. 4.
In some embodiments of the present application, a method of forming a first opening 251 and a second opening 252 in the first dielectric layer 250 includes: forming a patterned photoresist layer on the surface of the first dielectric layer 250, wherein the patterned photoresist layer defines the positions of the first opening 251 and the second opening 252; etching the first dielectric layer 250 to the etching stop layer 240 by using the patterned photoresist layer as a mask to form the first opening 251 and the second opening 252; and removing the patterned photoresist layer.
Referring to fig. 5, a metal material layer 253 is deposited on the surface of the first dielectric layer 250 and in the first and second openings 251 and 252.
In some embodiments of the present application, the metal material layer 253 is copper or tungsten. The method of forming the metal material layer 253 includes a chemical vapor deposition process, a physical vapor deposition process, or the like.
Referring to fig. 6, the metal material layer 253 is polished until the first dielectric layer 250 is exposed, forming a second redistribution layer 260 and a first metal bonding mark 270 in the first opening 251 and the second opening 252, respectively. The first metal bonding marks 270 are formed simultaneously during the formation of the second redistribution layer 260, so that the first metal bonding marks 270 do not increase process complexity, additional material loss, and cost.
In some embodiments of the present application, the first metal bond marks 270 are located on the scribe line, so the first metal bond marks 270 do not affect the routing layout of the second redistribution layer 260.
In the conventional process, the non-metal bonding marks are formed in the first dielectric layer 250, however, since the thickness uniformity of the first dielectric layer 250 is difficult to control, the alignment accuracy of the formed non-metal bonding marks is poor. If the metal bonding marks are directly formed in the first dielectric layer 250, the process flow is increased, the process is more complex, the material loss is increased, and the cost is increased. In the technical scheme of the application, the second redistribution layer originally positioned on the bottom wafer is adjusted to the functional wafer, then the first metal bonding mark is formed at the same time of forming the second redistribution layer, and the alignment precision is improved by using the first metal bonding mark under the condition of not increasing the complexity and the cost of the process.
With continued reference to fig. 1 and 7, step S3: a bottom wafer 300 is provided, a second dielectric layer 310 is formed on the surface of the bottom wafer 300, and a second metal layer 320 and a second metal bonding mark 330 are formed in the second dielectric layer 310.
In some embodiments of the present application, the bottom wafer 300 is a semiconductor wafer. The bottom wafer 300 has logic chips formed therein, for example.
In some embodiments of the present application, the material of the second dielectric layer 310 is silicon oxide, and the method for forming the second dielectric layer 310 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the second metal layer 320 is used to electrically connect active devices (not shown in the figures) in the bottom wafer 300.
In some embodiments of the present application, the second metal bonding mark 330 is located on the scribe line, so the second metal bonding mark 330 does not affect the routing layout of the second metal layer 320.
In some embodiments of the present application, the second metal bonding mark 330 is formed in a process of fabricating the second metal layer 320. That is, the second metal bonding marks 330 are formed simultaneously during the process of forming the second metal layer 320, so that the second metal bonding marks 330 do not increase the complexity of the process, and there is no additional material loss and no increase in cost.
With continued reference to fig. 1 and 8, in step S4, a third dielectric layer 340 is formed on the surface of the second dielectric layer 310.
In some embodiments of the present application, the material of the third dielectric layer 340 is silicon oxide, and the method for forming the third dielectric layer 340 includes a chemical vapor deposition process or a physical vapor deposition process. The third dielectric layer 340 is used to form a first redistribution layer.
With continued reference to fig. 1 and 9, at step S5, a first redistribution layer 350 is formed in the third dielectric layer 340, extending through the third dielectric layer 340 to the second dielectric layer 310 and electrically connecting the second metal layer 320.
In some embodiments of the present application, the material of the first redistribution layer 350 is copper or tungsten. The method of forming the first redistribution layer 350 includes an electroplating process.
In conventional processes, after the first redistribution layer 350 is formed, a second redistribution layer may continue to be formed on the first redistribution layer 350. However, the process of fabricating the second redistribution layer is performed in a high temperature environment that heats the bottom wafer 300, affecting the device reliability of the bottom wafer 300. In the technical solution of the present application, the second redistribution layer is fabricated on the functional wafer 200, so that the heat treatment on the bottom wafer 300 is reduced, the devices of the bottom wafer 300 can be more stable, and the yield is improved.
With continued reference to fig. 1 and 10, step S6: the first dielectric layer 250 of the functional wafer 200 and the third dielectric layer 310 of the bottom wafer 300 are bonded and the first redistribution layer 350 and the second redistribution layer 260 are electrically connected by aligning the first metal bonding mark 270 and the second metal bonding mark 330 with the functional wafer 200 and the bottom wafer 300.
In the technical solution of the present application, the first redistribution layer 260 originally located on the bottom wafer is formed on the functional wafer 200, and then the first metal bonding marks 270 are formed synchronously when the first redistribution layer 260 is formed, so that the alignment accuracy of the functional wafer 200 and the bottom wafer 300 can be improved without affecting the process complexity.
With continued reference to fig. 1 and 11, in step S7, the carrier wafer 100 is removed. Methods of removing the carrier wafer 100 include chemical mechanical polishing processes and etching processes.
With continued reference to fig. 12, the technical solution of the present application further includes: a through-silicon via structure 400 is formed through the functional dielectric layer 210 and functional wafer 200 and extends into the first dielectric layer 250 electrically connecting the second redistribution layer 260.
With continued reference to fig. 13, the technical solution of the present application further includes: a third redistribution layer 410 is formed in the functional dielectric layer 210 electrically connected to the first metal layer 220.
With continued reference to fig. 14, the technical solution of the present application further includes: a stacked wafer 500 is provided, a stacked dielectric layer 510 is formed on a first side of the stacked wafer 500, and a fourth redistribution layer 520 and a third metal bonding mark 530 are formed in the stacked dielectric layer 510, wherein the third metal bonding mark 530 is formed in a process of manufacturing the fourth redistribution layer 520.
With continued reference to fig. 15, the technical solution of the present application further includes: the stacked wafer 500 and the functional wafer 200 are aligned and bonded by the third metal bond mark 530 and the first metal bond mark 270, wherein the fourth redistribution layer 520 electrically connects the third redistribution layer 220 and the through-silicon via structure 400.
In the technical solution of the present application, the fourth redistribution layer 520 originally located on the functional wafer is formed on the stacked wafer 500, and then the third metal bonding mark 530 is formed synchronously when the fourth redistribution layer 520 is formed, so that the alignment accuracy of the functional wafer 200 and the stacked wafer 500 can be improved without affecting the process complexity.
In the technical scheme of the application, the multi-layer bonding structure of the multi-layer wafer stack can be formed by repeating the steps, and the alignment precision of each layer of wafer can be improved.
The application provides a method for forming a wafer bonding structure, which forms a first redistribution layer originally positioned on a bottom wafer on a functional wafer, and then synchronously forms a first metal bonding mark when forming the first redistribution layer, so that the wafer alignment precision can be improved under the condition of not affecting the process complexity.
The embodiment of the present application further provides a wafer bonding structure, as shown in fig. 15, including: a bottom wafer 300, wherein a second dielectric layer 310 is formed on the surface of the bottom wafer 300, and a second metal layer 320 and a second metal bonding mark 330 are formed in the second dielectric layer 310; a third dielectric layer 340 located on the surface of the second dielectric layer 310, wherein a first redistribution layer 350 penetrating through the third dielectric layer 340 and extending to the second dielectric layer 310 and electrically connecting the second metal layer 320 is formed in the third dielectric layer 340; a functional wafer 200, wherein a first dielectric layer 250 is formed on a second surface of the functional wafer 200, and a second redistribution layer 260 and a first metal bonding mark 270 are formed in the first dielectric layer 250; the first dielectric layer 250 of the functional wafer 200 and the third dielectric layer 310 of the bottom wafer 300 are aligned and bonded by the first metal bond mark 270 and the second metal bond mark 330, wherein the first redistribution layer 350 and the second redistribution layer 260 are electrically connected.
In some embodiments of the present application, the first side of the functional wafer 200 is further formed with a functional dielectric layer 210, and a first metal layer 220 is further formed in the functional dielectric layer 210. The first metal layer 220 is used to electrically connect active devices (not shown) in the functional wafer 200.
In some embodiments of the present application, the carrier wafer 100 is a semiconductor wafer. The carrier wafer 100 is used to carry the functional wafer 200.
In some embodiments of the present application, the functional wafer 200 is a semiconductor wafer. The functional wafer 200 is, for example, a wafer carrying memory chips.
In some embodiments of the present application, the first side of the carrier wafer 100 further forms a carrier dielectric layer (not shown in the figure for the sake of brevity), in which a non-metallic bonding mark (not shown in the figure for the sake of brevity) is formed, and the functional dielectric layer 210 further forms a metallic bonding mark (not shown in the figure for the sake of brevity) corresponding to the non-metallic bonding mark. The first side of the carrier wafer 100 and the first side of the functional wafer 200 are aligned and bonded by the non-metallic bonding marks and the metallic bonding marks. Wherein the metal bonding mark is formed simultaneously with the first metal layer 220.
In some embodiments of the present application, a buffer layer 230 and an etching stop layer 240 are further formed between the second surface of the functional wafer 200 and the first dielectric layer 250 in sequence.
In some embodiments of the present application, the material of the buffer layer 240 is silicon oxide. The etch stop layer 240 cannot be formed directly on the second side of the functional wafer 200, and thus the buffer layer 240 is used to grow the etch stop layer 240.
In some embodiments of the present application, the material of the etch stop layer 240 is silicon nitride. The etch stop layer 240 serves to make the depth of the subsequently formed second redistribution layer 260 and first metal bond marks 270 uniform.
In some embodiments of the present application, the material of the first dielectric layer 250 is silicon oxide, and the first dielectric layer 250 is used to form the second redistribution layer 260 and the first metal bond marks 270.
In some embodiments of the present application, the first metal bonding marks 270 are formed simultaneously during the formation of the second redistribution layer 260, so that the first metal bonding marks 270 do not increase process complexity, do not have additional material loss, and do not increase cost.
In some embodiments of the present application, the first metal bond marks 270 are located on the scribe line, so the first metal bond marks 270 do not affect the routing layout of the second redistribution layer 260.
In the conventional process, the non-metal bonding marks are formed in the first dielectric layer 250, however, since the thickness uniformity of the first dielectric layer 250 is difficult to control, the alignment accuracy of the formed non-metal bonding marks is poor. If the metal bonding marks are directly formed in the first dielectric layer 250, the process flow is increased, the process is more complex, the material loss is increased, and the cost is increased. In the technical scheme of the application, the second redistribution layer originally positioned on the bottom wafer is adjusted to the functional wafer, then the first metal bonding mark is formed at the same time of forming the second redistribution layer, and the alignment precision is improved by using the first metal bonding mark under the condition of not increasing the complexity and the cost of the process.
In some embodiments of the present application, the bottom wafer 300 is a semiconductor wafer. The bottom wafer 300 has logic chips formed therein, for example.
In some embodiments of the present application, the material of the second dielectric layer 310 is silicon oxide.
In some embodiments of the present application, the second metal layer 320 is used to electrically connect active devices (not shown in the figures) in the bottom wafer 300.
In some embodiments of the present application, the second metal bonding mark 330 is located on the scribe line, so the second metal bonding mark 330 does not affect the routing layout of the second metal layer 320.
In some embodiments of the present application, the second metal bonding mark 330 is formed in a process of fabricating the second metal layer 320. That is, the second metal bonding marks 330 are formed simultaneously during the process of forming the second metal layer 320, so that the second metal bonding marks 330 do not increase the complexity of the process, and there is no additional material loss and no increase in cost.
In some embodiments of the present application, the material of the third dielectric layer 340 is silicon oxide, and the third dielectric layer 340 is used to form the first redistribution layer.
In some embodiments of the present application, the material of the first redistribution layer 350 is copper or tungsten.
In conventional processes, after the first redistribution layer 350 is formed, a second redistribution layer may continue to be formed on the first redistribution layer 350. However, the process of fabricating the second redistribution layer is performed in a high temperature environment that heats the bottom wafer 300, affecting the device reliability of the bottom wafer 300. In the technical solution of the present application, the second redistribution layer is fabricated on the functional wafer 200, so that the heat treatment on the bottom wafer 300 is reduced, the devices of the bottom wafer 300 can be more stable, and the yield is improved.
The first dielectric layer 250 of the functional wafer 200 and the third dielectric layer 310 of the bottom wafer 300 are aligned and bonded by the first metal bonding mark 270 and the second metal bonding mark 330.
In the technical solution of the present application, the first redistribution layer 260 originally located on the bottom wafer is formed on the functional wafer 200, and then the first metal bonding marks 270 are formed synchronously when the first redistribution layer 260 is formed, so that the alignment accuracy of the functional wafer 200 and the bottom wafer 300 can be improved without affecting the process complexity.
The technical scheme of this application still includes: a through silicon via structure 400 extending through the functional dielectric layer 210 and the functional wafer 200 and into the first dielectric layer 250 electrically connecting the second redistribution layer 260; a third redistribution layer 410 located in the functional dielectric layer 210 and electrically connected to the first metal layer 220; a stacked wafer 500, wherein a stacked dielectric layer 510 is formed on a first surface of the stacked wafer 500, and a fourth redistribution layer 520 and a third metal bonding mark 530 are formed in the stacked dielectric layer 510, wherein the third metal bonding mark 530 is formed in a process of manufacturing the fourth redistribution layer 520; the stacked wafer 500 and the functional wafer 200 are aligned and bonded by the third metal bond mark 530 and the first metal bond mark 270, wherein the fourth redistribution layer 520 electrically connects the third redistribution layer 220 and the through-silicon via structure 400.
In the technical solution of the present application, the fourth redistribution layer 520 originally located on the functional wafer is formed on the stacked wafer 500, and then the third metal bonding mark 530 is formed synchronously when the fourth redistribution layer 520 is formed, so that the alignment accuracy of the functional wafer 200 and the stacked wafer 500 can be improved without affecting the process complexity.
The application provides a wafer bonding structure and a forming method thereof, wherein a first redistribution layer originally positioned on a bottom wafer is formed on a functional wafer, and then a first metal bonding mark is synchronously formed when the first redistribution layer is formed, so that the wafer alignment precision can be improved under the condition of not affecting the process complexity.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (12)

1. A method for forming a wafer bonding structure, comprising:
providing a bonded carrier wafer and a functional wafer, wherein a first face of the functional wafer is bonded with a first face of the carrier wafer;
forming a first dielectric layer on a second surface of the functional wafer, and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer, wherein the first metal bonding mark is formed in a process of manufacturing the first redistribution layer;
providing a bottom wafer, wherein a second dielectric layer is formed on the surface of the bottom wafer, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer;
forming a third dielectric layer on the surface of the second dielectric layer;
forming a first redistribution layer in the third dielectric layer extending through the third dielectric layer to the second dielectric layer and electrically connecting the second metal layer;
aligning the functional wafer and the bottom wafer through the first metal bonding mark and the second metal bonding mark, bonding a first dielectric layer of the functional wafer and a third dielectric layer of the bottom wafer, and electrically connecting the first redistribution layer and the second redistribution layer;
and removing the carrier wafer.
2. The method of forming a wafer bonding structure of claim 1, wherein forming a first dielectric layer on the second side of the functional wafer and forming a second redistribution layer and a first metal bonding mark in the first dielectric layer comprises:
forming a first dielectric layer on the second surface of the functional wafer;
forming a first opening and a second opening in the first dielectric layer;
depositing a metal material layer on the surface of the first dielectric layer and in the first opening and the second opening;
the metal material layer is polished until the first dielectric layer is exposed, and a second redistribution layer and a first metal bonding mark are formed in the first opening and the second opening, respectively.
3. The method of claim 1, wherein the second metal bond mark is formed during a process of forming the second metal layer.
4. The method of claim 1, wherein the first metal bond mark is located on a scribe line and the second metal bond mark is located on a scribe line.
5. The method of claim 1, wherein a buffer layer and an etch stop layer are further sequentially formed between the second surface of the functional wafer and the first dielectric layer.
6. The method of claim 1, wherein the first side of the functional wafer further comprises a functional dielectric layer, and wherein the functional dielectric layer further comprises a first metal layer.
7. The method of forming a wafer bonding structure according to claim 6, further comprising:
forming a through silicon via structure penetrating the functional dielectric layer and the functional wafer and extending into the first dielectric layer to electrically connect the second redistribution layer;
forming a third redistribution layer in the functional dielectric layer electrically connected to the first metal layer;
providing a stacked wafer, wherein a first surface of the stacked wafer is provided with a stacked dielectric layer, and a fourth redistribution layer and a third metal bonding mark are formed in the stacked dielectric layer, wherein the third metal bonding mark is formed in a process of manufacturing the fourth redistribution layer;
and aligning and bonding the stacked wafer and the functional wafer through the third metal bonding mark and the first metal bonding mark, wherein the fourth redistribution layer is electrically connected with the third redistribution layer and the through silicon via structure.
8. A wafer bonding structure, comprising:
the bottom wafer is provided with a second dielectric layer on the surface, and a second metal layer and a second metal bonding mark are formed in the second dielectric layer;
the third dielectric layer is positioned on the surface of the second dielectric layer, and a first redistribution layer penetrating through the third dielectric layer, extending to the second dielectric layer and electrically connecting the second metal layer is formed in the third dielectric layer;
a first dielectric layer is formed on the second surface of the functional wafer, and a second redistribution layer and a first metal bonding mark are formed in the first dielectric layer;
the first dielectric layer of the functional wafer and the third dielectric layer of the bottom wafer are aligned and bonded by the first metal bonding mark and the second metal bonding mark, wherein the first redistribution layer and the second redistribution layer are electrically connected.
9. The wafer bonding structure of claim 8 wherein the first metal bond mark is located on a scribe line and the second metal bond mark is located on a scribe line.
10. The wafer bonding structure of claim 8, wherein a buffer layer and an etch stop layer are further formed in sequence between the second side of the functional wafer and the first dielectric layer.
11. The wafer bonding structure of claim 8, wherein the first side of the functional wafer further has a functional dielectric layer formed therein, the functional dielectric layer further having a first metal layer formed therein.
12. The wafer bonding structure of claim 11, further comprising:
a through silicon via structure extending through the functional dielectric layer and the functional wafer into the first dielectric layer to electrically connect the second redistribution layer;
a third redistribution layer in the functional dielectric layer electrically connected to the first metal layer;
a stacked wafer, wherein a first surface of the stacked wafer is provided with a stacked dielectric layer, and a fourth redistribution layer and a third metal bonding mark are formed in the stacked dielectric layer;
the stacked wafer and the functional wafer are aligned and bonded by the third metal bond mark and the first metal bond mark, wherein the fourth redistribution layer electrically connects the third redistribution layer and the through-silicon via structure.
CN202111541406.7A 2021-12-16 2021-12-16 Wafer bonding structure and forming method thereof Pending CN116266541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111541406.7A CN116266541A (en) 2021-12-16 2021-12-16 Wafer bonding structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111541406.7A CN116266541A (en) 2021-12-16 2021-12-16 Wafer bonding structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN116266541A true CN116266541A (en) 2023-06-20

Family

ID=86743054

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111541406.7A Pending CN116266541A (en) 2021-12-16 2021-12-16 Wafer bonding structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN116266541A (en)

Similar Documents

Publication Publication Date Title
US7341938B2 (en) Single mask via method and device
CN105575890B (en) Semiconductor device and method for manufacturing semiconductor device
US8383460B1 (en) Method for fabricating through substrate vias in semiconductor substrate
US8222121B2 (en) Fiducial scheme adapted for stacked integrated circuits
US20050224921A1 (en) Method for bonding wafers to produce stacked integrated circuits
CN109390305B (en) Bonding wafer and preparation method thereof
JP6175701B2 (en) Manufacturing method of 3D multi-chip module
US7781887B2 (en) Semiconductor device including an interconnect
JPH08213548A (en) Manufacture of three-dimensional integrated circuit
CN103887226A (en) Wafer stacking structure, method of manufacturing the same, and method of manufacturing wafers
US9236359B2 (en) System and method for 3D integrated circuit stacking
EP2672511B1 (en) 3d stacked multichip module and method of fabrication
CN116266541A (en) Wafer bonding structure and forming method thereof
CN114999983A (en) Manufacturing method of bonding mark, bonding wafer, carrier wafer and bonding method
CN101273437B (en) Integrated circuit devices with trenches having different depth
CN116264183A (en) Forming method of through silicon via structure
US10903069B2 (en) Method of fabricating layered structure
CN107293484A (en) One kind switching board fabrication method
CN108231599A (en) Improve the method for wafer surface flatness uniformity
CN117894744A (en) Wafer bonding structure and forming method thereof
CN114864419A (en) Carrier wafer and method for removing carrier wafer in bonding structure
CN117976555A (en) Wafer bonding structure and forming method thereof
CN102832144B (en) The formation of metal coupling
AU2004286545B2 (en) Single mask via method and device
CN114023726A (en) Semiconductor structure and method for forming semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination