CN116264183A - Forming method of through silicon via structure - Google Patents

Forming method of through silicon via structure Download PDF

Info

Publication number
CN116264183A
CN116264183A CN202111533963.4A CN202111533963A CN116264183A CN 116264183 A CN116264183 A CN 116264183A CN 202111533963 A CN202111533963 A CN 202111533963A CN 116264183 A CN116264183 A CN 116264183A
Authority
CN
China
Prior art keywords
layer
wafer
silicon via
functional
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111533963.4A
Other languages
Chinese (zh)
Inventor
刘清召
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Semiconductor Manufacturing International Tianjin Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Semiconductor Manufacturing International Tianjin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp, Semiconductor Manufacturing International Tianjin Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202111533963.4A priority Critical patent/CN116264183A/en
Publication of CN116264183A publication Critical patent/CN116264183A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application provides a method for forming a through silicon via structure, which comprises the following steps: providing a carrier wafer, wherein a hard mask layer and a first bonding mark layer are sequentially formed on the surface of the carrier wafer; bonding the carrier wafer and the first surface of the functional wafer through the bonding mark layer; providing a bottom wafer, wherein a first dielectric layer and a first metal layer positioned in the first dielectric layer are formed on the surface of the bottom wafer; bonding the bottom wafer and the second face of the functional wafer; removing the carrier wafer; etching the first bonding mark layer and the functional wafer by taking the hard mask layer as a mask to form a through silicon hole penetrating through the first bonding mark layer and the functional wafer and exposing the first metal layer; and filling metal in the through silicon via to form a through silicon via structure. The method for forming the through silicon via structure can improve the density of the through silicon via structure and the electrical signal interconnection density between functional wafers.

Description

Forming method of through silicon via structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for forming a through silicon via structure.
Background
In the multi-layer stacked wafer, the stacked wafers (hereinafter, referred to as functional wafers) are electrically connected by Through Silicon Vias (TSVs). The TSV size directly affects the electrical signal interconnect density between wafers, so the cross-sectional view of the TSV structure is as close to rectangular as possible, rather than inverted trapezoidal, to achieve precise control of the TSV core size (critical dimension).
Because the TSV structure is deeper, a thicker dielectric layer is required to be deposited as a hard mask layer in addition to photoresist used as a mask in etching to form the through silicon via. Only when the thickness of the hard mask layer is thicker, the accurate control of the TSV core size can be realized. However, in the current technology, the hard mask layer is formed on the bottom wafer and the functional wafer bonded together, which limits the thickness of the hard mask layer because the functional wafer and the bottom wafer are already thicker.
Therefore, there is a need to provide a more efficient and reliable solution.
Disclosure of Invention
The method for forming the through silicon via structure can improve the thickness of the hard mask layer, so that the core size of the through silicon via structure is accurately controlled, the density of the through silicon via structure is further improved, and the electrical signal interconnection density between functional wafers is improved.
The application provides a method for forming a through silicon via structure, which comprises the following steps: providing a carrier wafer, wherein a hard mask layer and a first bonding mark layer are sequentially formed on the surface of the carrier wafer; bonding the carrier wafer and the first surface of the functional wafer through the bonding mark layer; providing a bottom wafer, wherein a first dielectric layer and a first metal layer positioned in the first dielectric layer are formed on the surface of the bottom wafer; bonding the bottom wafer and the second face of the functional wafer; removing the carrier wafer; etching the first bonding mark layer and the functional wafer by taking the hard mask layer as a mask to form a through silicon hole penetrating through the first bonding mark layer and the functional wafer and exposing the first metal layer; and filling metal in the through silicon via to form a through silicon via structure.
In some embodiments of the present application, an adhesion layer and a first etching stop layer are further formed between the carrier wafer surface and the hard mask layer in sequence, and a second etching stop layer is further formed between the hard mask layer and the first bonding mark layer.
In some embodiments of the present application, the thickness of the adhesion layer is 50 to 200 angstroms and the thickness of the first bonding marking layer is 3000 to 5000 angstroms.
In some embodiments of the present application, the hard mask layer has a thickness of 10000 to 40000 angstroms, the first etch stop layer has a thickness of 500 to 2000 angstroms, and the second etch stop layer has a thickness of 50 to 500 angstroms.
In some embodiments of the present application, the hard mask layer has a thickness of 10000 to 30000 angstroms, the first etch stop layer has a thickness of 1000 to 5000 angstroms, and the second etch stop layer has a thickness of 1000 to 2000 angstroms.
In some embodiments of the present application, the adhesion layer is also removed when the carrier wafer is removed.
In some embodiments of the present application, the first side of the functional wafer is further formed with a second bonding mark layer, and the carrier wafer and the first side of the functional wafer are bonded through the first bonding mark layer and the second bonding mark layer.
In some embodiments of the present application, after bonding the carrier wafer and the first surface of the functional wafer by the bonding mark layer, the method further includes: and thinning the functional wafer.
In some embodiments of the present application, the second side of the functional wafer is formed with a third bonding mark layer.
In some embodiments of the present application, a third etching stop layer and a fourth bonding mark layer are further formed on the surface of the first dielectric layer of the bottom wafer in sequence, and the bottom wafer and the second face of the functional wafer are bonded through the third bonding mark layer and the fourth bonding mark layer.
In some embodiments of the present application, the method for etching the first bonding mark layer and the functional wafer with the hard mask layer as a mask to form a through silicon via penetrating the first bonding mark layer and the functional wafer and exposing the first metal layer includes: forming a patterned photoresist layer on the surface of the first etching stop layer, wherein the patterned photoresist layer defines the position of the through silicon via; first etching the first etching stop layer, the hard mask layer, the second etching stop layer and the first bonding mark layer by taking the patterned photoresist layer as a mask until the first surface of the functional wafer is exposed to form a silicon through hole; second etching the functional wafer along the through silicon via until the third bonding mark layer is exposed; third etching the third bonding mark layer and the fourth bonding mark layer along the through silicon via until the third etching stop layer is exposed; and etching the third etching stop layer along the through silicon via until the first metal layer is exposed.
In some embodiments of the present application, third etching the third bonding marker layer and the fourth bonding marker layer along the through silicon via further comprises, after exposing the third etch stop layer: and forming a barrier layer on the side wall and the bottom of the through silicon via.
In some embodiments of the present application, the third etch stop layer is etched fourth along the through-silicon via to expose the first metal layer, and the barrier layer at the bottom of the through-silicon via is also etched.
The application provides a forming method of a through silicon via structure, which comprises the steps of manufacturing a hard mask layer on a carrier wafer, bonding the hard mask layer to a functional wafer, and improving the thickness of the hard mask layer, so that the core size of the through silicon via structure is accurately controlled, the density of the through silicon via structure is further improved, and the electrical signal interconnection density between the functional wafers is improved.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale.
Wherein:
FIG. 1 is a cross-sectional view of a through silicon via structure;
FIG. 2 is a plan view of a through silicon via structure;
FIG. 3 is a cross-sectional view of another through silicon via structure;
FIG. 4 is a plan view of another through silicon via structure;
fig. 5 is a flowchart of a method for forming a through-silicon via structure according to an embodiment of the present application;
fig. 6 to 17 are schematic structural diagrams illustrating steps in a method for forming a through-silicon via structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
Fig. 1 is a cross-sectional view of a through silicon via structure. Fig. 2 is a plan view of a through silicon via structure. It should be noted that fig. 1 and fig. 2 are only simplified schematic diagrams for concisely illustrating the shape and distribution of the through-silicon via structure.
Referring to fig. 1, a through silicon via structure 110 is formed in a wafer 100. The cross-sectional pattern of the through-silicon via structure 110 is rectangular, and the three-dimensional shape of the through-silicon via structure 110 is cylindrical. The upper surface of the through-silicon via structure 110 has the same dimensions as the lower surface of the through-silicon via structure 110.
Referring to fig. 2, fig. 2 illustrates the distribution of the through-silicon via structures 110 on the surface of the wafer 100. The through silicon via structures 110 are uniformly distributed on the surface of the wafer 100.
Fig. 3 is a cross-sectional view of another through silicon via structure. Fig. 4 is a plan view of another through silicon via structure. It should be noted that fig. 3 and fig. 4 are only simplified schematic diagrams for concisely illustrating the shape and distribution of the through-silicon via structure.
Referring to fig. 3, a through silicon via structure 210 is formed in a wafer 200. The cross-sectional pattern of the through-silicon via structure 210 is an inverted trapezoid, and the three-dimensional shape of the through-silicon via structure 210 is an inverted truncated cone shape. The upper surface dimension of the through-silicon via structure 210 is greater than the lower surface dimension of the through-silicon via structure 210.
Referring to fig. 4, fig. 4 illustrates the distribution of the through-silicon via structures 210 on the surface of the wafer 200. The through silicon via structures 210 are uniformly distributed on the surface of the wafer 200.
As can be seen by comparing fig. 1 and 3, the upper surface dimension of the through-silicon via structure 210 shown in fig. 3 is larger than the upper surface dimension of the through-silicon via structure 110 shown in fig. 1 in the case of the same core dimension (i.e., the case of the same lower surface dimension of the through-silicon via structure). Further, as can be seen by comparing fig. 2 and fig. 4, the distribution density of the through-silicon via structures 210 in fig. 4 is less than the distribution density of the through-silicon via structures 110 in fig. 1, where the wafer surface areas are the same. That is, the through silicon via structure 110 shown in fig. 1 and 2 has a high distribution density, and can improve the electrical signal interconnection density between functional wafers.
In fabricating through silicon via structures using an etching process, it is necessary to use the hard mask layer as a mask for etching. The thicker the hard mask layer, the closer the shape of the fabricated through-silicon via structure is to the shape of the through-silicon via structure 110 shown in fig. 1. That is, the thicker the hard mask layer is, the more the core size of the through silicon via structure is controlled, the more the distribution density of the through silicon via structure can be improved, and the electrical signal interconnection density between the functional wafers is further improved.
However, in the current technology, the hard mask layer is formed on the bottom wafer and the functional wafer bonded together, the thicker the hard mask layer is, the greater the stress of the hard mask layer on the functional wafer and the bottom wafer is, which results in serious wafer warpage. Thus, thicker hard mask layers cannot be formed on functional wafers at present, which limits the improvement of through-silicon via structures.
In view of the above, the present application provides a method for forming a through-silicon via structure, in which a hard mask layer is fabricated on a carrier wafer, and then the hard mask layer is bonded to a functional wafer, so that the thickness of the hard mask layer can be increased, thereby precisely controlling the core size of the through-silicon via structure, further increasing the density of the through-silicon via structure, and increasing the electrical signal interconnection density between the functional wafers.
Fig. 5 is a flowchart of a method for forming a through-silicon via structure according to an embodiment of the present application.
An embodiment of the present application provides a method for forming a through silicon via structure, as shown in fig. 5, including:
step S1: providing a carrier wafer, wherein a hard mask layer and a first bonding mark layer are sequentially formed on the surface of the carrier wafer;
step S2: bonding the carrier wafer and the first surface of the functional wafer through the bonding mark layer;
step S3: providing a bottom wafer, wherein a first dielectric layer and a first metal layer positioned in the first dielectric layer are formed on the surface of the bottom wafer;
step S4: bonding the bottom wafer and the second face of the functional wafer;
step S5: removing the carrier wafer;
step S6: etching the first bonding mark layer and the functional wafer by taking the hard mask layer as a mask to form a through silicon hole penetrating through the first bonding mark layer and the functional wafer and exposing the first metal layer;
step S7: and filling metal in the through silicon via to form a through silicon via structure.
Fig. 6 to 17 are schematic structural diagrams illustrating steps in a method for forming a through-silicon via structure according to an embodiment of the present application. The method for forming the through-silicon via structure according to the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 5 and 6, in step S1, a carrier wafer 300 is provided, and a hard mask layer 330 and a first bonding mark layer 350 are sequentially formed on the surface of the carrier wafer 300. The hard mask layer 330 is used as a mask for etching processes during subsequent fabrication of the through-silicon via structure. The first bonding mark layer 350 serves as a bonding interface for bonding the carrier wafer 300 to a functional wafer later. The first bonding mark layer 350 has bonding marks (not shown) formed therein for alignment.
In the conventional process, a carrier wafer and a functional wafer are bonded first, then the functional wafer and a bottom wafer are bonded, then the carrier wafer is removed, then a hard mask layer is formed on the functional wafer and the bottom wafer, and then the functional wafer is etched by taking the hard mask layer as a mask to manufacture a through silicon via structure. Because the hard mask layer is formed on the functional wafer and the bottom wafer, and the fabrication process of the hard mask layer is completed in a high temperature environment (about 400 degrees celsius), this results in the functional wafer and the bottom wafer also being thermally processed at the same time, which affects the device performance on the functional wafer and the bottom wafer, and reduces the device reliability. In addition, the thicknesses of the functional wafer and the bottom wafer are thicker, the whole warpage of the wafer is higher, and the compressive stress of the hard mask layer on the functional wafer and the bottom wafer further aggravates the whole warpage of the wafer, and the subsequent process is influenced, so that the thickness of the hard mask layer cannot be further increased, and the improvement of the through-silicon via structure is limited.
In the solution of the present application, however, the hard mask layer 330 is not formed on the functional wafer and the bottom wafer, but is formed on the carrier wafer 300 and then bonded to the functional wafer together with the carrier wafer 300. Therefore, the functional wafer and the bottom wafer are not affected by the heat treatment. In addition, the hard mask layer 330 is bonded to the functional wafer after being rotated 180 degrees, and the stress direction of the hard mask layer 330 to the functional wafer is also rotated 180 degrees, so that the hard mask layer 330 does not aggravate the warpage of the functional wafer and the bottom wafer, but can neutralize the stress to alleviate the warpage of the functional wafer and the bottom wafer. Moreover, because the hard mask layer 330 does not increase the warpage of the functional wafer and the bottom wafer, the thickness of the hard mask layer 330 may be thicker, so that the through-silicon via structure can be improved, that is, the cross-sectional shape of the through-silicon via structure is more rectangular, so that the distribution density of the through-silicon via structure is improved, and the electrical signal interconnection density between the functional wafers is further improved.
In some embodiments of the present application, the carrier wafer 300 is, for example, a semiconductor wafer or a glass wafer. The carrier wafer 300 serves as a carrier for carrying the functional wafer.
In some embodiments of the present application, an adhesion layer 310 and a first etching stop layer 320 are further formed between the surface of the carrier wafer 300 and the hard mask layer 330 in sequence, and a second etching stop layer 340 is further formed between the hard mask layer 330 and the first bonding mark layer 350.
The first etch stop layer 320 is used to protect the hard mask layer 330 from damage when the carrier wafer 300 and the adhesion layer 310 are removed in a subsequent process. The material of the first etching stop layer 320 is, for example, silicon nitride. The first etching stop layer 320 is formed by a chemical vapor deposition process or a physical vapor deposition process.
The adhesion layer 310 serves as a substrate for depositing the first etch stop layer 320. The material of the first etch stop layer 320 is silicon nitride, which cannot be formed directly on the surface of the silicon wafer (i.e., the carrier wafer 300). The adhesion layer 310 is required as an intermediate medium to form the first etch stop layer 320. The material of the adhesion layer 310 is, for example, silicon oxide. The adhesion layer 310 is formed by, for example, a chemical vapor deposition process or a physical vapor deposition process.
The second etch stop layer 340 serves to protect the hard mask layer 330 from damage when forming the bond marks in the first bond mark layer 350, on the one hand, and to improve depth uniformity of the bond marks in the first bond mark layer 350, on the other hand. The material of the second etching stop layer 340 is, for example, silicon nitride. The second etching stop layer 340 is formed by a chemical vapor deposition process or a physical vapor deposition process, for example.
In some embodiments of the present application, the thickness of the adhesion layer 310 is 50 to 200 angstroms and the thickness of the first bonding mark layer 350 is 3000 to 5000 angstroms.
In some embodiments of the present application, the hard mask layer 330 has a thickness of 10000 to 40000 angstroms, the first etch stop layer 320 has a thickness of 500 to 2000 angstroms, and the second etch stop layer 340 has a thickness of 50 to 500 angstroms. Since the hard mask layer 330 is formed on the carrier wafer 300 in the technical solution of the present application, the thickness of the hard mask layer 330 may be thicker.
In other embodiments of the present application, the first etch stop layer 320 and the second etch stop layer 340 may also function as an etch mask as the hard mask layer 330. In turn, the thickness of the hard mask layer 330 may be reduced, and then the thicknesses of the first and second etch stop layers 320 and 340 may be increased. Specifically, the thickness of the hard mask layer 330 is 10000 to 30000 angstroms, the thickness of the first etch stop layer 320 is 1000 to 5000 angstroms, and the thickness of the second etch stop layer 340 is 1000 to 2000 angstroms.
With continued reference to fig. 5 and 7, in step S2, the carrier wafer 300 and the first side of the functional wafer 400 are bonded by the bonding mark layer 350. The functional wafer 400 is, for example, a semiconductor wafer.
In some embodiments of the present application, the first side of the functional wafer 400 is further formed with a second bonding mark layer 410, and the carrier wafer 300 and the first side of the functional wafer 400 are bonded through the first bonding mark layer 350 and the second bonding mark layer 410. The second bonding mark layer 410 has bonding marks (not shown) formed therein for alignment. The material of the second bonding mark layer 410 is, for example, silicon oxide. The second bonding mark layer 410 is formed by a chemical vapor deposition process, a physical vapor deposition process, or the like.
In some embodiments of the present application, other film layers (omitted herein for brevity) are also formed between the functional wafer 400 and the second bonding mark layer 410. Such as an etch stop layer below the second bond mark layer 410, a metal interconnect layer on the surface of the functional wafer 400, and device structures on the functional wafer 400.
In some embodiments of the present application, it is further necessary to perform an edging process on the functional wafer 400 to remove a portion of the edge of the functional wafer 400 and the second bonding mark layer 410 located on the functional wafer 400. For the sake of brevity, the trimming process is omitted in this application.
Referring to fig. 8, in some embodiments of the present application, after the carrier wafer 300 and the first surface of the functional wafer 400 are bonded by the bonding mark layer 350, the method further includes: the functional wafer 400 is thinned. The method of thinning the functional wafer 400 includes a chemical mechanical polishing process.
In some embodiments of the present application, the second side of the functional wafer 400 is formed with a third bonding mark layer 420. After the functional wafer 400 is thinned, a third bonding mark layer 420 is formed on the second surface of the functional wafer 400, and bonding marks (not shown) for alignment are formed in the third bonding mark layer 420. The third bonding mark layer 420 is used to bond the functional wafer 400 and the bottom wafer. The material of the third bonding mark layer 420 is, for example, silicon oxide. The third bonding mark layer 420 is formed by a chemical vapor deposition process or a physical vapor deposition process.
With continued reference to fig. 5 and 9, in step S3, a bottom wafer 500 is provided, where a first dielectric layer 510 and a first metal layer 520 located in the first dielectric layer 510 are formed on a surface of the bottom wafer 500.
In some embodiments of the present application, the bottom wafer 500 is, for example, a semiconductor wafer.
In some embodiments of the present application, a semiconductor device, a metal interconnection structure, and the like are further formed in the first dielectric layer 510. The first metal layer 520 is the top metal of the metal interconnect structure and is used to electrically connect the devices in the bottom wafer 500 and the devices in the functional wafer 400.
In some embodiments of the present application, a third etching stop layer 530 and a fourth bonding mark layer 540 are further sequentially formed on the surface of the first dielectric layer 510 of the bottom wafer 500.
The third etch stop layer 530 is used to protect the first metal layer 520 from damage during subsequent formation of a through silicon via structure. The material of the third etching stop layer 530 is, for example, silicon nitride. The third etching stop layer 530 is formed by a chemical vapor deposition process or a physical vapor deposition process.
The fourth bonding mark layer 540 is used to bond the functional wafer 400 and the bottom wafer 500. The fourth bonding mark layer 540 has bonding marks (not shown) formed therein for alignment. The material of the fourth bonding mark layer 540 is, for example, silicon oxide. The fourth bonding mark layer 540 is formed by a chemical vapor deposition process or a physical vapor deposition process.
With continued reference to fig. 5 and 10, in step S4, the bottom wafer 500 and the second surface of the functional wafer 400 are bonded. Specifically, the bottom wafer 500 and the second side of the functional wafer 400 are bonded through the third bonding mark layer 420 and the fourth bonding mark layer 540.
With continued reference to fig. 5 and 11, in step S5, the carrier wafer 300 is removed.
In some embodiments of the present application, the adhesion layer 310 is also removed when the carrier wafer 300 is removed.
In some embodiments of the present application, the method of removing the carrier wafer 300 and the adhesion layer 310 includes: firstly, polishing and removing most of the carrier wafer 300 by using a chemical mechanical polishing process; the remaining small portion of the carrier wafer 300 and the adhesion layer 310 are then etched away using a wet etch process. The hard mask layer 320 is not etched and is not damaged due to the protection of the first etch stop layer 320.
In conventional processes, the hard mask layer 330 is formed on the functional wafer 400 and the bottom wafer 500 at this point (i.e., after the functional wafer 400 and the bottom wafer 500 are bonded together and the carrier wafer 300 is removed). Therefore, on the one hand, the high temperature environment during forming the hard mask layer 330 may have a thermal influence on the functional wafer 400 and the bottom wafer 500, so as to reduce the device reliability of the functional wafer 400 and the bottom wafer 500; on the other hand, the hard mask layer 330 may generate downward compressive stress on the functional wafer 400 and the bottom wafer 500, which may cause serious warpage of the functional wafer 400 and the bottom wafer 500, and affect the subsequent processes.
However, in the present embodiment, the hard mask layer 330 is formed on the carrier wafer 300, and then bonded to the functional wafer 400, and thus to the bottom wafer 500, together with the carrier wafer 300. Thus, on the one hand, there is no thermal impact on the functional wafer 400 and the bottom wafer 500; on the other hand, since the hard mask layer 330 is located on the carrier wafer 300 and then turned 180 degrees and then bonded to the functional wafer 400 and the bottom wafer 500, the hard mask layer 330 generates upward tensile stress to the bottom wafer 300 after being turned (this is because the film stress is a characteristic of the film itself, and is not affected by the orientation of the film after the deposition), and the tensile stress balances the stresses of the functional wafer 400 and the bottom wafer 500, thereby reducing warpage of the functional wafer 400 and the bottom wafer 500.
With continued reference to fig. 5 and 12 to 17, in step S6, the first bonding mark layer 350 and the functional wafer 400 are etched using the hard mask layer 330 as a mask to form a through-silicon via 600 penetrating the first bonding mark layer 350 and the functional wafer 400 and exposing the first metal layer 520.
Referring to fig. 12, a patterned photoresist layer 610 is formed on the surface of the first etch stop layer 320, and the patterned photoresist layer 610 defines the position of the through silicon via 600.
Referring to fig. 13, the patterned photoresist layer 610 is used as a mask to first etch the first etching stop layer 320, the hard mask layer 330, the second etching stop layer 340, the first bonding mark layer 350, and the second bonding mark layer 410 to expose the first surface of the functional wafer 400 to form a through silicon via 600.
The first etchant used for the first etching is an etchant with a relatively high etching selectivity to silicon oxide, silicon nitride material (the first etching stop layer 320, the hard mask layer 330, the second etching stop layer 340, the first bonding mark layer 350, and the second bonding mark layer 410 are all made of silicon oxide or silicon nitride material), and silicon material (the functional wafer 400 is made of silicon material). This stops the first etch at the surface of the functional wafer 400.
In some embodiments of the present application, the first etch is an anisotropic etch. The patterned photoresist layer 610 is completely consumed due to the deeper etch depth.
Referring to fig. 14, the functional wafer 400 is etched along the through silicon via 600 until the third bonding mark layer 420 is exposed.
The second etchant used in the second etching is an etchant with a relatively high etching selectivity for the silicon material (the functional wafer 400 is a silicon material) and the silicon oxide material (the third bonding mark layer 420 is a silicon oxide material). This stops the second etch at the surface of the third bond mark layer 420.
In some embodiments of the present application, the second etch is an anisotropic etch. The first etch stop layer 320 is completely consumed and the hard mask layer 330 is also partially consumed.
Referring to fig. 15, the third bonding mark layer 420 and the fourth bonding mark layer 540 are third etched along the through-silicon via 600 until the third etch stop layer 530 is exposed. The first metal layer 520 is not damaged by etching due to the protection of the third etch stop layer 530.
The third etchant used for the third etching is an etchant having a relatively high etching selectivity to a silicon oxide material (the third bonding mark layer 420 and the fourth bonding mark layer 540 are silicon oxide materials) and a silicon nitride material (the third etching stop layer 530 is silicon nitride materials). This stops the third etch at the surface of the third etch stop layer 530.
In some embodiments of the present application, the third etch is an anisotropic etch. The hard mask layer 330, the second etch stop layer 340, and the first bond mark layer 350 are completely consumed.
In some embodiments of the present application, third etching the third bonding mark layer 420 and the fourth bonding mark layer 540 along the through-silicon via 600 until the third etching stop layer 530 is exposed further comprises: barrier layers (not shown) are formed on the sidewalls and bottom of the through silicon via 600.
The blocking layer is used to block metal particles in a through-silicon via structure formed in the through-silicon via 600 from diffusing into the functional wafer 400, so that the functional wafer 400 is shorted. The material of the barrier layer is, for example, silicon oxide. The method for forming the barrier layer is, for example, a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 16, the third etch stop layer 530 is etched fourth along the through silicon via 600 until the first metal layer 520 is exposed.
In some embodiments of the present application, the third etch stop layer 530 is etched fourth along the through-silicon via 600 to expose the first metal layer 520, and also etch the barrier layer at the bottom of the through-silicon via 600.
In the technical solution of the present application, since the thicknesses of the first etching stop layer 320, the hard mask layer 330 and the second etching stop layer 340 (i.e., the film layer that is used as the etching mask when etching to form the through-silicon via 600) are thicker, the shape of the through-silicon via 600 can be controlled more precisely, so that the cross-sectional shape of the through-silicon via 600 is closer to a rectangle than an inverted trapezoid. Thereby improving the density of the through silicon via structure formed subsequently and the electrical signal interconnection density between the functional wafers.
With continued reference to fig. 5 and 17, in step S7, a metal is filled in the through-silicon via 600 to form a through-silicon via structure 620. The through silicon via structure 620 is electrically connected to the first metal layer 520.
In this technical solution, the through silicon via structure 620 has high density, so as to improve the electrical signal interconnection density between the functional wafers.
The material of the through silicon via structure 620 is, for example, copper or tungsten. The through silicon via structure 620 is formed by, for example, an electroplating process.
The application provides a forming method of a through silicon via structure, which comprises the steps of manufacturing a hard mask layer on a carrier wafer, bonding the hard mask layer to a functional wafer, and improving the thickness of the hard mask layer, so that the core size of the through silicon via structure is accurately controlled, the density of the through silicon via structure is further improved, and the electrical signal interconnection density between the functional wafers is improved.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (13)

1. The method for forming the through silicon via structure is characterized by comprising the following steps:
providing a carrier wafer, wherein a hard mask layer and a first bonding mark layer are sequentially formed on the surface of the carrier wafer;
bonding the carrier wafer and the first surface of the functional wafer through the bonding mark layer;
providing a bottom wafer, wherein a first dielectric layer and a first metal layer positioned in the first dielectric layer are formed on the surface of the bottom wafer;
bonding the bottom wafer and the second face of the functional wafer;
removing the carrier wafer;
etching the first bonding mark layer and the functional wafer by taking the hard mask layer as a mask to form a through silicon hole penetrating through the first bonding mark layer and the functional wafer and exposing the first metal layer;
and filling metal in the through silicon via to form a through silicon via structure.
2. The method of claim 1, wherein an adhesion layer and a first etch stop layer are further formed in sequence between the carrier wafer surface and the hard mask layer, and a second etch stop layer is further formed between the hard mask layer and the first bond mark layer.
3. The method of forming a through silicon via structure of claim 2, wherein the adhesion layer has a thickness of 50 to 200 angstroms and the first bond mark layer has a thickness of 3000 to 5000 angstroms.
4. The method of claim 3, wherein the hard mask layer has a thickness of 10000 to 40000 angstroms, the first etch stop layer has a thickness of 500 to 2000 angstroms, and the second etch stop layer has a thickness of 50 to 500 angstroms.
5. The method of claim 3, wherein the hard mask layer has a thickness of 10000 to 30000 angstroms, the first etch stop layer has a thickness of 1000 to 5000 angstroms, and the second etch stop layer has a thickness of 1000 to 2000 angstroms.
6. The method of forming a through silicon via structure of claim 2, wherein the adhesion layer is also removed when the carrier wafer is removed.
7. The method of forming a through-silicon via structure of claim 1, wherein the first side of the functional wafer is further formed with a second bond mark layer, the carrier wafer and the first side of the functional wafer being bonded through the first bond mark layer and the second bond mark layer.
8. The method of forming a through silicon via structure of claim 1, wherein bonding the carrier wafer to the first side of the functional wafer via the bonding mark layer further comprises: and thinning the functional wafer.
9. The method of forming a through silicon via structure of claim 2, wherein the second side of the functional wafer is formed with a third bond mark layer.
10. The method of forming a through-silicon via structure of claim 9, wherein a third etch stop layer and a fourth bond mark layer are further formed on the surface of the first dielectric layer of the bottom wafer in sequence, and the second surfaces of the bottom wafer and the functional wafer are bonded through the third bond mark layer and the fourth bond mark layer.
11. The method of claim 10, wherein etching the first bond mark layer and the functional wafer with the hard mask layer as a mask to form a through-silicon via that extends through the first bond mark layer and the functional wafer and exposes the first metal layer comprises:
forming a patterned photoresist layer on the surface of the first etching stop layer, wherein the patterned photoresist layer defines the position of the through silicon via;
first etching the first etching stop layer, the hard mask layer, the second etching stop layer and the first bonding mark layer by taking the patterned photoresist layer as a mask until the first surface of the functional wafer is exposed to form a silicon through hole;
second etching the functional wafer along the through silicon via until the third bonding mark layer is exposed;
third etching the third bonding mark layer and the fourth bonding mark layer along the through silicon via until the third etching stop layer is exposed;
and etching the third etching stop layer along the through silicon via until the first metal layer is exposed.
12. The method of forming a through-silicon via structure of claim 11, wherein third etching the third bond mark layer and the fourth bond mark layer along the through-silicon via to expose the third etch stop layer further comprises: and forming a barrier layer on the side wall and the bottom of the through silicon via.
13. The method of forming a through-silicon via structure of claim 12, wherein the third etch stop layer is etched fourth along the through-silicon via to expose the first metal layer and further etching a barrier layer at the bottom of the through-silicon via.
CN202111533963.4A 2021-12-15 2021-12-15 Forming method of through silicon via structure Pending CN116264183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111533963.4A CN116264183A (en) 2021-12-15 2021-12-15 Forming method of through silicon via structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111533963.4A CN116264183A (en) 2021-12-15 2021-12-15 Forming method of through silicon via structure

Publications (1)

Publication Number Publication Date
CN116264183A true CN116264183A (en) 2023-06-16

Family

ID=86723597

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111533963.4A Pending CN116264183A (en) 2021-12-15 2021-12-15 Forming method of through silicon via structure

Country Status (1)

Country Link
CN (1) CN116264183A (en)

Similar Documents

Publication Publication Date Title
US20050224921A1 (en) Method for bonding wafers to produce stacked integrated circuits
US8222121B2 (en) Fiducial scheme adapted for stacked integrated circuits
US7671460B2 (en) Buried via technology for three dimensional integrated circuits
US8183127B2 (en) Method for bonding wafers to produce stacked integrated circuits
US8896136B2 (en) Alignment mark and method of formation
CN110121766B (en) Method for forming lead in hybrid bonding semiconductor device
KR100383504B1 (en) Semiconductor device and method of producing the same
US11127729B2 (en) Method for removing a bulk substrate from a bonded assembly of wafers
JPH09507612A (en) Manufacturing method of three-dimensional circuit device
KR20180118656A (en) Composite wafer, semiconductor device, electronic component and method of manufacturing semiconductor device
US20200075482A1 (en) Semiconductor device and manufacturing method thereof
CN106206499A (en) Semiconductor device and method
CN111564368A (en) Semiconductor device and manufacturing method thereof
US20230411435A1 (en) Semiconductor device and manufacturing method therefor, and chip bonding structure
US9236359B2 (en) System and method for 3D integrated circuit stacking
JP2007005401A (en) Semiconductor device and its manufacturing method
US20240170475A1 (en) Method for manufacturing semiconductor device, semiconductor device, integrated circuit element, and method for manufacturing integrated circuit element
TWI701716B (en) Semiconductor device and the method of manufacturing the same
TWI793655B (en) Conductive feature with non-uniform critical dimension and method of manufacturing the same
KR100721625B1 (en) Mems package and method of manufacturing the same
CN116264183A (en) Forming method of through silicon via structure
CN210015846U (en) Wafer and semiconductor device
US9960081B1 (en) Method for selective etching using dry film photoresist
CN112151439A (en) Wafer, manufacturing method thereof and semiconductor device
TW202042317A (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination