CN116264447A - Programmable gain amplifier and gain control method - Google Patents
Programmable gain amplifier and gain control method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
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- H03G3/30—Automatic control in amplifiers having semiconductor devices
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Abstract
A programmable gain amplifier for providing gain to an input signal to generate an output signal includes an operational amplifier and a capacitive array. The capacitor array comprises a first capacitor, a second capacitor and a third capacitor which are arranged in parallel and are selectively coupled to an input end or a ground end of the operational amplifier according to a first switch, a second switch and a third switch respectively, wherein the first capacitor, the second capacitor and the third capacitor respectively have a first capacitance value, a second capacitance value and a third capacitance value, and the third capacitance value is equal to the first capacitance value plus the second capacitance value. In the first configuration, the first switch and the second switch are operated in a first conductive state and the third switch is operated in a second conductive state. When the first configuration is switched to the second configuration, the third switch is operated in a first conduction state and the first switch and the second switch are operated in a second conduction state. The gain values provided in the first configuration and the second configuration are equal.
Description
Technical Field
The present invention relates to an amplifier and a gain control method, and more particularly, to a programmable gain amplifier and a gain control method thereof.
Background
When a programmable gain amplifier (programmable gain amplifier, hereinafter referred to as PGA) performs gain adjustment, it is an important issue in the art to reduce the disturbance in adjusting the gain because the switching of the internal components of the PGA causes different disturbances to affect the stability of the PGA.
Disclosure of Invention
The invention discloses a PGA for providing gain values to an input signal to generate an output signal, which comprises an operational amplifier and a capacitor array. The capacitor array comprises a first capacitor, a second capacitor and a third capacitor which are arranged in parallel and are selectively coupled to an input end or a ground end of the operational amplifier according to a first switch, a second switch and a third switch respectively, wherein the first capacitor, the second capacitor and the third capacitor respectively have a first capacitance value, a second capacitance value and a third capacitance value, and the third capacitance value is equal to the first capacitance value plus the second capacitance value. In the first configuration, the first switch and the second switch are operated in a first conductive state and the third switch is operated in a second conductive state. When the first configuration is switched to the second configuration, the third switch is operated in a first conduction state and the first switch and the second switch are operated in a second conduction state. The gain values provided in the first configuration and the second configuration are equal.
The invention discloses a gain control method for providing gain values to an input signal to generate an output signal. The gain control method comprises the following steps: receiving an input signal through a capacitor array, wherein the capacitor array is coupled to an input end of the operational amplifier, comprises a first capacitor, a second capacitor and a third capacitor which are arranged in parallel and are selectively coupled to the input end or the ground end of the operational amplifier according to a first switch, a second switch and a third switch respectively, and the first capacitor, the second capacitor and the third capacitor respectively have a first capacitance value, a second capacitance value and a third capacitance value, wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value; under a first configuration, the first switch and the second switch are operated in a first conduction state, and the third switch is operated in a second conduction state; when the first configuration is switched to the second configuration, the third switch is operated in a first conduction state, and the first switch and the second switch are operated in a second conduction state, wherein gain values provided by the first configuration and the second configuration are equal; and outputting the output signal with the operational amplifier according to the second configuration.
Compared with the prior art, the PGA and the gain control method of the present invention can flexibly adjust the gain value in a manner that generates less disturbance to increase the stability of the circuit.
Drawings
The various forms of the invention can be best understood upon reading the following embodiments and upon reference to the drawings. It should be noted that the various features of the drawings are not drawn to scale in accordance with standard practice in the industry. Indeed, the dimensions of some features may be exaggerated or reduced on purpose for clarity of description.
Fig. 1 is a schematic diagram of a PGA according to some embodiments of the invention.
FIG. 2 is a schematic diagram of a capacitor array in different sets of states according to some embodiments of the present invention.
Fig. 3 is a schematic diagram of a capacitor array in accordance with another embodiment of the present invention.
Fig. 4 is a schematic diagram of a PGA according to another embodiment of the invention.
Fig. 5 is a schematic diagram of a capacitor array in different sets of states according to another embodiment of the present invention.
FIG. 6 is a timing diagram illustrating a configuration change of a capacitor array according to some embodiments of the present invention.
Detailed Description
Fig. 1 is a schematic diagram of a PGA 10 according to some embodiments of the invention. The PGA 10 is used for providing a gain value to the input signal Sin to generate the output signal Sout. PGA 10 includes capacitor array a, OP, capacitor CFB and resistor R.
The capacitor array A comprises a capacitor C1, a capacitor C2, a capacitor C3-capacitor Cx, and a switch S1, a switch S2 and a switch S3-switch Sx corresponding to the capacitor C3-capacitor Cx, wherein x is a positive integer. In some embodiments, the capacitive array a comprises at least three capacitors. The capacitors C1-Cx respectively comprise a first end for receiving the input signal Sin and a second end correspondingly connected with the switches S1-1 x. The capacitors C1 to Cx are arranged in parallel and selectively coupled to the input terminal N1 or the ground terminal of the operational amplifier OP, respectively, according to the switches S1 to Sx.
The capacitor CFB and the resistor R are respectively connected between the output terminal N1 and the output terminal N2 of the operational amplifier OP. The operational amplifier OP is configured to output an output signal Sout at an output terminal N2.
The gain value of the PGA 10 is controlled by the on-state of the switches S1 to Sx. Details thereof are described below.
The capacitance values of the capacitances C1-Cx in the capacitance array A are not exactly the same as each other, and in some embodiments, the capacitance values of the capacitances C1-Cx are partially the same but partially different. In the present invention, according to the configuration of the switches S1 to Sx, when the capacitances C1 to Cx are connected to the input terminal N, these capacitances operate as the capacitance array A1, and when the capacitances C1 to Cx are connected to the ground terminal, these capacitances operate as the capacitance array A2. The sum of the capacitance values of the capacitor array A1 and the capacitor array A2 is equal to the capacitance value of the capacitor array a. In other words, the changes in the capacitive array A1 and the capacitive array A2 are interrelated. The following description will be made with reference to the embodiment in which the capacitor array a includes six capacitors, but the invention is not limited thereto, and the number of the capacitors is within the scope of the invention.
Reference is made to fig. 2. Fig. 2 is a schematic diagram illustrating an embodiment of switching the capacitor array A1 and the capacitor array A2 from the configuration F1 to the configuration F2. The capacitances C1 to C6 have capacitance values of 2.5, 5, 10, 20 and 40 units, respectively. The capacitance value of the capacitor C4 is equal to the sum of the capacitance values of the capacitor C2 and the capacitor C3. In some embodiments, the capacitance value of capacitor C2 is not equal to the capacitance value of capacitor C3. The above values are used to represent the ratio of capacitance values between capacitors, and are not limited to any unit, for example, the units may be 1pF, 10pF, or other suitable units.
Under different states of the PGA 10, the switches S1 to Sx have different on states to control the capacitance values of the capacitor array A1 and the capacitor array A2. In some embodiments, the configuration of the capacitor array A1 and the capacitor array A2 is represented by a six-bit array B, wherein six bits of the array B represent which capacitors among the capacitors C1-C6 are operated as part of the capacitor array A1 (or the capacitor array A2), respectively. In the array B, "0" represents that a specific capacitor does not operate as part of the capacitor array A1 (or the capacitor array A2), and "1" represents that a specific capacitor operates as part of the capacitor array A1 (or the capacitor array A2). For example, when the array B of the capacitor array A1 is "110000", it indicates that the capacitor C1 and the capacitor C2 are operated as a part of the capacitor array A1, so that the overall capacitance value of the capacitor array A1 in this configuration is the sum of the capacitance values of the capacitor C1 and the capacitor C2. In contrast, in the configuration in which the array B of the capacitor array A1 is "110000", the array B of the capacitor array A2 is "001111", so that the overall capacitance value of the capacitor array A2 in this configuration is the sum of the capacitance values of the capacitors C3 to C6.
For ease of understanding, when the switches S1-Sx are switched to connect the capacitances C1-Cx to the input N1, they are referred to as a first conductive state; when the switches S1 to Sx are switched to connect the capacitances C1 to Cx to the ground terminal, the second conduction state is referred to as a second conduction state.
Referring to fig. 2, in the configuration F1 of the PGA 10, the array B of the capacitor array A1 is "011000", and the total capacitance is 10 (0+5+5+0+0+0=10) units. In the configuration F2, the array B of the capacitor array A1 is "000100", and the capacitance value is also 10 (0+0+0+10+0+0=10) units. The capacitance values of the two configurations are the same, but the capacitance number of the capacitor array A1 is changed from 2 to 1.
When the PGA 10 is switched from the configuration F1 to the configuration F2, the capacitors C1 and C2 are switched from operating as part of the capacitor array A1 to operating as part of the capacitor array A2, the capacitor C4 is switched from operating as part of the capacitor array A2 to operating as part of the capacitor array A1, wherein the switches S2, S3 are switched from the first conductive state to the second conductive state, and the switch S4 is switched from the second conductive state to the first conductive state. The overall capacitance of the capacitor array A1 in the configurations F1 and F2 is unchanged. In some embodiments, the process of switching from configuration F1 to configuration F2 is referred to as "handoff. The capacitor array A1 after the hand-off can have more capacitors with lower gears (lower capacitance values) for the subsequent switching. Therefore, even when the capacitance value of the capacitance array A1 has been adjusted to a larger value, the PGA 10 can adjust the gain value with a finer resolution.
In contrast, the adjustment of the capacitor array A2 corresponds to the capacitor array A1. Specifically, the capacitors C1-C6 may be shared as part of the capacitor array A1 and the capacitor array A2, if operated as either part of the capacitor array A1 or part of the capacitor array A2. Thus, in the configuration F1-F2 of the PGA 10, the array B of the capacitor array A2 may be denoted as "100111" and "111011", respectively, in exactly the opposite form to the array B of the capacitor array A2.
In some embodiments, the transition from configuration F1 to configuration F2 of PGA 10 is also referred to as a least differential transition (minimum difference transition) because the overall capacitance values of capacitive array A1 and capacitive array A2 do not change.
In some embodiments, the PGA 10 switches only two switches (changes the coupling state of two capacitors) when adjusting the gain value. Please refer to fig. 3, which illustrates an embodiment of switching the capacitor array A1 and the capacitor array A2 from the configuration F3 to the configuration F4 of the PGA 10.
In the configuration F3 of the PGA 10, the array B of the capacitor array A1 is 100000. When the capacitor array A1 is switched from the configuration F3 to the configuration F4, the switch S1 is switched from the first conductive state to the second conductive state, and the switch S2 is switched from the second conductive state to the first conductive state, so that the array B of the capacitor array A1 is switched to "010000". In this transition, only one switch is switched from the first conductive state to the second conductive state, and only one switch is switched from the second conductive state to the first conductive state. The conversion of the capacitor array A2 corresponds to the capacitor array A1, and will not be described herein.
In some embodiments, when transitioning from configuration F3 to configuration F4, the transition is also referred to as a minimum switching transition (minimum switching transition) because the capacitive array A1 switches only two switches. In general, switching a greater number of switches causes a greater disturbance, such that the stability of the circuit is affected. Therefore, compared with the prior art, the PGA 10 of the present invention generates less disturbance when adjusting the gain value, so that the circuit is more stable.
In some embodiments, the PGA 10 applies the minimum difference conversion and the minimum switching conversion simultaneously when adjusting the gain value.
Refer to fig. 4. Fig. 4 is a schematic diagram of a PGA 10 according to another embodiment of the invention. In other embodiments, the capacitor array a of the PGA 10 further includes a compensation capacitor Cn1, a compensation capacitor Cn2, a switch Sn1 and a switch Sn2. The capacitors Cn1 to Cn2 respectively include a first terminal for receiving the input signal Sin and a second terminal correspondingly connected to the switches Sn1 to Sn2. The capacitors Cn1 to Cn2 are arranged in parallel and selectively coupled to the input terminal N1 or the ground terminal of the operational amplifier OP according to the switches Sn1 to Sn2, respectively.
Similar to the capacitors C1-Cx, the capacitors Cn 1-Cn 2 are operable as part of the capacitor array A1 or the capacitor array A2 according to the switches Sn 1-Sn 2, wherein the switches Sn 1-Sn 2 are conducted to the input terminal N1, also referred to as a first conductive state, and to ground, also referred to as a second conductive state.
The compensation capacitors Cn1 and Cn2 are used to present a changed state in a period after the capacitance array A1 changes the overall capacitance value, and transition to a steady state after the changed state, wherein the changed state is divided into three transient states TT1 to TT3 (as shown in fig. 5). The three transients TT 1-TT 3 correspond to the first, second and third columns of the array B of capacitors A1 of the configuration F6 of the PGA 10 of FIG. 5, respectively. In the first transient TT1, the compensation capacitor Cn1 and the compensation capacitor Cn2 compensate the capacitance value of the capacitor array A1 that is changed by the switches S1 to Sx switching on states. Then, in the second transient TT2, the compensation capacitor Cn1 and the compensation capacitor Cn2 gradually cancel the compensated capacitance value. And finally, in the third transient state TT3, the capacitance values compensated by the compensation capacitor Cn1 and the compensation capacitor Cn2 are eliminated. It should be noted that the columns of the transients TT 1-TT 3 shown in FIG. 5 represent the results after the transition in the transient, and reference is made to FIG. 5 for details of the operation.
In the embodiment of fig. 5, the capacitor array a is illustrated with 4 capacitors C1-C4 and compensation capacitors Cn1 and Cn 2. However, the present invention is not limited thereto, and the number of the compensation capacitors is within the scope of the present invention. For example, the number of compensation capacitances may be one or more than two.
As shown in fig. 5, the capacitors C1 to C4 and the compensation capacitors Cn1 and Cn2 have capacitance values of 2.5, 5, 10, 1.25 and 1.25 units, respectively.
In the configuration F5, the switch S2 is in the first conductive state, and the other switches are in the second conductive state, and the capacitor array A1 has a capacitance of 5 (0+5+0+0+0=5) units. When the switch is switched from the configuration F5 to the configuration F6, the switch S2 is switched from the first conductive state to the second conductive state, the switch S1 is switched from the second conductive state to the first conductive state, and the conductive states of the other switches are unchanged, so that the capacitor array A1 has a capacitance value of 2.5 (2.5+0+0+0+0+0=2.5) units.
After the switch S1 and the switch S2 are switched from the configuration F5 to the configuration F6, the capacitance array A1 is reduced by 2.5 (5-2.5=2.5) units, and the change state F6' of the configuration F6 is entered (refer to fig. 6), and the compensation capacitors Cn1 and Cn2 are used to compensate for the reduced 2.5 units of the capacitance array A1 in the first transient TT1 immediately after the switch is switched to the configuration F6. Therefore, the switch Sn1 and the switch Sn2 switch from the second conductive state to the first conductive state, so that the capacitance value of the capacitor array A1 is increased by 2.5 units. Then a second transient TT2 is entered, gradually decreasing the compensated 2.5 units to 0. As shown in fig. 5, the switch Sn1 and the switch Sn2 are switched from the second conductive state to the first conductive state when the switch Sn1 is just switched to the first transient state, then the switch Sn2 is switched from the first conductive state to the second conductive state when the switch Sn2 is switched to the second transient state when the switch Sn2 is switched to the second conductive state, and finally the switch Sn1 is switched from the first conductive state to the second conductive state and enters the third transient state TT3. After the switching of the third transient TT3 is completed, the steady state of the configuration F6 is entered. The overall capacitance value of the capacitor array A1 is shifted from 5 units to 3.75 units and finally to 2.5 units via the three transitions of the transients TT 1-TT 3 during the above period.
In other words, the compensation capacitors Cn1 and Cn2 are used to prolong the overall capacitance value conversion time of the capacitor array A1 (i.e. the time covered by the change state F6' shown in fig. 6), so that the capacitance value change of each stage of the capacitor array A1 is reduced, thereby reducing the disturbance generated by the converted capacitance value and improving the stability of the PGA 10 circuit.
The sum of the capacitance values of the compensation capacitance Cn1 and the compensation capacitance Cn2 is equal to the smallest capacitance value among the capacitances C1 to C4. In some embodiments, the sum of the capacitance values of compensation capacitance Cn1 and compensation capacitance Cn2 is less than the smallest of the capacitances C1-C4. In some embodiments, the capacitance values of compensation capacitor Cn1 and compensation capacitor Cn2 are not equal.
In other embodiments, the sum of the capacitance values of the compensation capacitor Cn1 and the compensation capacitor Cn2 is greater than the smallest of the capacitances C1-C4, but less than a threshold value, wherein the threshold value is used to indicate that the PGA 10 has negligible change in its corresponding capacitance value.
In some embodiments, the capacitive array a includes more than two compensation capacitors, which have equal capacitance values. The capacitance values of the compensation capacitors are m-n times of the smallest capacitance value among the capacitors C1-Cx, wherein m and n are positive integers larger than 1.
Combining fig. 1-5, the compensation method provided by the embodiment of fig. 5 may combine the minimum differential conversion and the minimum switching conversion described above. That is, the compensation method provided in the embodiment of fig. 5 can be used to change the configuration regardless of whether the overall capacitance of the capacitor array A1 and the capacitor array A2 is changed.
The foregoing description briefly sets forth features of certain embodiments of the invention in order to provide a more thorough understanding of the various forms of the invention to those skilled in the art. Those skilled in the art should appreciate that they may readily use the conception and the specific disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments herein. It will be apparent to those skilled in the art that such equivalent embodiments are within the spirit and scope of the present disclosure, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.
[ symbolic description ]
10 programmable gain amplifier
A: capacitor array
OP (operational amplifier)
CFB capacitor
R is resistance
Sin input signal
Sout: output signal
C1 capacitance
C2 capacitance
C3 capacitance
C4 capacitance
C5 capacitance
C6 capacitance
Cx capacitance
Cn1 compensating capacitor
Cn2 compensating capacitor
S1 switch
S2 switch
S3 switch
S1x switch
Sn1 switch
Sn2 switch
N1 input terminal
N2 output end
F1 configuration of
F2 configuration of
F3 configuration
F4 configuration of
F5 configuration
F6 configuration of
F6': change state
B series of numbers
TT1 transient state
TT2 transient state
TT3 transient state
Claims (10)
1. A programmable gain amplifier (programmable gain amplifier, PGA) for providing a gain value to an input signal to produce an output signal, comprising:
an operational amplifier for outputting the output signal; and
a capacitor array including a first capacitor, a second capacitor and a third capacitor arranged in parallel and selectively coupled to an input terminal or a ground terminal of the operational amplifier according to a first switch, a second switch and a third switch, respectively, wherein the first capacitor, the second capacitor and the third capacitor have a first capacitance value, a second capacitance value and a third capacitance value, respectively, wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value,
wherein in a first configuration, the first switch and the second switch operate in a first conductive state and the third switch operate in a second conductive state, and when transitioning from the first configuration to the second configuration, the third switch operates in the first conductive state and the first switch and the second switch operate in the second conductive state, wherein the gain values provided in the first configuration and the second configuration are equal.
2. The programmable gain amplifier of claim 1, wherein when the first, second and/or third switches are operated in the first conductive state, the first, second and/or third capacitances respectively corresponding to the first, second and/or third switches operate as a first capacitance array, and
when the first switch, the second switch and/or the third switch are operated in the second conduction state, the first capacitor, the second capacitor and/or the third capacitor respectively corresponding to the first switch, the second switch and/or the third switch are operated as a second capacitor array.
3. The programmable gain amplifier of claim 2, wherein in a third configuration, the second switch is operated in the first conductive state and the first switch and the third switch are operated in the second conductive state,
wherein upon transition from the third configuration to a fourth configuration, the third switch is operated in the first conductive state and the first switch and the second switch are operated in the second conductive state, an
Wherein the gain values provided in the third configuration and the fourth configuration are not equal.
4. A programmable gain amplifier as in claim 3, wherein said capacitor array further comprises a first compensation capacitor selectively coupled to said input terminal or said ground terminal according to a first compensation switch, wherein said first compensation capacitor has a compensation capacitance value, wherein said compensation capacitance value is less than or equal to said first capacitance value.
5. The programmable gain amplifier of claim 4, wherein during a first period of time after switching the first capacitor from operating as the first capacitor array to operating as the second capacitor array, the first compensation switch is configured to switch from the second conductive state to the first conductive state and then to the second conductive state during the first period of time, wherein during the first period of time the second capacitor and the third capacitor operate as the second capacitor array.
6. A gain control method for providing a gain value to an input signal to generate an output signal, comprising:
receiving the input signal via a capacitor array, wherein the capacitor array is coupled to an input terminal of an operational amplifier, comprises a first capacitor, a second capacitor and a third capacitor which are arranged in parallel and are selectively coupled to the input terminal or a ground terminal of the operational amplifier according to a first switch, a second switch and a third switch respectively, wherein the first capacitor, the second capacitor and the third capacitor respectively have a first capacitance value, a second capacitance value and a third capacitance value, and wherein the third capacitance value is equal to the first capacitance value plus the second capacitance value;
in a first configuration, operating the first switch and the second switch in a first conductive state and operating the third switch in a second conductive state;
when switching from the first configuration to a second configuration, operating the third switch in the first conductive state and the first switch and the second switch in the second conductive state, wherein the gain value provided in the first configuration and the second configuration is equal; and
according to the second configuration, the output signal is output by the operational amplifier.
7. The gain control method according to claim 6, wherein when the first switch, the second switch, and/or the third switch are operated in the first on state, the first capacitor, the second capacitor, and/or the third capacitor to which the first switch, the second switch, and/or the third switch respectively correspond are operated as a first capacitor array, and
when the first switch, the second switch and/or the third switch are operated in the second conduction state, the first capacitor, the second capacitor and/or the third capacitor respectively corresponding to the first switch, the second switch and/or the third switch are operated as a second capacitor array.
8. The gain control method according to claim 7, further comprising:
in a third configuration, operating the second switch in the first conductive state and operating the first switch and the third switch in the second conductive state; and
when the third configuration is changed to the fourth configuration, the third switch is operated in the first conduction state, the first switch and the second switch are operated in the second conduction state,
wherein the gain values provided in the third configuration and the fourth configuration are not equal.
9. The gain control method of claim 8, wherein said capacitor array further comprises a first compensation capacitor selectively coupled to said input terminal or said ground terminal according to a first compensation switch, wherein said first compensation capacitor has a compensation capacitance value.
10. The gain control method according to claim 9, further comprising:
when the third configuration is switched to the fourth configuration, the first compensation switch is switched from the first conduction state to the second conduction state and then is switched to the first conduction state.
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| CN202111527052.0A CN116264447A (en) | 2021-12-14 | 2021-12-14 | Programmable gain amplifier and gain control method |
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| CN202111527052.0A CN116264447A (en) | 2021-12-14 | 2021-12-14 | Programmable gain amplifier and gain control method |
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| CN116264447A true CN116264447A (en) | 2023-06-16 |
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