JP3920272B2 - Current output type digital / analog converter circuit - Google Patents

Description

  The present invention relates to a digital / analog converter, and more particularly to a current output type digital / analog converter operating at high speed.

  A current output type digital-analog converter (hereinafter referred to as a current output type DAC) is used for communication and video systems because it is suitable for high-speed operation. However, the current output type DAC is configured such that the output impedance changes because the number of current cells selected by the digital input code changes. Furthermore, as the operation speed increases, the overall output impedance decreases. For this reason, especially in the case of high-speed operation, the difference in output impedance that changes due to the digital input code of the output load and the current output DAC is reduced, and the change in the output current due to the difference in the digital input code is less than the ideal change value. Will cause distortion and distortion. This output distortion causes the analog output error or the linearity of the analog output to be lost, affects the stability of the operation, and becomes a conversion error of the digital / analog converter.

  Conventionally, a contrivance has been made to increase the impedance of the internal circuit with respect to these fluctuations in output impedance. FIG. 11 shows a circuit diagram of a current cell. The current cell includes a constant current source transistor MP11 and differential switching transistors MP21 and MP31. The source of the constant current source transistor MP11 is connected to the power supply voltage, the gate is connected to the reference bias voltage, and the drain is connected to the sources of the differential switching transistors MP21 and MP31, thereby forming a constant current source.

  The source of the differential switching transistor MP21 is connected to the drain of the constant current source transistor MP11, the gate is connected to the inversion conversion control signal, and the drain is connected to the ground potential. The source of the differential switching transistor MP31 is connected to the drain of the constant current source transistor MP11, the gate is connected to the conversion control signal, and the drain is connected to the analog output line. The current cell always supplies a constant current by switching the constant current to the analog output line or the ground potential by the conversion control signal and the inverted conversion control signal, and keeps the output voltage constant. With this configuration, by increasing the impedance of the internal circuit viewed from the analog output line, the constant current property is maintained even when the output potential varies.

  A conventional current output type DAC using this current cell will be described below. FIG. 9 is a circuit diagram of a current output type DAC, and FIG. 10 is a circuit diagram of a matrix type current output type DAC.

  The current output DAC shown in FIG. 9 includes a plurality of current cells 121 to 12n and a decoder circuit 11 that decodes an input digital input code 10. The decoder circuit decodes the input digital input code 10 and outputs conversion control signals D1 to n corresponding to the digital input code and inverted conversion control signals DB1 to n, which are inverted signals, to the respective current cells. (Hereinafter, when the subscripts 1 to n are omitted, any one of them will be referred to as a representative).

  Each current cell turns on the differential switch transistor MP3 of the current cell, turns off the differential switch transistor MP2 according to the input conversion control signal, or turns off the differential switch transistor MP3 and turns on the differential switch transistor MP2. As a result, a constant current is passed through the analog output line 20 or the dummy output line (GND). A desired analog value is obtained by adding a constant current flowing from the differential switch transistor MP3 to the analog output line 20. When a constant current from the current cell flows to the analog output line side, it is said that the current cell has been selected or turned ON.

  The matrix-type current output DAC shown in FIG. 10 has current cells arranged in a matrix, and decodes an upper bit digital input code and a decoder circuit 11- that decodes a lower bit digital input code. 2, each current cell has a logic circuit (logic) corresponding to signals from the decoder circuits 11-1 and 11-2 arranged in rows and columns, and the conversion control signal D / inverted conversion control signal 9 is different from FIG. 9 in that DB is generated, but the other operations are the same as those of the current output DAC of FIG.

  However, these current output type DACs are configured such that the output impedance changes as the number of current cells selected by the digital input code changes. The impedance of the current cell viewed from the analog output line 20 will be described. 12 and 13 show equivalent circuits of the current cell when the differential switching transistor MP31 of the current cell shown in FIG. 11 is in the ON or OFF state.

An equivalent circuit when the differential switching transistor MP31 is in the ON state will be described. The drain-gate capacitance of the differential switch transistor MP31 is C1, and its high-frequency impedance is Z = 1 / jωC1. A drain-source resistance rds _MP11 of the constant current source transistor MP11, the combined impedance of the capacitive load C2 parasitic to the drain and X. Further, Y is the combined impedance of the drain-source resistance rds _{MP31 of} the differential switching transistor MP31 and the capacitive load C3 such as the drain-source capacitance.

From the mutual conductance (gm _MP31 ) of the differential switching transistor MP31, let A be the combined impedance of the output impedance of the internal circuit represented by X + Y (1 + gmMP31 · X) and Z. On the other hand, in the equivalent circuit in which the differential switching transistor MP31 is in the OFF state, the impedance of the internal circuit is negligible and becomes Z.

This indicates that there is a difference in the impedance of the current cell in the selected / unselected state of the current cell. The output impedance viewed from the analog output line differs depending on the number of current cells that are turned on and the fluctuation of the output potential. For example, if the total number of current cells is n and the number of selected current cells is m,
When the output impedance R is expressed by R = A × B / {(n−m) × A + mB} and all current cells are selected (full scale output), the output current R becomes A / n, and the selected current cell is In the case of 0 (zero scale output), it becomes B / n and has different impedance.

  Although the output impedance of the current cell is increased in this way, the output impedance of the internal circuit as viewed from the analog output line changes depending on the number of selected current cells. The characteristics of these current output type DACs will be described below. FIG. 14 shows a graph of output impedance variation with respect to a digital input code at a high frequency. FIG. 4B shows a variation of output impedance with respect to the digital input code, and FIG. 5B shows a graph of an ILE (Integral Linearity Error) converted value with respect to the digital input code. FIG. 6B shows the spectrum characteristics of the analog output.

  As the operation becomes faster, the absolute value of the output impedance decreases, as can be seen from the graph of fluctuation of the output impedance with respect to the signal frequency in FIG. Further, when the current cell selected by the digital input code is set from FIG. 4B, the output impedance is lowered. For this reason, at high frequencies, these “differences in output impedance due to digital input codes” greatly affect the distortion of analog output. Hereinafter, when the number of current cells to be selected is small (the number of codes in the figure is small), the digital input code is small. Conversely, when the number of current cells to be selected is large (the number of codes in the figure is large), the digital input code is large. It expresses.

  FIG. 5B shows an ILE conversion value for the digital input code. In the current output type DAC of FIG. 9, when the analog output current and the output load RL are converted into voltage values, the analog output voltage is expressed as analog output current × output load, but this has a sufficiently large internal output impedance value. The case holds. However, at high frequencies, the internal output impedance value becomes small as shown in FIG. 14, and the analog output voltage is replaced by analog output current × (combined impedance of output load and internal output impedance) and fluctuates.

  The ILE value in FIG. 4 is calculated by the endpoint method as an output load of 200Ω and an internal output impedance, and represents an error from an ideal output value obtained by connecting a zero scale output potential and a full scale output potential with a straight line. The unit is LSB. A 10-bit converter has a distortion of about 1 LSB.

JP-A 63-178624 JP-A-10-112654 Japanese Examined Patent Publication No. 7-105722

  As communication and video systems increase in speed, current output DACs used in these systems are required to operate at higher speeds. However, as described above, in the current output type DAC, the output impedance changes because the number of current cells selected by the digital input code changes, and the change in the output current value due to the difference in the digital input code is different from the ideal change value. Will cause a gap. This output distortion causes the error of the analog output or the linearity of the analog output to be lost, affects the stability of the operation, and has a problem of becoming a conversion error of the digital / analog converter.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a current output type digital-analog converter that suppresses fluctuations in output impedance caused by a digital input code, has a small analog output error, and has linearity and can be operated at high speed.

  The current output type digital-analog converter circuit of the present invention is characterized in that an output impedance adjustment circuit is added to an analog output line.

The output impedance adjustment circuit has a low impedance when the digital input code is small and a high impedance when the digital input code is large. The impedance of the output impedance adjustment circuit has a digital input code dependency opposite to the digital input code dependency of the output impedance of the current cell. The output impedance adjustment circuit connects the source and drain of the MOS transistor to the analog output line. And a reference voltage is applied to the gate. The reference voltage may be the maximum value of the analog output voltage.

The output impedance adjustment circuit includes a plurality of MOS transistors, the plurality of MOS transistors each having a source and a drain connected to an analog output line, and a different reference voltage applied to each gate.

  The output impedance adjustment circuit includes a plurality of capacitors and switches, and the switch can be switched by a digital input code. A large capacitance value is obtained when the digital input code is small, and a small capacitance value is obtained when the digital input code is large. The switch is controlled so as to form.

  The current output type digital-analog converter of the present invention (hereinafter referred to as a current output type DAC) adds an output impedance adjustment circuit to the analog output line, and corrects the fluctuation of the output impedance due to the digital input code. Changes in output impedance can be suppressed. According to the present application, it is possible to obtain a current output type DAC that has few errors in analog output and can operate at high speed and has linearity.

  The current output DAC of the present invention will be described in detail below with reference to the drawings.

  FIG. 1 shows a current output DAC according to the first embodiment of the present invention. An output impedance adjustment circuit 13 is added to the configuration of the current output DAC of FIG. An output impedance adjustment circuit 13 is added to a conventional current output type DAC including a plurality of current cells 12 and a decoder circuit 11 that decodes an input digital input code 10. A plurality of current cells 121 to 12n and a decoder circuit 11 for decoding the input digital input code 10 are provided. The decoder circuit decodes the input digital input code 10 and outputs conversion control signals D1 to n corresponding to the digital input code and inverted conversion control signals DB1 to n, which are inverted signals, to the respective current cells. . The same components as those in FIG. 9 are denoted by the same reference numerals, and the configuration and operation thereof are the same, and the description thereof will be omitted.

  The output impedance adjustment circuit 13 added in the present invention functions to suppress fluctuations in output impedance due to the input digital input code 10. In the present invention, as an example, the output impedance adjustment circuit 13 will be described as a configuration using the gate capacitance of a Pch transistor. As shown in FIG. 2, the gate of the Pch transistor is connected to the reference voltage REF, and the source, drain, and bulk are connected to the analog output line 10. The reference voltage REF is set to the maximum analog output level. When the output voltage level of the analog output line 20 is 0 to 1V, the reference voltage is set to 1V.

  The gate capacitance of the MOS transistor has a bias-dependent characteristic as shown in FIG. In this CV curve, a region with good linearity, for example, the illustrated region of 0 to 1 V is used. The gate voltage is Vg, the source, drain, and bulk are commonly connected to the analog output line, and the voltage is Vs.

  Here, when the value of the digital input code is small and the number of selected current cells is small, the analog output voltage is low and a voltage close to 0 V is applied as the source voltage. Accordingly, since a large voltage is applied to the gate-source voltage, the gate capacitance has a large capacitance value. Conversely, when the value of the digital input code is large and there are many selected current cells, the analog output voltage is high, the voltage close to the maximum value of the analog output is applied, and the gate-source voltage is almost 0V. Therefore, the gate capacitance is a small capacitance value. Thus, the gate capacitance value of the MOS transistor changes depending on the digital input code.

  Referring to the graph of the dependence of the output impedance on the digital input code in the conventional example of FIG. 4B, the output impedance is large when the digital input code is small, and the output impedance is small when the digital input code is large. It has a tendency opposite to the impedance of the output impedance adjustment circuit. From this, at high frequencies, fluctuations in the output impedance of the internal circuit as seen from the output line and fluctuations in the capacitance value of the output impedance adjustment circuit tend to be opposite, so the fluctuations are canceled out as the combined impedance. As shown in a), the output impedance in the present invention can suppress the dependency on the digital input code.

  Here, the dependency of the output impedance on the digital input code is caused by a change in the combined impedance of the impedance A of the selected current cell and the impedance B of the unselected current cell. To cancel this dependency, half of the total number of current cells is selected, or the slope of the dependence of the output impedance on the digital input code under the unselected condition is opposite to the slope of the impedance of the output impedance adjustment circuit. It should be set as follows. As a result, as shown in FIG. 4A, the output impedance in the present invention can suppress the dependency on the digital input code.

  By suppressing the fluctuation of the output impedance, in the embodiment, the ILE conversion value for the digital input code is improved as shown in FIG. 5A, and the high frequency characteristics (SINAD, SFDR) as shown in FIG. 6A. Also, in the conventional circuit, SINAD (signal plus noise pulse to noise pulse distortion) = 58.5 dB, SFDR (spurious free dynamic range) = − 62.3 dB from DR = 66. It turns out that it is improved.

  Although the transistor configuration of the present invention has been described using a Pch transistor, this configuration can also be an Nch transistor. Further, a matrix current output type DAC as shown in FIG. 10 in which current cells are arranged on a matrix and selected by a row and a column can be applied in the same manner as this current output type DAC.

  As described above, the output impedance adjustment circuit has a low impedance when the digital input code is small and has a high impedance when the digital input code is large. That is, the impedance of the output impedance adjustment circuit is equal to the output impedance of the current cell. It is configured to have a digital input code dependency opposite to the digital input code dependency. Further, the output impedance adjustment circuit is configured such that the source and drain of the MOS transistor are constituted by MOS capacitors connected to the analog output line, and the reference voltage applied to the gate is the maximum value of the analog output voltage. In this way, fluctuations in the output impedance can be suppressed by matching the output impedance.

  In the current output type DAC of the first embodiment, by adding an output impedance adjustment circuit to the analog output line and adjusting the output impedance of the current cell, the fluctuation of the output impedance due to the digital input code is suppressed, and the error of the analog output is reduced. A current output type digital / analog converter having a small linearity and capable of operating at high speed can be obtained.

  FIG. 7 shows a second embodiment. In the first embodiment of FIG. 1, the output impedance adjustment circuit is constituted by one MOS transistor capacitor having a large capacitance value and a reference potential. In the second embodiment, the output impedance adjusting circuit is constituted by a plurality of MOS transistor capacitors to which different reference voltages are applied. The configuration of the second embodiment is different from that of the first embodiment only in the configuration of the output impedance adjustment circuit. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The output impedance adjustment circuit 14 of the second embodiment is composed of a plurality of MOS transistors and a control circuit for supplying a reference voltage. Sources, drains, and bulks of a plurality of MOS transistors are connected to an analog output line, and different reference voltages are supplied from the control circuit to the respective gates. In order to increase the digital input code dependency in FIG. 3, for example, in FIG. 3, a reference voltage having a large slope of 0.5 to 1 V is set and in order to reduce the digital input code dependency in FIG. What is necessary is just to set the voltage of 1V or more of the area | region with a small inclination as a reference voltage. The reference voltage is made different so as to reduce the dependency of the digital input code on a plurality of capacitors.

  Thus, by configuring the output impedance adjustment circuit 14 with a plurality of impedance adjustment elements, it is possible to adjust the capacitance values more precisely and finely adjust the impedance. Further, it is possible to add means for further controlling the reference voltage from the control circuit in accordance with the digital input code from the decoder circuit.

  In the current output type DAC of the second embodiment, the output impedance adjustment circuit 14 includes a plurality of MOS transistors, each of which has a source and a drain connected to an analog output line, and each gate has a different reference voltage. By using the applied MOS capacitor, the output impedance of the current cell can be further finely adjusted. In this way, it is possible to obtain a current output type digital-to-analog converter capable of suppressing a change in output impedance due to a digital input code, reducing an analog output error, and having linearity and capable of high-speed operation.

  FIG. 8 shows a third embodiment. The third embodiment is different from the first embodiment in that an output impedance adjustment circuit 15 having a control circuit to which a control signal from a decoder circuit is input, a switch, and a capacitor is provided. The other components are the same as those in the first embodiment, and are given the same reference numerals and explanations thereof are omitted.

  The output impedance circuit 15 of the third embodiment includes a plurality of capacitors connected in series between the analog output line 20 and the reference voltage, and a switch for switching the connection point to the reference voltage at the connection point of each capacitor. The control circuit is configured to control switching of the switch by a signal from the decoder circuit.

  When the digital input code is the smallest, the output impedance adjustment circuit 15 connects the connection point of the first and second capacitors to the reference voltage according to the control signal from the decoder circuit 11, and the output impedance circuit 15 The capacity is composed only of the first capacity value C1. Next, when the digital input code becomes a little larger, the control signal from the decoder circuit 11 causes the first switch to disconnect the connection point between the first and second capacitors from the reference voltage, and the second switch uses the second and third switches. By connecting the connection point of the capacitor to the reference voltage, the capacitance of the output impedance circuit becomes the combined capacitance C1 × C2 / C1 + C2 of the first and second capacitors. That is, as the digital input code increases, the number of capacitors connected in series is increased and the capacitance value is decreased. In this way, by controlling the switching of the connection point with the control signal from the decoder circuit, the output impedance is adjusted according to the digital input code.

  The output impedance adjustment circuit of the third embodiment includes a plurality of capacitors and switches, and the plurality of capacitors are connected in series between the analog output line and the reference potential, and when the digital input code is small, a large capacitance value is obtained. By controlling the switch to form a small capacitance value when the input code is large and adjusting the output impedance, the output impedance fluctuation due to the digital input code is corrected, the analog output error is small, and the linearity is reduced. A current output type digital-analog converter capable of high-speed operation can be obtained.

  Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.

  The current output DAC of the present invention can suppress fluctuations in output impedance by adding an output impedance adjustment circuit to the analog output line and correcting fluctuations in output impedance due to the digital input code. According to the present application, it is possible to obtain a current output type DAC that has few errors in analog output and can operate at high speed and has linearity.

It is a circuit diagram of the current output type DAC of the first embodiment. It is a capacity connection diagram of a MOS transistor. It is a CV characteristic diagram of a MOS transistor. (A) is a 1st Example, (b) is a prior art example, and is a figure which shows the digital input code dependence of output impedance. (A) is a 1st Example, (b) is a prior art example, and is a figure which shows the digital input code dependence of the ILE conversion value. (A) is the first embodiment, (b) is a conventional example, and shows the spectrum of the analog output. It is a circuit diagram of the current output type DAC of the second embodiment. It is a circuit diagram of the current output type DAC of the third embodiment. It is a circuit diagram of a current output type DAC of a conventional example. It is a circuit diagram of a matrix current output type DAC of a conventional example. It is a circuit diagram of a current cell. It is a small signal equivalent circuit diagram at the time of ON of a current cell. It is a small signal equivalent circuit diagram at the time of OFF of a current cell. It is a figure which shows the frequency dependence characteristic of output impedance.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Digital input code 11 Decoder circuit 12,121,122, ... 12n Current cell 13,14,15 Output impedance adjustment circuit 20 Analog output line 21 Output load

Claims (7)

In a current output type digital-analog converter circuit, an output impedance adjustment circuit having a low impedance when a digital input code is small and a high impedance when the digital input code is large is added to an analog output line. Output type digital / analog converter circuit.   2. The current output type digital-analog converter circuit according to claim 1, wherein the impedance of the output impedance adjusting circuit has a digital input code dependency opposite to the digital input code dependency of the output impedance of the current cell. 3. The current output type digital / analog converter circuit according to claim 1, wherein the output impedance adjusting circuit connects a source and a drain of a MOS transistor to an analog output line and applies a reference voltage to a gate. 4. The current output type digital / analog converter circuit according to claim 3 , wherein the reference voltage is a maximum value of an analog output voltage. The output impedance adjustment circuit includes a plurality of MOS transistors, and the plurality of MOS transistors each have a source and a drain connected to the analog output line, and a different reference voltage is applied to each gate. 3. A current output type digital / analog converter circuit according to claim 1 . 3. The current output type digital / analog converter circuit according to claim 1, wherein the output impedance adjustment circuit includes a plurality of capacitors and switches, and switches the switches by a digital input code. The plurality of capacitors are connected in series between an analog output line and a reference potential, and the switch is controlled to form a large capacitance value when the digital input code is small and a small capacitance value when the digital input code is large. 7. The current output type digital / analog converter circuit according to claim 6, wherein:

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