CN116260429B - Non-uniform period ultra-narrow pulse generation circuit and method based on ultra-high speed AND gate - Google Patents
Non-uniform period ultra-narrow pulse generation circuit and method based on ultra-high speed AND gate Download PDFInfo
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- CN116260429B CN116260429B CN202310298950.6A CN202310298950A CN116260429B CN 116260429 B CN116260429 B CN 116260429B CN 202310298950 A CN202310298950 A CN 202310298950A CN 116260429 B CN116260429 B CN 116260429B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a non-uniform period ultra-narrow pulse generating circuit and method based on an ultra-high speed AND gate, comprising an amplifier, wherein the output of the amplifier is connected with a radio frequency power divider, the radio frequency power divider is used for outputting an amplified input signal into two paths of signals with equal power, one path of signals sequentially passes through a numerical control delay device I, the amplifier I, an amplitude adjusting circuit I and a transformer I and is connected with one path of input of a logic AND gate circuit, the other path of signals are connected with the other path of input of the logic AND gate circuit through an amplitude adjusting circuit II and the transformer II, and the output of the logic AND gate circuit is a narrow pulse signal; the transformers I and II are used for converting single-ended radio frequency signals into differential signals with equal amplitude. The invention is based on a super-high-speed digital logic device and a radio frequency delay device, and has the advantages of controllable pulse width, high flexibility, super-narrow pulse width and the like. The design idea of the microwave circuit is adopted, and the signal integrity of the microwave circuit under the condition of high-frequency signals is ensured.
Description
Technical Field
The invention relates to a narrow pulse generation technology, in particular to a non-uniform period ultra-narrow pulse generation method based on an ultra-high speed AND gate
The invention discloses a generating circuit and a generating method, which can generate narrow pulses required by sampling for an ultra-wideband Nyquist folding receiver and belong to the technical field of radio frequency circuits.
Background
The Nyquist folding receiving technology is an analog information receiving technology based on a compressed sensing theory, and can realize a structure of single-channel full-frequency-band signal receiving under the condition of low-rate sampling. The essence of the method is that the received signal is sampled once in simulation by utilizing the radio frequency pulse strings with non-uniform periods, so that the phase information in the radio frequency LO is modulated into each Nyquist zone of the received signal, and the differentiation of different Nyquist Zones (NZ) is realized by utilizing the characteristic that the modulated bandwidths and amplitudes in the different Nyquist Zones (NZ) are not consistent.
In the above-mentioned primary sampling process, according to the frequency and bandwidth of the input sampled signal, a corresponding narrow sampling pulse is required to be matched with the input sampled signal, and theoretically, the relationship is as follows:
the inverse of the pulse width is greater than or equal to the bandwidth of the sampled signal and the subsampled bandwidth
Therefore, the wider the bandwidth of the sampled signal, the narrower the sampling pulse is required, for example, a 16GHz bandwidth, and a narrow pulse of 50ps or less is required to meet the use requirement.
The traditional narrow pulse is mostly generated in a pure analog mode, a step diode is adopted in the mode, and the nonlinearity of the step diode is utilized, so that the narrow pulse is inflexible to use and the pulse width is not adjustable. The pulse width of the existing generation mode of most low-speed digital logic modes is only in the nanosecond order.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide a non-uniform period ultra-narrow pulse generating circuit and method based on an ultra-high speed AND gate.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
the non-uniform period ultra-narrow pulse generating circuit based on the ultra-high speed AND gate comprises an amplifier, wherein the amplifier is used for amplifying an input radio frequency signal, the output of the amplifier is connected with a radio frequency power divider, the radio frequency power divider is used for outputting the amplified input signal into two paths of signals with equal power, one path of signal sequentially passes through a numerical control delay device I, the amplifier I, an amplitude adjusting circuit I and a transformer I and is connected with one path of input of a logic AND gate circuit, the other path of signal is connected with the other path of input of the logic AND gate circuit through an amplitude adjusting circuit II and the transformer II, and the output of the logic AND gate circuit is a narrow pulse signal; the transformers I and II are used for converting single-ended radio frequency signals into differential signals with equal amplitude.
Further, the other path of signal of the radio frequency power divider is connected to the amplitude adjusting circuit II through the numerical control delay device II and the amplifier II, wherein the numerical control delay device II, the amplifier II, the amplitude adjusting circuit II and the transformer II are symmetrically arranged with the corresponding numerical control delay device I, the amplifier I, the amplitude adjusting circuit I and the transformer I in the same model.
Further, the input radio frequency signal is connected with the amplifier through the radio frequency connector I; and the logic AND gate circuit outputs the narrow pulse signal through the radio frequency connector II.
Furthermore, the amplitude adjusting circuit I and the amplitude adjusting circuit II are respectively composed of a capacitor C1, a capacitor C2, a resistor R1, a resistor R2 and a resistor R3, an input signal sequentially passes through the capacitor C1, the resistor R3 and the capacitor C2 and is output, one end of the resistor R1 is grounded, and the other end of the resistor R1 is connected between the capacitor C1 and the resistor R3; one end of the resistor R2 is grounded, and the other end of the resistor R2 is connected between the capacitor C2 and the resistor R3; wherein the capacitors C1 and C2 block the direct current signals; the resistors R1, R2 and R3 jointly realize the adjustment of the signal amplitude and the requirement of input and output impedance.
Specifically, the logic AND gate circuit adopts a logic AND gate device with the model of ASNT 5160-KMC.
Preferably, the amplifier, the radio frequency power divider, the numerical control delay device II, the amplifier II, the amplitude adjusting circuit II, the transformer II, the numerical control delay device I, the amplifier I, the amplitude adjusting circuit I, the transformer I and the logic AND gate circuit are integrated on the same circuit substrate.
The invention also provides a non-uniform period ultra-narrow pulse generation method based on the ultra-high speed AND gate, which divides the sine wave signal into two paths of signals through the power of a radio frequency power divider and the like, enables the two paths of signals to generate required delay, then inputs the two paths of signals generating the delay into a logic AND gate circuit for AND operation, and when the two paths of input signals are both high level, the logic AND gate circuit outputs high level, otherwise outputs low level, thereby realizing the output of narrow pulse signals.
The method for generating the required delay of the two paths of signals is that at least one path of signals enters the numerical control delay device and the required delay is generated through the numerical control delay device.
Further, after two paths of signals divided by the radio frequency power divider are respectively delayed through the numerical control delay device, the two paths of signals are respectively input into the logic AND gate circuit through the amplifier, the amplitude adjusting circuit and the transformer for AND operation, and the numerical control delay device, the amplifier, the amplitude adjusting circuit and the transformer corresponding to the two paths of signals are symmetrically arranged in the same model, so that the delay absolute errors and the random errors of the two paths of delay signals input into the logic AND gate circuit are minimized.
Compared with the prior art, the invention has the following beneficial effects:
the core of the invention is based on an ultra-high speed digital logic device and a radio frequency delay device, and combines a microwave circuit design method and a microwave circuit design process, and has the advantages of controllable pulse width, high flexibility, ultra-narrow pulse width and the like. The traditional step diode and other analog modes have the defects that the generated pulse width is not narrow enough, the waveform is irregular, the pulse width is not adjustable after the circuit is designed, and the like. The invention adopts a digital control mode to realize the delay of signals, and the pulse width can be flexibly controlled; the design idea of the microwave circuit is adopted, and the signal integrity of the microwave circuit under the condition of high-frequency signals is ensured.
The invention adopts a symmetrical architecture design mode, so that the influence of devices on a circuit is reduced to the minimum, and the consistency of parameters in various environments and in the use process is ensured.
The invention takes the ultra-high speed AND gate ASNT5160-KMC as a core, has the highest working frequency of 50GHz, and combines the design method of a radio frequency microwave circuit, so that the ultra-high speed AND gate ASNT5160-KMC has the characteristics of narrow pulse width (ps-level) and flexible and controllable pulse width.
Drawings
Fig. 1-schematic diagram of a narrow pulse generation circuit of the present invention.
Fig. 2-the amplitude adjusting circuit structure of the present invention.
Fig. 3-the high speed and gate of the present invention produces a narrow pulse schematic.
Fig. 4-a delay circuit diagram of an asymmetric architecture of the present invention.
Fig. 5-a delay circuit diagram of the symmetrical architecture of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
Referring to fig. 1, the non-uniform periodic ultra-narrow pulse generating circuit based on the ultra-high speed and gate comprises an amplifier, wherein the amplifier is used for amplifying an input radio frequency signal, the output of the amplifier is connected with a radio frequency power divider, the radio frequency power divider is used for outputting the amplified input signal into two paths of signals with equal power, one path of signals sequentially passes through a numerical control delay device I, the amplifier I, an amplitude adjusting circuit I and a transformer I and is connected with one path of input of a logic AND gate circuit, the other path of signals is connected with the other path of input of the logic AND gate circuit through an amplitude adjusting circuit II and the transformer II, and the output of the logic AND gate circuit is a narrow pulse signal; the transformers I and II are used for converting single-ended radio frequency signals into differential signals with equal amplitude.
Further, the other path of signal of the radio frequency power divider is connected to the amplitude adjusting circuit II through the numerical control delay device II and the amplifier II, wherein the numerical control delay device II, the amplifier II, the amplitude adjusting circuit II and the transformer II are symmetrically arranged with the corresponding numerical control delay device I, the amplifier I, the amplitude adjusting circuit I and the transformer I in the same model.
In order to realize signal input and output more conveniently, the radio frequency signal input by the invention is connected with the amplifier through the radio frequency connector I; and the logic AND gate circuit outputs the narrow pulse signal through the radio frequency connector II. Thus, the signal input end is directly spliced with the radio frequency connector I, namely, the signal input is realized; the output signal receiving end is directly spliced with the radio frequency connector II, so that signal output is realized.
Specifically, the amplitude adjusting circuit I and the amplitude adjusting circuit II of the invention are composed of capacitors C1 and C2, and resistors R1, R2 and R3, an input signal sequentially passes through the capacitor C1, the resistor R3 and the capacitor C2 and then is output, one end of the resistor R1 is grounded, and the other end is connected between the capacitor C1 and the resistor R3; one end of the resistor R2 is grounded, and the other end of the resistor R2 is connected between the capacitor C2 and the resistor R3; wherein the capacitors C1 and C2 block the direct current signals; the resistors R1, R2 and R3 jointly realize the adjustment of the signal amplitude and the requirement of input and output impedance.
The amplifier, the radio frequency power divider, the numerical control delay device II, the amplifier II, the amplitude adjusting circuit II, the transformer II, the numerical control delay device I, the amplifier I, the amplitude adjusting circuit I, the transformer I and the logic AND gate circuit are integrated on the same circuit substrate.
The invention also provides a non-uniform period ultra-narrow pulse generation method based on the ultra-high speed AND gate, which divides the sine wave signal into two paths of signals through the power of a radio frequency power divider and the like, enables the two paths of signals to generate required delay, then inputs the two paths of signals generating the delay into a logic AND gate circuit for AND operation, and when the two paths of input signals are both high level, the logic AND gate circuit outputs high level, otherwise outputs low level, thereby realizing the output of narrow pulse signals.
The method for generating the required delay of the two paths of signals is that at least one path of signals enters the numerical control delay device and the required delay is generated through the numerical control delay device.
Preferably, the two paths of signals divided by the radio frequency power divider are respectively input into the logic and gate circuit through the amplifier, the amplitude adjusting circuit and the transformer for performing AND operation after the two paths of delayed signals are respectively generated by the numerical control delay device, and the numerical control delay device, the amplifier, the amplitude adjusting circuit and the transformer corresponding to the two paths of signals are symmetrically arranged in the same model, so that the delay absolute errors and the random errors of the two paths of delayed signals input into the logic and gate circuit are minimized.
The present invention will be described in further detail with reference to examples, but embodiments of the present invention are not limited thereto.
Referring to fig. 1, the whole circuit of the invention is provided with an input port of a sine wave signal and an output port of a narrow pulse signal, the frequency of the input port is designed to be 2GHz +/-100 MHz, and the frequency of the signal is the repetition frequency of the output pulse. The output port outputs a narrow pulse signal of about 30ps width, and the corresponding main frequency is about the inverse of the pulse width, about 30GHz. In order to ensure the performance as much as possible, a radio frequency connector with the working frequency reaching 50GHz is selected, and a 2.4-KFD2 type connector of Ailite company is selected in the embodiment of the invention, wherein the characteristic impedance is 50 ohms, and the working frequency can reach 50GHz.
A1 shown in FIG. 1 is an amplifier for amplifying an input radio frequency signal, and in the embodiment, model NC10200C-103 is selected, working frequency is 1-3GHz, and gain is 14dB.
B1 is a radio frequency power divider, and is used for dividing one path of radio frequency signal into two paths of signals with equal power for subsequent and processing, and in the embodiment, the model is NC6520C-103.
In the embodiment, a numerical control delayer I and a numerical control delayer II which are manufactured by electronic thirteen and are of the model NC12115C-106 are selected, delay steps corresponding to each bit are 5ps, and control bits are 8 bits. Thus, the maximum delay time is calculated as
Thus, when the input signal is 2GHz, i.e. 500ps period, the digitally controlled delay device can cover the delay of the entire waveform of the 2GHz signal.
D1 and D2 are an amplifier i and an amplifier ii, which are used to compensate for attenuation in the transmission process of the delay device and the signal link, so as to ensure that the signal meets the amplitude requirement in the subsequent use. In the embodiment, the two amplifiers are NC10200C-103, the working frequency is 0.3-3GHz, and the gain is 29dB.
E1 and E2 are an amplitude adjusting circuit I and an amplitude adjusting circuit II, and the amplitude of the signal is adjusted to be about 6dB, so that after the signal is converted into a differential signal through a transformer, the CML level standard meets the CML level standard of the device ASNT 5160-KMC. As shown in fig. 2, the two amplitude adjusting circuits are pi-type resistor attenuation networks, and are composed of capacitors C1, C2 and resistors R1, R2 and R3, wherein the capacitors C1 and C2 block direct current signals; r1, R2 and R3 jointly realize the adjustment of signal amplitude and the requirement of 50 ohms of input/output impedance, and different signal output/input power ratios can be obtained according to different resistance values.
F1 and F2 are a radio frequency transformer i and a radio frequency transformer ii, which are used for converting single-ended radio frequency signals into differential signals with equal amplitude, in the embodiment, the two radio frequency transformers are RFT-5-1T, the working frequency is 0.3-6 GHz, and the insertion loss is about 3dB; the transformer is combined with the amplitude adjusting circuit to skillfully convert the single-ended radio frequency signal into the CML level standard, and compared with the traditional conversion mode adopting a digital CML level chip, the transformer almost does not need a peripheral auxiliary circuit, and the circuit is simpler and easier to integrate.
G1 is a high-speed logic AND gate circuit, in the embodiment, the model is ASNT5160-KMC, and the purpose of generating narrow pulse signals is realized through the AND operation of two groups of input signals. When the two paths of input signals are in high level, the output is in high level, otherwise, the output is in low level. The signal generation diagram is shown in fig. 3.
In the design process, a symmetrical architecture design is adopted, so that two paths of phases and signals have the same parameter characteristics, and then random factors can be offset in the same direction, and the consistency of links is ensured.
From the aspect of functions, the delay function can be realized by only one path of radio frequency delay device; however, under various circumstances, the amplitude and phase change characteristics of the device will cause the relative delay of the two links to change. Meanwhile, in order to meet the use requirement, the absolute delay of two paths of signals is not allowed to exceed one sine wave period, so that the design of a symmetrical framework is adopted, the devices of the same type and the same batch are adopted in a peer-to-peer layout and wiring mode, and the absolute delay error and the random error of the two paths of delay signals are minimized. The schematic block diagrams of the two architectures are shown in fig. 4 and 5.
The invention realizes the generation of the variable-period ultra-narrow pulse signal based on the ultra-high speed logic device and the radio frequency microwave circuit. The advantages of the radio frequency circuit and the ultra-high speed digital circuit are combined, the delay of the signals is realized in a numerical control radio frequency delay mode, and further, picosecond ultra-narrow pulse signals are generated by the signal phases with time difference.
In the circuit, the frequency modulation signal with the input signal frequency of 2GHz +/-100 MHz is selected and the time shift step of the radio frequency delayer is about 5ps, and the time adjustable delay can be conveniently realized due to the adoption of a digital control mode. In the design, the delay circuit adopts a symmetrical framework, the same device is selected, the same signal transmission path is designed, and the consistency of two paths of phases and the change of signals along with the environment such as temperature is ensured, so that stable narrow pulse output can be finally generated. Meanwhile, a radio frequency differential conversion method is adopted to replace a digital CML level conversion mode, so that the structure is simpler and the integration is easier. Because the pulse signal is narrow and the corresponding signal frequency is high, in the design consideration of the whole circuit, the design method of a microwave circuit is adopted in the aspects of signal transmission and device use, and the circuit board adopts a Rogowski 5880 substrate with good high-frequency characteristics.
The above examples of the present invention are merely illustrative of the present invention and are not intended to limit the embodiments of the present invention. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. Not all embodiments are exhaustive. Obvious changes and modifications which are extended by the technical proposal of the invention are still within the protection scope of the invention.
Claims (6)
1. An ultra-high speed AND gate based non-uniform period ultra-narrow pulse generation circuit is characterized in that: the device comprises an amplifier, a radio frequency power divider, a digital control delay device I, an amplitude adjusting circuit I and a transformer I, wherein the amplifier is used for amplifying an input radio frequency signal, the output of the amplifier is connected with the radio frequency power divider, the radio frequency power divider is used for outputting the amplified input signal into two paths of signals with equal power, one path of signals sequentially pass through the digital control delay device I, the amplifier I, the amplitude adjusting circuit I and the transformer I and are connected with one path of input of a logic AND gate circuit, the other path of signals pass through the amplitude adjusting circuit II and the transformer II and are connected with the other path of input of the logic AND gate circuit, and the output of the logic AND gate circuit is a narrow pulse signal; the transformer I and the transformer II are used for converting the single-ended radio frequency signals into differential signals with equal amplitude;
the other path of signal of the radio frequency power divider is connected to the amplitude adjusting circuit II through the numerical control delay device II and the amplifier II, wherein the numerical control delay device II, the amplifier II, the amplitude adjusting circuit II and the transformer II are symmetrically arranged with the corresponding numerical control delay device I, the amplifier I, the amplitude adjusting circuit I and the transformer I in the same model.
2. The ultra-high speed and gate based non-uniform periodic ultra-narrow pulse generation circuit of claim 1, wherein: the input radio frequency signal is connected with the amplifier through a radio frequency connector I; and the logic AND gate circuit outputs the narrow pulse signal through the radio frequency connector II.
3. The ultra-high speed and gate based non-uniform periodic ultra-narrow pulse generation circuit of claim 1, wherein: the amplitude adjusting circuit I and the amplitude adjusting circuit II are composed of capacitors C1 and C2, resistors R1 and R2 and R3, input signals are sequentially output after passing through the capacitor C1, the resistor R3 and the capacitor C2, one end of the resistor R1 is grounded, and the other end of the resistor R1 is connected between the capacitor C1 and the resistor R3; one end of the resistor R2 is grounded, and the other end of the resistor R2 is connected between the capacitor C2 and the resistor R3; wherein the capacitors C1 and C2 block the direct current signals; the resistors R1, R2 and R3 jointly realize the adjustment of the signal amplitude and the requirement of input and output impedance.
4. The ultra-high speed and gate based non-uniform periodic ultra-narrow pulse generation circuit of claim 1, wherein: the logical AND gate circuit adopts a logical AND gate device with the model of ASNT 5160-KMC.
5. The ultra-high speed and gate based non-uniform periodic ultra-narrow pulse generation circuit of claim 1, wherein: the amplifier, the radio frequency power divider, the numerical control delay device II, the amplifier II, the amplitude adjusting circuit II, the transformer II, the numerical control delay device I, the amplifier I, the amplitude adjusting circuit I, the transformer I and the logic AND gate circuit are integrated on the same circuit substrate.
6. A non-uniform period ultra-narrow pulse generation method based on ultra-high speed AND gate is characterized in that: dividing the sine wave signal into two paths of signals through the equal power of the radio frequency power divider, enabling the two paths of signals to generate required delay, inputting the two paths of signals for generating the delay into the logic AND gate circuit for AND operation, outputting high level by the logic AND gate circuit when the two paths of input signals are both high level, otherwise outputting low level, and thus realizing narrow pulse signal output;
the method for generating the required delay of the two paths of signals is that at least one path of signals enters a numerical control delay device and generates the required delay through the numerical control delay device;
the two paths of signals divided by the radio frequency power divider are respectively input to the logic AND gate circuit through the amplifier, the amplitude adjusting circuit and the transformer for AND operation after the two paths of signals are delayed by the numerical control delay device, so that the delay absolute errors and the random errors of the two paths of delay signals input to the logic AND gate circuit are minimized.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102170277A (en) * | 2011-01-20 | 2011-08-31 | 中国科学院半导体研究所 | Picosecond-accuracy narrow-pulse width transistor-transistor logic (TTL) signal acquisition method based on phase shift AND operation |
| CN102324951A (en) * | 2011-08-24 | 2012-01-18 | 东南大学 | Ultra-wideband pulse generator based on digital circuit |
| CN111200236A (en) * | 2018-11-20 | 2020-05-26 | 余姚舜宇智能光学技术有限公司 | High-frequency narrow-pulse semiconductor laser driving circuit |
| WO2022258034A1 (en) * | 2021-06-11 | 2022-12-15 | 成都飞云科技有限公司 | Pulse generation apparatus and pulse control method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10355320B3 (en) * | 2003-11-27 | 2005-04-14 | Infineon Technologies Ag | High resolution digital pulse width modulator for control of DC-DC converter with combining of 2 pulse width modulated intermediate signals via logic stage |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102170277A (en) * | 2011-01-20 | 2011-08-31 | 中国科学院半导体研究所 | Picosecond-accuracy narrow-pulse width transistor-transistor logic (TTL) signal acquisition method based on phase shift AND operation |
| CN102324951A (en) * | 2011-08-24 | 2012-01-18 | 东南大学 | Ultra-wideband pulse generator based on digital circuit |
| CN111200236A (en) * | 2018-11-20 | 2020-05-26 | 余姚舜宇智能光学技术有限公司 | High-frequency narrow-pulse semiconductor laser driving circuit |
| WO2022258034A1 (en) * | 2021-06-11 | 2022-12-15 | 成都飞云科技有限公司 | Pulse generation apparatus and pulse control method |
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