CN116248109A - Level shift circuit and half-bridge conversion circuit with same - Google Patents
Level shift circuit and half-bridge conversion circuit with same Download PDFInfo
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- CN116248109A CN116248109A CN202310117163.7A CN202310117163A CN116248109A CN 116248109 A CN116248109 A CN 116248109A CN 202310117163 A CN202310117163 A CN 202310117163A CN 116248109 A CN116248109 A CN 116248109A
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- H—ELECTRICITY
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
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- H—ELECTRICITY
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Abstract
The invention discloses a level shift circuit and a half-bridge conversion circuit with the same. The level shift circuit includes: an input unit for providing a logic drive current signal, the common mode voltage of the logic drive current signal having a first change state from a low level to a high level and a second change state from the high level to the low level; the first current generation unit is used for generating a positive transient common mode current, and a common mode voltage corresponding to the positive transient common mode current has a first change state; the second current generation unit is used for generating a negative transient common mode current, and the common mode voltage corresponding to the negative transient common mode current has a second change state; the interference filtering unit is used for counteracting parasitic current generated by common mode voltage change of the logic driving current signal; and an output unit for converting the logic driving current signal into a floating control signal. The circuit solves the problem that transient voltage of the voltage level shifter interferes with normal operation of the level shifter.
Description
Technical Field
The present invention relates to the field of electronic technology, and in particular, to a level shift circuit and a half-bridge conversion circuit having the same.
Background
The half-bridge driver comprises a low-side driver and a high-side driver, and is widely applied to the fields of power management, motor driving, synchronous rectification and the like.
The voltage level shifter is responsible for converting the logic control signal to ground reference into the floating control signal of the high-side driver as an important module of the half-bridge driver. In the process of controlling the high-side driver, the transient voltage of the floating ground can be rapidly changed to generate transient common-mode voltage and current signals, and the rapid change of the transient common-mode signal can generate serious interference on the normal operation of the level shifter, so that the normal operation of the half-bridge driver is influenced, and the reliability design of the driver is challenged. For driving wide bandgap semiconductor gallium nitride and silicon carbide power devices, floating ground transient common mode voltage variations can exceed 100V/ns, which presents challenges to the anti-transient common mode interference capability of level shifters in half-bridge drivers. Conventional voltage level shifters do not meet this requirement.
Disclosure of Invention
The embodiment of the invention provides a level shifting circuit and a half-bridge conversion circuit with the same, which at least solve the technical problem that transient voltage of a voltage level shifter interferes with normal operation of the level shifter.
According to an aspect of an embodiment of the present invention, there is provided a level shift circuit including: an input unit for providing a logic drive current signal, the common mode voltage of the logic drive current signal having a first change state from a low level to a high level and a second change state from the high level to the low level; the first current generation unit is used for generating a positive transient common mode current, and a common mode voltage corresponding to the positive transient common mode current has a first change state; the second current generation unit is electrically connected with the first current generation unit and is used for generating a negative transient common mode current, and a common mode voltage corresponding to the negative transient common mode current has a second change state; the interference filtering unit is respectively and electrically connected with the input unit, the first current generating unit and the second current generating unit and is used for counteracting parasitic current generated by common-mode voltage change of the logic driving current signal according to the positive transient common-mode current and the negative transient common-mode current; and the output unit is electrically connected with the interference filtering unit and is used for converting the logic driving current signal into a floating control signal.
Optionally, the input unit includes: a pulse generator for generating a pulse voltage signal; and the first switch module is electrically connected with the output end of the pulse generator and the ground level and is used for generating a logic driving current signal according to the pulse voltage signal.
Optionally, the first switch module includes a first transistor and a first capacitor, wherein: the grid electrode of the first transistor is electrically connected with the output end of the pulse generator, the drain end of the first transistor is electrically connected with the first end of the first capacitor, and the source end of the first transistor and the second end of the first capacitor are electrically connected with the ground level.
Optionally, the first current generating unit includes: the second switch module is electrically connected with the ground level and is used for generating positive transient common mode current; the first current mirror module is electrically connected with the second switch module and the interference filtering unit respectively and is used for copying the positive transient common mode current into output current.
Optionally, the second switch module includes a second transistor and a second capacitor, wherein: the second transistor is of the same type and size as the first transistor; the drain terminal of the second transistor is electrically connected with the first output terminal of the first current mirror module and the first terminal of the second capacitor respectively, the source terminal of the second transistor, the grid electrode of the second transistor and the second terminal of the second capacitor are electrically connected with the ground level, and the second output terminal of the first current mirror module is used for providing output current.
Optionally, the first current mirror module includes a first PMOS tube and a second PMOS tube, wherein: the first PMOS tube is interconnected with the source end of the second PMOS tube, the grid electrode of the first PMOS tube is interconnected with the grid electrode of the second PMOS tube, and then the grid electrode of the first PMOS tube and the drain end of the first PMOS tube jointly form a first output end of the first current mirror module, and the drain end of the second PMOS tube is used as a second output end of the first current mirror module.
Optionally, the second current generating unit includes: the third switch module is electrically connected with the ground level and is used for generating negative transient common mode current; the second current mirror module is electrically connected with the third switch module, the first current generating unit and the interference filtering unit respectively and is used for copying the negative transient common mode current into input current.
Optionally, the third switching module includes a third transistor and a third capacitor, wherein: the third transistor is of the same type and size as the first transistor; the drain terminal of the third transistor is electrically connected to the first input terminal of the second current mirror module and the first terminal of the third capacitor, respectively, and the source terminal of the third transistor, the gate of the third transistor and the second terminal of the third capacitor are all electrically connected to ground, and the second input terminal of the second current mirror module is used for providing input current.
Optionally, the second current mirror module includes a first NMOS transistor and a second NMOS transistor, wherein: the first NMOS tube is interconnected with the source end of the second NMOS tube, the grid electrode of the first NMOS tube and the drain end of the first NMOS tube are mutually connected to form a first input end of the second current mirror module, and the drain end of the second NMOS tube is used as a second input end of the second current mirror module and is electrically connected with the first current generating unit.
Optionally, the second current mirror module further includes a third NMOS transistor, gates of the third NMOS transistor, the first NMOS transistor, and the second NMOS transistor are interconnected, source ends of the third NMOS transistor, the first NMOS transistor, and the second NMOS transistor are interconnected, and a drain end of the third NMOS transistor is electrically connected to the interference filtering unit.
Optionally, the interference filtering unit includes: the third current mirror module is respectively and electrically connected with the first current generating unit and the output unit; and the fourth current mirror module is respectively and electrically connected with the input unit, the second current generating unit and the output unit.
Optionally, the third current mirror module includes a fourth NMOS transistor and a fifth NMOS transistor, wherein: the source ends of the fourth NMOS tube and the fifth NMOS tube are interconnected, the grid electrodes of the fourth NMOS tube and the fifth NMOS tube are electrically connected with the drain end of the fourth NMOS tube to form a first current generating unit, and the drain end of the fifth NMOS tube is electrically connected with the output unit.
Optionally, the fourth current mirror module includes a third PMOS transistor and a fourth PMOS transistor, wherein: the source ends of the third PMOS tube and the fourth PMOS tube are connected with each other, the grid electrodes of the third PMOS tube and the fourth PMOS tube are connected with the drain end of the third PMOS tube after being connected with each other, the input unit is electrically connected with the second current generating unit, and the drain end of the fourth PMOS tube is electrically connected with the output unit.
Optionally, the input unit includes two first switch modules electrically connected to the pulse generator, and the level shift circuit includes: two first current generating units; two second current generating units; and the fourth current mirror module is electrically connected with the output unit through the drain end of the fourth PMOS tube.
According to another aspect of the embodiment of the present invention, there is also provided a half-bridge conversion circuit including the level shift circuit described above.
In the embodiment of the invention, the first current generating unit is adopted to generate the positive transient common mode current and the common mode voltage corresponding to the positive transient common mode current have a first change state, the second current generating unit is adopted to generate the negative transient common mode current and the common mode voltage corresponding to the negative transient common mode current has a second change state, and then the parasitic current generated by the common mode voltage is counteracted by the interference filtering unit according to the positive transient common mode current and the negative transient common mode current, so that the purpose of eliminating the parasitic current generated by the positive transient voltage and the negative transient voltage change of the floating ground is achieved, the driving current triggered by an input signal is ensured to be conducted to an output circuit, the normal operation of the level voltage shifter is realized, and the technical problem that the transient voltage of the voltage level shifter interferes the normal operation of the level shifter is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a logic block diagram of a level shifting circuit provided in accordance with an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of an input unit in a level shift circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a first current generating unit in a level shift circuit according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a second current generating unit in a level shift circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a level shift circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the operating principle of the voltage level shifter during a positive transient voltage change according to the circuit configuration of FIG. 5;
FIG. 7 is a schematic diagram of the operating principle of the voltage level shifter upon a negative transient voltage change according to the circuit configuration of FIG. 5;
fig. 8 is a schematic circuit diagram of an output unit in a level shift circuit according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of a half-bridge conversion circuit according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a level shift circuit according to an embodiment of the present invention, as shown in fig. 1, including:
an input unit 10 for providing a logic drive current signal having a first change state in which a common mode voltage of the logic drive current signal changes from a low level to a high level and a second change state in which the high level changes to the low level;
a first current generating unit 20 for generating a positive transient common mode current, the common mode voltage corresponding to the positive transient common mode current having a first variation state;
a second current generating unit 30 electrically connected to the first current generating unit 20, for generating a negative transient common mode current, the common mode voltage corresponding to the negative transient common mode current having a second variation state;
the interference filtering unit 40 is electrically connected with the input unit 10, the first current generating unit 20 and the second current generating unit 30 respectively, and is used for counteracting parasitic current generated by the common mode voltage of the logic driving current signal according to the positive transient common mode current and the negative transient common mode current;
the output unit 50 is electrically connected to the disturbance rejection unit 40, and is configured to convert the logic driving current signal into a floating control signal.
Through the level shift circuit, the purpose of eliminating parasitic current generated by the change of the positive transient voltage and the negative transient voltage of the floating ground can be achieved, so that the driving current triggered by an input signal can be transmitted to the output circuit, the normal operation of the level voltage shifter is realized, and the technical problem that the transient voltage of the voltage level shifter interferes with the normal operation of the level shifter is solved.
In some alternative embodiments, the input unit includes a pulse generator and a first switch module, wherein: the pulse generator is used for generating a pulse voltage signal; the first switch module is electrically connected with the output end of the pulse generator and the ground level and is used for generating a logic driving current signal according to the pulse voltage signal.
Exemplary, as shown in FIG. 2, the first switch module includes a transistor NHM_G (first transistor) and a capacitor C ds (first capacitance), wherein: the grid electrode of the transistor NHM_G is electrically connected with the output end of the pulse generator, and the drain end of the transistor NHM_G is connected with the capacitor C ds Is electrically connected to the source terminal of transistor NHM_G and capacitor C ds Is all at the level V with the ground SS And (5) electric connection.
Specifically, C ds Is parasitic capacitance from drain end to source end of transistor NHM_G, its drain end output current is I out ＝I Cds +I ds Wherein I Cds For flowing through the capacitor C ds Current of I ds Is the channel current of transistor hnm_g. I out As a driving current of the voltage level shifter, it can be seen from its expression that the driving current includes I Cds I when the transient voltage of the drain terminal changes from low to high Cds In the direction of the arrow shown in FIG. 2, I is positive out Greater than I ds The method comprises the steps of carrying out a first treatment on the surface of the I when the transient voltage of the drain terminal changes from high to low Cds Negative in the direction of the arrow in FIG. 2, when I out Less than I ds If the drain voltage changes too fast, I may result out Is 0 or negative.
In some alternative embodiments, the first current generating unit comprises a second switching module and a first current mirror module, wherein: the second switch module is electrically connected with the ground level and is used for generating positive transient common mode current; the first current mirror module is electrically connected with the second switch module and the interference filtering unit respectively and is used for copying the positive transient common mode current into output current.
Ideally, the voltage level shifter only requires I ds As an input drive current, due to flowing through C ds Is (are) parasitic current I Cds In order to eliminate the interference, in this embodiment, a dummy transistor of the input terminal with the same size is added to detect a positive transient parasitic current flowing through the drain-source terminal and cancel the parasitic current between the drain-source terminal of the first transistor nhm_g in the input unit, thereby eliminating the interference of the parasitic current to the voltage level shifter.
Exemplary, as shown in FIG. 3, the second switch module includes a transistor HNM_P (second transistor) and a capacitor C dsP (second capacitance), wherein: the transistor hnm_p and the transistor nhm_g have the same type and size; the drain terminal of the transistor HNM_P is respectively connected with the first output terminal of the first current mirror module and the capacitor C dsP A source terminal of the transistor HNM_P, a gate of the transistor HNM_P and a capacitor C dsP Is all at the level V with the ground SS The second output end of the first current mirror module is used for providing output current.
The first current mirror module may include a PMOS tube PM1 (first PMOS tube) and a PMOS tube PM2 (second PMOS tube), as shown in fig. 3, wherein: the source ends of the PMOS tube PM1 and the PMOS tube PM2 are interconnected, and the drain ends of the PMOS tube PM2 and the PMOS tube PM1 form a first output end of the first current mirror module together after the grid electrodes of the PMOS tube PM1 and the PMOS tube PM2 are interconnected, wherein the drain end of the PMOS tube PM2 is used as a second output end of the first current mirror module.
Specifically, as shown in FIG. 3, the gate and source of transistor HNM_P are shorted to ground level V SS Its channel current is zero. When V is BST When the voltage is changed from low to high, the drain terminal D_P of the transistor HNM_P is also changed from low to high, and the parasitic current I CdsP Through capacitor C by D_P port dsP Inflow ground level V SS . PMOS tube PM1 and PMOS tube of first current mirror modulePM2 is the same size so the output current of the OUTP port I OUTP ＝I CdsP . When V is BST When changing from high to low, I CdsP From ground level V SS End pass C dsP Flows into the D_P port and flows into V through the parasitic body diode of the PMOS tube PM1 BST The gate end voltage of the PMOS tube PM1 is higher than the source end voltage, and the PMOS tube PM1 is cut off, so that the PMOS tube PM2 is also in a cut-off state, I OUTP Zero. The circuit shown in fig. 3 has the characteristic of unidirectional positive transient current detection.
In some alternative embodiments, the second current generating unit comprises a third switching module and a second current mirror module, wherein: the third switch module is electrically connected with the ground level and is used for generating negative transient common mode current; the second current mirror module is electrically connected with the third switch module, the first current generating unit and the interference filtering unit respectively and is used for copying the negative transient common mode current into input current.
Similarly, to eliminate flow through C ds Is (are) parasitic current I Cds In this embodiment, by adding dummy transistors at the input terminals with the same size, the negative transient parasitic current flowing through the drain-source terminal is detected and counteracted with the parasitic current between the drain-source terminals of the transistor nhm_g in the input unit, so as to eliminate the interference of the parasitic current on the voltage level shifter.
Exemplary, as shown in FIG. 4, the third switch module includes a transistor HNM_N (third transistor) and a capacitor C dsN (third capacitance), wherein: the transistor hnm_n and the transistor nhm_g have the same type and size; the drain terminal of the transistor HNM_N is respectively connected with the first input terminal of the second current mirror module and the capacitor C dsN A source terminal of the transistor HNM_N, a gate of the transistor HNM_N and a capacitor C dsN Is all at the level V with the ground SS The second input end of the second current mirror module is used for providing input current.
The second current mirror module may include an NMOS transistor NM1 (first NMOS transistor), an NMOS transistor NM2 (second NMOS transistor), and an NMOS transistor NM3 (third NMOS transistor), as shown in fig. 4, wherein: the NMOS tube NM1 is interconnected with the source ends of the NMOS tube NM2 and the NMOS tube NM3, the grid electrodes of the NMOS tube NM1, the NMOS tube NM2 and the NMOS tube NM3 are interconnected to form a first input end of a second current mirror module together with the drain end of the NMOS tube NM1, and the drain end of the NMOS tube NM2 is used as a second input end of the second current mirror module and is electrically connected with the first current generating unit; the drain terminal of the NMOS tube NM3 is electrically connected with the interference filtering unit.
Specifically, as shown in FIG. 4, the gate and source terminals of the transistor HNM_N are shorted to the ground level V SS Its channel current is zero. When V is SW Parasitic current I when changing from high to low CdsN From ground level V SS Port through capacitance C dsN And NMOS tube NM1 inflow V SW . The NMOS tube NM1, NM2 and NM3 of the current mirror structure have the same size, so the output current I of the OUTN port OUTN1 ＝I OUTN2 ＝I CdsN . When V is SW When changing from low to high, I CdsN From V SW Parasitic diode through NMOS tube NM1 flows into capacitor C dsN To ground level V SS NMOS tube NM1 is cut off, I OUTN1 And I OUTN2 Zero.
In some alternative embodiments, the interference filtering unit includes: the third current mirror module is respectively and electrically connected with the first current generating unit and the output unit; and the fourth current mirror module is respectively and electrically connected with the input unit, the second current generating unit and the output unit.
In the above embodiment, the third current mirror module may include a fourth NMOS transistor and a fifth NMOS transistor, wherein: the source ends of the fourth NMOS tube and the fifth NMOS tube are interconnected, the grid electrodes of the fourth NMOS tube and the fifth NMOS tube are electrically connected with the drain end of the fourth NMOS tube to form a first current generating unit, and the drain end of the fifth NMOS tube is electrically connected with the output unit.
In the above embodiment, the fourth current mirror module may include a third PMOS transistor and a fourth PMOS transistor, where: the third PMOS tube is connected with the source end of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain end of the fourth PMOS tube is electrically connected with the input unit, and the drain end of the fourth PMOS tube is electrically connected with the output unit.
In the above embodiment, as shown in fig. 5, the input unit 10 may include two first switching modules electrically connected with the pulse generator 110. One of the first switch modules comprises a transistor HNM1 and a capacitor C1, the other first switch module comprises a transistor HNM2 and a capacitor C2, the transistors HNM1 and HNM2 are first transistors in different first switch modules, and the capacitors C1 and C2 are first capacitors in different first switch modules.
In the above embodiment, as shown in fig. 5, the level shift circuit may include two first current generating units 20, two second current generating units 30, and two interference filtering units 40, the interference filtering units 40 are electrically connected to the first current generating units 30 and the second current generating units 30 in a one-to-one correspondence, respectively, and a fourth current mirror module of the two interference filtering units 40 is electrically connected to the output unit 50.
As shown in fig. 5, in one first current generating unit 20, the second switch module includes a transistor HNM3 and a capacitor C3, the first current mirror module includes a PMOS transistor PM5 and a PMOS transistor PM6, in the other first current generating unit 20, the second switch module includes a transistor HNM4 and a capacitor C4, the first current mirror module includes a PMOS transistor PM11 and a PMOS transistor PM12, wherein the transistors HNM3 and HNM4 are second transistors in different first current generating units, the capacitors C3 and C4 are second capacitors in different first current generating units, the PMOS transistors PM5 and PM11 are first PMOS transistors in different first current generating units, and the PMOS transistors PM6 and PM12 are second PMOS transistors in different first current generating units; in one second current generation unit 30, the third switch module includes a transistor HNM5 and a capacitor C5, the second current mirror module includes an NMOS transistor NM11, an NMOS transistor NM12, and an NMOS transistor NM13, in the other second current generation unit 30, the third switch module includes a transistor HNM6 and a capacitor C6, the second current mirror module includes an NMOS transistor NM14, an NMOS transistor NM15, and an NMOS transistor NM16, where the transistors HNM5 and HNM6 are third transistors in different second current generation units, the capacitor C5 and the capacitor C6 are third capacitors in different second current generation units, the NMOS transistors NM11 and NM14 are first NMOS transistors in different first current generation units, the NMOS transistors NM12 and NM15 are second NMOS transistors in different first current generation units, and the NMOS transistors NM13 and NM16 are third NMOS transistors in different first current generation units; in the interference filtering unit 40, the third current mirror module comprises an NMOS tube NM7 and an NMOS tube NM8, and the fourth current mirror module comprises a PMOS tube PM7 and a PMOS tube PM8; in another interference filtering unit 40, the third current mirror module includes an NMOS tube NM9 and an NMOS tube NM10, and the fourth current mirror module includes a PMOS tube PM9 and a PMOS tube PM10, where the NMOS tubes NM7 and NM9 are fourth NMOS tubes in different interference filtering units, the NMOS tubes NM8 and NM10 are fifth NMOS tubes in different interference filtering units, the PMOS tubes PM7 and PM9 are third PMOS tubes in different interference filtering units, and the PMOS tubes PM8 and PM10 are fourth PMOS tubes in different interference filtering units.
Specifically, as shown in fig. 5, HNM1 to HNM6 are high voltage transistors of the same type and have the same size. C1-C6 are parasitic capacitances of drain and source ends of HNM1-HNM6 respectively, and the capacitances are the same. PM5-PM12 are P-type transistors of the same size, NM7-NM10 are N-type transistors of the same size, and NM11-NM16 are N-type transistors of the same size. The narrow pulse generator circuit module is a low-voltage side module, and the power supply is V DD The module detects the edges of the input signal IN and generates two narrow pulse voltage signals, wherein the falling edge of IN generates a narrow pulse voltage signal at the IN1 end and the rising edge of IN generates a narrow pulse voltage signal at the IN2 end, which are used for driving HNM1 and HNM2 to generate a narrow pulse driving current I ds1 And I ds2 And pulse currents of the same magnitude are generated at the points N3 and N6 to drive the output unit.
The voltage level shifter of fig. 5 is a bilateral symmetry circuit, and the operation principle of the voltage level shifter at the time of a positive transient voltage change will be described by taking the left half side shown in fig. 6 as an example:
when V is SW When the transient voltage of (1) is changed from low to high, the negative transient voltage detection circuit consisting of HNM5, NM11, NM12 and NM13 does not work, and MN12 and NM13 are cut off. Current I flowing through HNM1 1 ＝I ds1 +I C1 Wherein I ds1 Channel current of HNM1, I C1 Is the current flowing through the parasitic capacitance C1. I 1 By mirroring the PM7 and PM8 current mirror, the current flowing through PM8 is I 1 . At the same time, flows through the capacitorC3 positive transient current I C3 By copying the current mirrors PM5, PM6 and NM7, NM8, the same current I is caused C3 Flows from the drain to the source of NM 8. C1 and C3 have the same value, I C1 ＝I C3 . Finally, the current used for triggering the output unit is I 1 -I C3 ＝I ds1 。
The voltage level shifter of fig. 5 is a bilateral symmetry circuit, and the left half side shown in fig. 7 is taken as an example to explain the operating principle of the voltage level shifter when the negative transient voltage changes:
when V is SW When the transient voltage of (a) is changed from high to low, a parasitic current I flows through a parasitic capacitor C5 C5 Mirror NM12 and NM13 through NM 11. Parasitic current flowing through C3 is-I C3 C5 and C3 have the same value, I C5 ＝I C3 The current flowing through PM5 is I C5 -I C3 =0, and the pm6, NM7, NM8 currents are all 0. C1 and C5 have the same value, I C1 ＝I C5 . Output cell trigger current I flowing through PM8 1 ＝I ds1 +I C5 -I C1 ＝I ds1 。
By the above analysis, no matter V SW The trigger current of the output unit of the voltage level shifter of this embodiment is the channel current of the transistor in the input unit, regardless of the current flowing through the parasitic capacitance of the drain and source terminals.
The circuit configuration of the output unit in this embodiment is shown in FIG. 8, and the input current I ds1 And I ds2 And will not be input at the same time. NM1-NM6 are N-type transistors with the same size, and PM1-PM4 are P-type transistors with the same size. When the current I is input ds1 When NM1 is generated and flows in, NM2, NM3, PM1, PM2 generate mirror currents of the same magnitude. NM3 pulls S low while PM2 pulls R high. The latch formed by inverters Inv1 and Inv2 will latch the state of S low, R high and output OUT low. The inverter Inv3 serves to increase the driving capability of the output OUT, the size of the inverter Inv4 is the same as that of Inv3, and the purpose of the inverter Inv4 is to ensure the symmetrical structure of the output cell, and the load seen at both S and R by the latch consisting of Inv1 and Inv2 is the same. When I ds2 When NM4 is generated and flows in, the samePrinciple S of (a) will be pulled high, R will be pulled low, and the state will be latched, with output OUT high.
According to another embodiment of the present invention, there is provided a half-bridge conversion circuit including: the level shift circuit and the half-bridge driving unit described above.
Specifically, fig. 9 shows a half-bridge conversion circuit of the present embodiment, where the half-bridge driving unit includes a lower power tube Q1, an upper power tube Q2, a level shift circuit 101, a driving stage 102 and a low-side driver 200, and the lower power tube Q1 and the upper power tube Q2 are N-type power tubes, V SW Is the voltage of the floating ground SW of the high-side driver. The upper power transistor Q2 is driven by a high-side driver 100 composed of a level shift circuit 101 and a driving stage 102, and its turn-on and turn-off are controlled by an input signal IN2 of the voltage level shifter. IN which the logic level of the input signal IN2 is relative to the ground level V of the low-side driver SS The logic level of the output signal Out of the level shifter is relative to the floating ground V of the high-side gate driver SW . After the lower power tube Q1 is turned off, IN2 is formed by V SS Rising to V DD Out is defined by V SW Rising to V BST Upper power tube Q2 is conducted and floats to ground V SW Will be from ground level V SS Rising to input voltage V of half-bridge converter IN . At V SW During the fast rise period, the voltage level shifter output OUT is guaranteed to remain at a high level V BST The upper power tube Q2 is ensured to be conducted, so that the half-bridge converter circuit works normally.
V SW The rapid rise of the voltage will generate a high-speed transient common mode current interference signal, similarly, when the upper power tube Q2 is closed and the lower power tube Q1 is conducted, V SW The rapid drop in voltage also produces a high-speed transient common mode current that interferes with the normal operation of the voltage level shifter. The level shift circuit in the embodiment of the invention can achieve the purpose of eliminating parasitic current generated by the change of the positive transient voltage and the negative transient voltage of the floating ground, thereby ensuring that the driving current triggered by the input signal can be conducted to the output circuit, realizing the normal operation of the level voltage shifter, and further solving the problem that the transient voltage of the voltage level shifter generates the normal operation of the level shifterInterference technical problems.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed technology content may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, for example, may be a logic function division, and may be implemented in another manner, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (15)
1. A level shift circuit, comprising:
an input unit for providing a logic drive current signal having a first change state in which a common mode voltage changes from a low level to a high level and a second change state in which the high level changes to the low level;
a first current generating unit, configured to generate a positive transient common mode current, where a common mode voltage corresponding to the positive transient common mode current has the first change state;
a second current generation unit electrically connected to the first current generation unit, for generating a negative transient common mode current, the common mode voltage corresponding to the negative transient common mode current having the second variation state;
the interference filtering unit is respectively and electrically connected with the input unit, the first current generating unit and the second current generating unit and is used for counteracting parasitic current generated by common-mode voltage change of the logic driving current signal according to the positive transient common-mode current and the negative transient common-mode current;
and the output unit is electrically connected with the interference filtering unit and is used for converting the logic driving current signal into a floating control signal.
2. The level shift circuit according to claim 1, wherein the input unit includes:
a pulse generator for generating a pulse voltage signal;
and the first switch module is electrically connected with the output end of the pulse generator and the ground level and is used for generating the logic driving current signal according to the pulse voltage signal.
3. The level shifting circuit of claim 2, wherein the first switching module comprises a first transistor and a first capacitor, wherein:
the grid electrode of the first transistor is electrically connected with the output end of the pulse generator, the drain end of the first transistor is electrically connected with the first end of the first capacitor, and the source end of the first transistor and the second end of the first capacitor are electrically connected with the ground level.
4. The level shift circuit according to claim 3, wherein the first current generating unit includes:
the second switch module is electrically connected with the ground level and is used for generating the positive transient common mode current;
and the first current mirror module is respectively and electrically connected with the second switch module and the interference filtering unit and is used for copying the positive transient common mode current into output current.
5. The level shifting circuit of claim 4, wherein the second switching module comprises a second transistor and a second capacitor, wherein:
the second transistor is of the same type and size as the first transistor;
the drain terminal of the second transistor is electrically connected with the first output terminal of the first current mirror module and the first terminal of the second capacitor respectively, the source terminal of the second transistor, the grid electrode of the second transistor and the second terminal of the second capacitor are electrically connected with the ground level, and the second output terminal of the first current mirror module is used for providing the output current.
6. The level shift circuit of claim 5, wherein the first current mirror module comprises a first PMOS transistor and a second PMOS transistor, wherein:
the first PMOS tube is interconnected with the source end of the second PMOS tube, the first PMOS tube and the drain end of the first PMOS tube jointly form a first output end of the first current mirror module after being interconnected with the grid electrode of the second PMOS tube, and the drain end of the second PMOS tube is used as a second output end of the first current mirror module.
7. The level shift circuit according to claim 3, wherein the second current generating unit includes:
a third switching module electrically connected to ground level for generating the negative transient common mode current;
and the second current mirror module is respectively and electrically connected with the third switch module, the first current generation unit and the interference filtering unit and is used for copying the negative transient common mode current into input current.
8. The level shifting circuit of claim 7, wherein the third switching module comprises a third transistor and a third capacitor, wherein:
the third transistor is of the same type and size as the first transistor;
the drain terminal of the third transistor is electrically connected to the first input terminal of the second current mirror module and the first terminal of the third capacitor, the source terminal of the third transistor, the gate of the third transistor and the second terminal of the third capacitor are all electrically connected to the ground level, and the second input terminal of the second current mirror module is used for providing the input current.
9. The level shifting circuit of claim 8, wherein the second current mirror module comprises a first NMOS transistor and a second NMOS transistor, wherein:
the first NMOS tube is interconnected with the source end of the second NMOS tube, the first NMOS tube and the grid electrode of the second NMOS tube are interconnected and then form a first input end of the second current mirror module together with the drain end of the first NMOS tube, and the drain end of the second NMOS tube is used as a second input end of the second current mirror module and is electrically connected with the first current generating unit.
10. The level shift circuit of claim 9, wherein the second current mirror module further comprises a third NMOS transistor, wherein gates of the third NMOS transistor, the first NMOS transistor, and the second NMOS transistor are interconnected, wherein source terminals of the third NMOS transistor, the first NMOS transistor, and the second NMOS transistor are interconnected, and wherein a drain terminal of the third NMOS transistor is electrically connected to the interference filtering unit.
11. The level shift circuit according to any one of claims 2 to 10, wherein the interference filtering unit includes:
the third current mirror module is respectively and electrically connected with the first current generation unit and the output unit;
and the fourth current mirror module is respectively and electrically connected with the input unit, the second current generation unit and the output unit.
12. The level shifting circuit of claim 11, wherein the third current mirror module comprises a fourth NMOS transistor and a fifth NMOS transistor, wherein:
the fourth NMOS tube is interconnected with the source end of the fifth NMOS tube, the grid electrode of the fourth NMOS tube is interconnected with the grid electrode of the fifth NMOS tube and then is electrically connected with the drain end of the fourth NMOS tube to form the first current generation unit, and the drain end of the fifth NMOS tube is electrically connected with the output unit.
13. The level shift circuit of claim 11, wherein the fourth current mirror module comprises a third PMOS transistor and a fourth PMOS transistor, wherein:
the third PMOS tube is interconnected with the source end of the fourth PMOS tube, the drain end of the fourth PMOS tube is electrically connected with the output unit after the grid electrodes of the third PMOS tube and the fourth PMOS tube are interconnected, and the drain end of the fourth PMOS tube is electrically connected with the input unit and the second current generation unit.
14. The level shift circuit of claim 13, wherein the input unit includes two of the first switch modules electrically connected to the pulse generator, the level shift circuit comprising:
two of the first current generating units;
two of the second current generating units;
and the fourth current mirror module is electrically connected with the output unit through the drain end of the fourth PMOS tube.
15. A half-bridge conversion circuit comprising the level shift circuit of any one of claims 1 to 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310117163.7A CN116248109A (en) | 2023-01-30 | 2023-01-30 | Level shift circuit and half-bridge conversion circuit with same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310117163.7A CN116248109A (en) | 2023-01-30 | 2023-01-30 | Level shift circuit and half-bridge conversion circuit with same |
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| CN116248109A true CN116248109A (en) | 2023-06-09 |
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| CN202310117163.7A Withdrawn CN116248109A (en) | 2023-01-30 | 2023-01-30 | Level shift circuit and half-bridge conversion circuit with same |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113014246A (en) * | 2021-02-20 | 2021-06-22 | 广东省科学院半导体研究所 | Voltage level shifter and electronic device |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113014246A (en) * | 2021-02-20 | 2021-06-22 | 广东省科学院半导体研究所 | Voltage level shifter and electronic device |
Non-Patent Citations (1)
| Title |
|---|
| D. LIU, S. J. HOLLIS , B. H. STARK,: "A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS》, pages 1284 * |
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