CN116247933B - Power supply device and working mode configuration circuit for power supply chip - Google Patents

Power supply device and working mode configuration circuit for power supply chip Download PDF

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Publication number
CN116247933B
CN116247933B CN202310505858.2A CN202310505858A CN116247933B CN 116247933 B CN116247933 B CN 116247933B CN 202310505858 A CN202310505858 A CN 202310505858A CN 116247933 B CN116247933 B CN 116247933B
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signal
trigger signal
configuration
pull
bias current
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CN116247933A (en
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李征
赵泊然
朱伟东
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JIANGSU YINGNENG MICROELECTRONICS CO Ltd
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JIANGSU YINGNENG MICROELECTRONICS CO Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a power supply device and a working mode configuration circuit for a power supply chip, wherein the configuration circuit comprises: the time sequence signal generation unit is used for sequentially outputting a first trigger signal, a second trigger signal and a third trigger signal based on a preset time sequence; the bias current source unit is provided with a controllable switch and is used for receiving a second trigger signal and triggering the controllable switch based on the second trigger signal to adjust bias current applied to the pad body; a connection state detection unit for outputting a state signal according to the connection point voltage and the bias current of the pad body; the configuration output unit is used for receiving the first trigger signal at the first moment, outputting the first configuration signal based on the state signal corresponding to the first moment, receiving the third trigger signal at the second moment and outputting the second configuration signal based on the state signal corresponding to the second moment. The invention detects the connection mode of the single bonding pad body through the digital circuit, and has high circuit reliability and low cost.

Description

Power supply device and working mode configuration circuit for power supply chip
Technical Field
The present invention relates to the field of power electronics, and in particular, to a power supply device and a working mode configuration circuit for a power supply chip.
Background
In order for a power chip to meet the requirements of various application environments, the operation mode of the chip is often required to be configured. Taking a direct current-direct current (DC/DC) converter chip as an example, the light load state operation modes include: forced freewheel mode (Continuous Conduction Mode, CCM) or discontinuous mode (Discontinuous Conduction Mode, DCM). Wherein, in CCM mode, the inductance current is continuous and the current will not return to zero in one switching period; in DCM, the inductor current always returns to zero during one switching cycle.
In CCM mode, output ripple voltage and frequency are constant in the whole load variation range, noise is easy to filter, and the method is suitable for application scenes requiring low interference noise, for example, application scenes of communication equipment. However, when a synchronous BUCK dc-dc converter (BUCK) chip adopts CCM mode in light load, a phenomenon of backward flowing of inductor current occurs, resulting in low conversion efficiency, and in low power consumption application equipment, for example: the mobile device must use DCM to reduce unnecessary loss of DC/DC and increase standby time. When the DCM mode is selected, the working frequency in light load is lower than that in CCM mode. The operating frequency in CCM mode is typically between a few hundred KHz to a few MHz. In DCM, the lighter the load, the lower the frequency. When the load is sufficiently light, the frequency may be below 20KHz, entering the audible frequency range that can be heard by the human ear. In audio applications, such operation may cause interference, such as a speaker or earphone, and for such applications, it is necessary to limit the lowest operating frequency in DCM. It follows that the DC/DC converter needs to be configured into three modes, i.e., CCM, DCM with lowest frequency limitation, and DCM without lowest frequency limitation, respectively, according to the application environment.
The DC/DC converter chip is configured in different modes, generally using the following method: firstly, the configuration of different modes is realized by adopting a mode of rewriting the content of a memory, and the memory can be a charged erasable programmable read-only memory (Electrically Erasable Programmable Read Only Memory, EEPROM) or a one-time programmable memory (One Time Programmable, OTP), and the method needs special semiconductor process support and special communication circuits during reading and writing; second, the configuration of different modes is implemented by changing the blowing state of the Fuse (Fuse), which requires a Chip-on-wafer test (Chip Probing). The above configuration method increases the use cost of the chip. Thus, the most common methods are: a Bonding Pad is additionally reserved on the wafer (Die). When packaging, the connection mode of the bonding pad is changed, the internal circuit detects the difference of the connection modes and outputs signals corresponding to the connection modes, so that the configuration of different modes is realized.
Fig. 1 is a schematic circuit diagram of a conventional mode configuration circuit for a power chip.
As shown in FIG. 1, the mode configuration circuit includes a voltage dividing resistor R TOP 、R BOT 、R 1 、R 2 And R is 3 First comparator COMP 1 And a second comparator COMP 2 . Wherein the first comparator COMP 1 Is V H A second comparator COMP 2 Is V L The voltage of the PAD PAD is V PAD ' the resistance value of each voltage dividing resistor is reasonably configured to meet the following working principle：
When the PAD PAD is suspended, the voltage of the PAD PAD is V PAD ' less than the first comparator COMP 1 Reference voltage V of (2) H And the voltage of the PAD PAD is V PAD ' greater than the second comparator COMP 2 Reference voltage V of (2) L First comparator COMP 1 A second comparator COMP for outputting a low level signal 2 Outputting a high level signal;
when the PAD PAD is connected to the power supply VDD, the voltage of the PAD PAD is V PAD ' greater than the first comparator COMP 1 Reference voltage V of (2) H And the voltage of the PAD PAD is V PAD ' greater than the second comparator COMP 2 Reference voltage V of (2) L First comparator COMP 1 And a second comparator COMP 2 All output high level signals;
when the PAD PAD is grounded to GND, the voltage of the PAD PAD is V PAD ' less than the first comparator COMP 1 Reference voltage V of (2) H And the voltage of the PAD PAD is V PAD ' less than the second comparator COMP 2 Reference voltage V of (2) L First comparator COMP 1 And a second comparator COMP 2 A low level signal is output.
The subsequent circuit is based on the first comparator COMP 1 And a second comparator COMP 2 And outputting the logic state of the signal, making a judgment, and carrying out corresponding configuration on the related circuit.
The prior art has the following problems: firstly, the configuration circuit sets two strings of voltage dividing resistors, consumes additional current, and influences the static power consumption of the chip in light load. If the power consumption is to be reduced, the resistance value needs to be increased. However, this results in an increase in wafer area. Second, the difference between the two comparator reference voltages in the configuration circuit is small, and the difference becomes smaller as the power supply VDD becomes lower. Meanwhile, mismatch of the voltage dividing resistors can lead to deviation of the input voltage of the comparator from a design value, so that fault tolerance performance of the circuit is poor, and the fault tolerance problem is particularly prominent in low-voltage application.
Disclosure of Invention
The invention provides power supply equipment and a working mode configuration circuit for a power supply chip, which are used for solving the problems that the cost of an analog circuit adopted in the existing working mode configuration of the power supply chip is high, and the fault tolerance is poor due to circuit matching or offset voltage, and are beneficial to improving the reliability of the circuit.
According to an aspect of the present invention, there is provided an operation mode configuration circuit for a power chip for detecting a connection mode of a pad body, the configuration circuit including:
the time sequence signal generation unit is used for sequentially outputting a first trigger signal, a second trigger signal and a third trigger signal based on a preset time sequence;
a bias current source unit provided with a controllable switch, the bias current source unit being configured to receive the second trigger signal and trigger the controllable switch based on the second trigger signal to adjust a bias current applied to the pad body;
a connection state detection unit for outputting a state signal according to the connection point voltage of the pad body and the bias current;
the configuration output unit is used for receiving the first trigger signal at a first moment, outputting a first configuration signal based on a state signal corresponding to the first moment, receiving a third trigger signal at a second moment, and outputting a second configuration signal based on a state signal corresponding to the second moment;
wherein the first time occurs before the controllable switch is triggered and the second time occurs after the controllable switch is triggered.
According to another aspect of the present invention, there is provided a power supply apparatus including: a power chip and the working mode configuration circuit; the working mode configuration circuit is used for detecting the connection mode of the bonding pad body and generating a first configuration signal and a second configuration signal according to the connection mode, wherein the first configuration signal and the second configuration signal are used for configuring the working mode of the power supply chip.
According to the technical scheme, a time sequence signal generation unit, a bias current source unit, a connection state detection unit and a configuration output unit are arranged, a plurality of trigger signals are output through the time sequence signal generation unit, the bias current source unit receives second trigger signals, and a controllable switch is triggered based on the second trigger signals to adjust bias current applied to a bonding pad body; the connection state detection unit outputs a state signal according to the connection point voltage of the bonding pad body and the bias current applied to the bonding pad body, the configuration output unit receives a first trigger signal at a first moment, outputs a first configuration signal based on the state signal corresponding to the first moment, receives a third trigger signal at a second moment, outputs a second configuration signal based on the state signal corresponding to the second moment, outputs the connection state of the bonding pad body as a digital logic signal after time sequence processing, solves the problems that the cost of an analog circuit is high, and fault tolerance is poor due to circuit matching or offset voltage in the existing power chip working mode configuration, is beneficial to improving the reliability of the circuit, improving the detection accuracy and reducing the circuit cost.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of a prior art mode configuration circuit for a power chip;
fig. 2 is a schematic structural diagram of an operation mode configuration circuit for a power chip according to a first embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of an operation mode configuration circuit according to a first alternative embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a second alternative embodiment of the operating mode configuration circuit according to the first embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of an operation mode configuration circuit according to a third alternative embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a fourth alternative embodiment of an operating mode configuration circuit according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of an operational mode configuration circuit according to a fifth alternative embodiment of the present invention;
fig. 8 is a schematic circuit diagram of an operation mode configuration circuit according to a sixth alternative embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 2 is a schematic structural diagram of a circuit for configuring an operation mode of a power chip according to a first embodiment of the present invention, where the embodiment is applicable to an application scenario in which the configuration of the operation mode of the power chip is implemented by detecting a connection mode of a single pad body. Typically, the modes of operation include, but are not limited to: CCM, DCM with lowest frequency limit and DCM without lowest frequency limit.
In embodiments of the invention, the power supply chip may be a switching power supply chip, typically a Buck DC/DC Converter chip (Buck Converter) or a Boost DC/DC Converter chip (Boost Converter).
In an embodiment of the present invention, a connection manner of the PAD body PAD includes: the PAD body PAD is suspended, the PAD body PAD is connected to the power supply VDD or the PAD body PAD is connected to the ground.
As shown in fig. 2, the operation mode configuration circuit includes:
a timing signal generation unit 100 for sequentially outputting the first trigger signals P based on a preset timing 1 Second trigger signal P 2 And a third trigger signal P 3 . Wherein the first trigger signal P 1 Second trigger signal P 2 And a third trigger signal P 3 May be a single pulse signal. At the first trigger signal P 1 After the occurrence, after a specific delay time, a second trigger signal P is sent out 2 The method comprises the steps of carrying out a first treatment on the surface of the At the second trigger signal P 2 After the occurrence, after a specific delay time, a third trigger signal P is sent out 3 . The embodiment of the invention does not limit the specific value of the delay time.
The bias current source unit 200 is provided with a controllable switch S, the controllable switch S is electrically connected with the PAD body PAD, and the bias current source unit 200 is used for receiving a second trigger signal P 2 And based on the second trigger signal P 2 The controllable switch S is triggered to adjust the bias current applied to the PAD body PAD. The bias current comprises a pull-up bias current and a pull-down bias current, and the controllable switch S can be arranged on a branch where any one of the pull-up bias current and the pull-down bias current is located based on actual requirements. When the controllable switch SWhen closed, both a pull-up bias current and a pull-down bias current are applied to the PAD body PAD; when the controllable switch S is turned off, pull-up bias current or pull-down bias current controlled by the controllable switch S cannot be applied to the PAD body PAD, so that bias current adjustment is realized.
The connection state detection unit 300 is electrically connected with the PAD body PAD and is used for outputting a state signal according to the voltage and the bias current of the connection point of the PAD body PAD. Wherein, the voltage of the connection point of the PAD body PAD is affected by the connection mode of the PAD body PAD, for example, when the PAD body PAD is grounded, the voltage of the connection point is equal to zero; when the PAD body PAD is connected with the power supply VDD, the voltage of the connection point of the PAD body PAD is equal to the power supply voltage; when the PAD body PAD is suspended, the voltage of the connection point is empty.
A configuration output unit 400 for at a first time t 1 Receiving a first trigger signal P 1 And based on the first time t 1 The corresponding status signal outputs a first configuration signal V O1 And, at a second time t 2 Receiving the third trigger signal P 3 And based on the second time t 2 The corresponding status signal outputs a second configuration signal V O2 . Wherein at a first time t 1 Occurs before the controllable switch S is triggered at a second time t 2 Which occurs after the controllable switch S is triggered.
In an embodiment of the invention, the first configuration signal V O1 And a second configuration signal V O2 Can be digital signals, and the first configuration signal V O1 And a second configuration signal V O2 The logic output difference and the subsequent logic judgment under different connection states of the PAD body PAD are matched and designed, so that the subsequent circuit can identify the connection mode of the current PAD body PAD, and the configuration of the corresponding working mode is realized.
Specifically, at the initial time of executing the chip mode configuration, the controllable switch S is turned off, and the connection point voltage is pulled to the power supply VDD or the ground GND, affected by the connection mode of the PAD body PAD and the pull-up bias current or the pull-down bias current. In order to identify the connection mode, the timing signal generation unit 100 sequentially sends out the first trigger signals P according to a preset timing 1 Second trigger signal P 2 And a third trigger signal P 3 For example, at a first time t 1 A first trigger signal P is sent to the configuration output unit 400 1 The configuration output unit 400 is caused to sample the connection state detection unit 300 at the first time t 1 A first status signal is outputted and a first configuration signal V is outputted based on the first status signal O1 . After a certain delay time, the timing signal generating unit 100 sends out a second trigger signal P to the controllable switch S 2 The controllable switch S is closed and the connection state detection unit 300 outputs a second state signal based on the current pad connection mode, the pull-up bias current, and the pull-down bias current. At a second time t 2 The timing signal generation unit 100 sends out a third trigger signal P to the configuration output unit 400 3 The configuration output unit 400 is caused to sample the connection state detection unit 300 at the first time t 2 A second status signal is outputted and a second configuration signal V is outputted based on the second status signal O2 . The digital circuit detects the connection mode of the single bonding pad body, and outputs the connection state of the bonding pad body as a digital logic signal, so that the problems that the cost of adopting an analog circuit for the existing power chip working mode configuration is high, and the fault tolerance is poor due to circuit matching or offset voltage are solved, the circuit reliability is improved, the detection accuracy is improved, and the circuit cost is reduced.
Optionally, fig. 3 is a schematic circuit diagram of an operation mode configuration circuit of a first alternative embodiment provided in the first embodiment of the present invention, which is suitable for an application scenario in which a current value of a pull-up bias current of a PAD body PAD is greater than a current value of a pull-down bias current.
As shown in fig. 3, the bias current source unit 200 includes: pull-up current source I SRC First controllable switch S 1 And pull-down current source I SNK . First controllable switch S 1 Is arranged on the pull-up current source I SRC A first controllable switch S between the PAD body PAD and the PAD body PAD 1 For receiving the second trigger signal P 2 And according to the second trigger signal P 2 On or off; pull-up current source I SRC For switching on a first controllable switch S 1 After the trigger is activated,applying a first pull-up bias current to the PAD body PAD; pull-down current source I SNK Applying a first pull-down bias current to the PAD body PAD; the current value of the first pull-up bias current is larger than that of the first pull-down bias current.
Specifically, with reference to fig. 3, the following description is made on the detection principle based on different connection modes of the PAD body PAD:
first, PAD body PAD is unsettled:
a) Initial time: first controllable switch S 1 Switch off, pull-down current source I SNK PAD voltage V of PAD body PAD PAD Pulled to ground GND. At this time, the first state signal output from the connection state detection unit 300 is a low level signal.
b) First time t 1 : first trigger signal P 1 The configuration output unit 400 is enabled, and the configuration output unit 400 samples the first state signal output by the connection state detection unit 300 and outputs a first configuration signal V matched with the first state signal O1 At this time, the first configuration signal V O1 Is a low level signal, i.e. V O1 =0。
c) Intermediate time t 1-2 : from the first time t 1 Reaching the intermediate time t after a specific delay 1-2 Second trigger signal P 2 Occurs, a first controllable switch S 1 Closing. The pull-up bias current and the pull-down bias current are simultaneously applied to the PAD body PAD, and the PAD voltage V is greater than the pull-down bias current due to the current value of the pull-up bias current PAD Pulled up to near the supply voltage. At this time, the second state signal output from the connection state detection unit 300 is a high level signal.
d) Second time t 2 : from the intermediate time t 1-2 Reaching the second moment t after a specific delay 2 Third trigger signal P 3 The configuration output unit 400 is enabled, the configuration output unit 400 samples the second state signal output by the connection state detection unit 300 and outputs a second configuration signal V matching the second state signal O2 At this time, the second configuration signal V O2 Is high enough toLevel signal, i.e. V O2 =1。
Second, the PAD body PAD is connected to the power supply VDD:
a) Initial time: since the PAD body PAD is connected to the power supply VDD, the first state signal outputted from the connection state detection unit 300 is a high level signal, and is not subjected to the first controllable switch S 1 Influence of the switching state.
b) First time t 1 : first trigger signal P 1 The enable configuration output unit 400 samples the first state signal output from the connection state detection unit 300 and outputs a first configuration signal V matching the first state signal O1 At this time, the first configuration signal V O1 Is a high level signal, i.e. V O1 =1。
c) Intermediate time t 1-2 : from the first time t 1 Reaching the intermediate time t after a specific delay 1-2 Second trigger signal P 2 Occurs, a first controllable switch S 1 Closing. This action does not affect the pad voltage V PAD The second state signal output from the connection state detection unit 300 maintains a high level.
d) Second time t 2 : from the intermediate time t 1-2 Reaching the second moment t after a specific delay 2 Third trigger signal P 3 The enabling configuration output unit 400 samples the second state signal output from the connection state detection unit 300 and outputs a second configuration signal V matching the second state signal O2 At this time, the second configuration signal V O2 Is a high level signal, i.e. V O2 =1。
Third, the PAD body PAD is grounded GND:
a) Initial time: since the PAD body PAD is grounded GND, the first state signal output by the connection state detection unit 300 is a low level signal, and is not affected by the first controllable switch S 1 Influence of the switching state.
b) First time t 1 : first trigger signal P 1 The enable configuration output unit 400 samples the first state signal output from the connection state detection unit 300 and outputs the first state signalMatched first configuration signal V O1 At this time, the first configuration signal V O1 Is a low level signal, i.e. V O1 =0。
c) Intermediate time t 1-2 : from the first time t 1 Reaching the intermediate time t after a specific delay 1-2 Second trigger signal P 2 Occurs, a first controllable switch S 1 Closing. This action does not affect the pad voltage V PAD The second state signal output from the connection state detection unit 300 maintains a low level;
d) Second time t 2 : from the intermediate time t 1-2 Reaching the second moment t after a specific delay 2 Third trigger signal P 3 The configuration output unit 400 is enabled, the configuration output unit 400 samples the second state signal output by the connection state detection unit 300 and outputs a second configuration signal V matching the second state signal O2 At this time, the second configuration signal V O2 Is a low level signal, i.e. V O2 =0。
In connection with fig. 3 and the above analysis, three time points (first time t 1 Intermediate time t 1-2 And a second time t 2 ) And outputting the connection state detection result of the PAD in a digital logic form, so that a subsequent circuit can be distinguished and correspondingly configured.
Optionally, fig. 4 is a schematic circuit diagram of an operation mode configuration circuit of a second alternative embodiment provided in the first embodiment of the present invention, which is suitable for an application scenario in which a current value of a pull-up bias current of a PAD body PAD is smaller than a current value of a pull-down bias current.
As shown in fig. 4, the bias current source unit 200 includes: pull-up current source I SRC Second controllable switch S 2 And pull-down current source I SNK The method comprises the steps of carrying out a first treatment on the surface of the Second controllable switch S 2 Is arranged at the pull-down current source I SNK A second controllable switch S between the PAD body PAD and the PAD body PAD 2 For receiving the second trigger signal P 2 And according to the second trigger signal P 2 On or off; pull-up current source I SRC The second pull-up bias current is applied to the PAD body PAD; pull-down current source I SNK For switching on and off the second controllable switch S 2 After being triggered, applying a second pull-down bias current to the PAD body PAD; wherein the current value of the second pull-up bias current is smaller than the current value of the second pull-down bias current.
Specifically, with reference to fig. 4, the following description is made on the detection principle based on different connection modes of the PAD body PAD:
first, PAD body PAD is unsettled:
a) Initial time: second controllable switch S 2 Switch off, pull-up current source I SRC PAD voltage V of PAD body PAD PAD Pulled to VDD. At this time, the first state signal output from the connection state detection unit 300 is a high level signal.
b) First time t 1 : first trigger signal P 1 The enable configuration output unit 400 samples the first state signal output from the connection state detection unit 300 and outputs a first configuration signal V O1 At this time, the first configuration signal V O1 Is a high level signal, i.e. V O1 =1。
c) Intermediate time t 1-2 : from the first time t 1 Reaching the intermediate time t after a specific delay 1-2 Second trigger signal P 2 Occurs, the second controllable switch S 2 Closing. The pull-up bias current and the pull-down bias current are simultaneously applied to the PAD body PAD, and the PAD voltage V is smaller than the pull-down bias current due to the current value of the pull-up bias current PAD Pulled low to near ground GND. At this time, the second state signal output from the connection state detection unit 300 is a low level signal.
d) Second time t 2 : from the intermediate time t 1-2 Reaching the second moment t after a specific delay 2 Third trigger signal P 3 The enable configuration output unit 400 samples the second state signal output from the connection state detection unit 300 and outputs a second configuration signal V O2 At this time, the second configuration signal V O2 Is a low level signal, i.e. V O2 =0。
Second, the PAD body PAD is connected to the power supply VDD:
a) Initial time: since the PAD body PAD is connected to the power supply VDD, the first state signal outputted from the connection state detection unit 300 is a high level signal, and is not subjected to the second controllable switch S at this time 2 Influence of the switching state.
b) First time t 1 : first trigger signal P 1 The enable configuration output unit 400 samples the first state signal output from the connection state detection unit 300 and outputs a first configuration signal V O1 At this time, the first configuration signal V O1 Is a high level signal, i.e. V O1 =1。
c) Intermediate time t 1-2 : from the first time t 1 Reaching the intermediate time t after a specific delay 1-2 Second trigger signal P 2 Occurs, the second controllable switch S 2 Closing. This action does not affect the pad voltage V PAD The second state signal outputted from the connection state detection unit 300 is maintained at the first time t 1 The same is the high level;
d) Second time t 2 : from the intermediate time t 1-2 Reaching the second moment t after a specific delay 2 Third trigger signal P 3 The enable configuration output unit 400 samples the second state signal output from the connection state detection unit 300 and outputs a second configuration signal V O2 At this time, the second configuration signal V O2 Is a high level signal, i.e. V O2 =1。
Third, the PAD body PAD is grounded GND:
a) Initial time: since the PAD body PAD is grounded GND, the first state signal output by the connection state detection unit 300 is a low level signal, and is not affected by the second controllable switch S 2 Influence of the switching state.
b) First time t 1 : first trigger signal P 1 The enable configuration output unit 400 samples the first state signal output from the connection state detection unit 300 and outputs a first configuration signal V matching the first state signal O1 At this time, the first configuration signal V O1 Is a low level signal, i.e. V O1 =0。
c) In (a)Time t 1-2 : from the first time t 1 Reaching the intermediate time t after a specific delay 1-2 Second trigger signal P 2 Occurs, the second controllable switch S 2 Closing. This action does not affect the pad voltage V PAD The second state signal output from the connection state detection unit 300 maintains a low level.
d) Second time t 2 : from the intermediate time t 1-2 Reaching the second moment t after a specific delay 2 Third trigger signal P 3 The configuration output unit 400 is enabled, the configuration output unit 400 samples the second state signal output by the connection state detection unit 300 and outputs a second configuration signal V matching the second state signal O2 At this time, the second configuration signal V O2 Is a low level signal, i.e. V O2 =0。
With reference to fig. 3 and fig. 4 and the corresponding working principles, the circuit structures of the two bias current source units 200 can output the connection state detection result of the PAD body PAD in the form of digital logic. Based on the difference of logic outputs in different circuit structures, the subsequent logic judgment is correspondingly adjusted, so that the identification of the connection state of the PAD body PAD can be realized, and the working mode is correspondingly configured based on the corresponding connection state.
Alternatively, as shown in connection with fig. 3 and 4, the pull-up current source and the pull-down current source may be mirror constant current sources.
Specifically, the pull-up bias current and the pull-down bias current required by the present invention can be applied through a current mirror, and the current value is typically several hundred nanoamperes to several microamperes, which is negligible with respect to the quiescent current of several hundred microamperes in the power supply chip. The structure of the current mirror has small influence on the chip area, and is beneficial to saving the space cost.
Optionally, fig. 5 is a schematic circuit diagram of an operation mode configuration circuit according to a third alternative embodiment provided in the first embodiment of the present invention; fig. 6 is a schematic circuit diagram of an operation mode configuration circuit according to a fourth alternative embodiment of the present invention.
As shown in fig. 5 and 6, the timing signal generation unit 100 includes: pulse generatorGenerator 101, first delay unit T D1 And a second delay unit T D2 . A pulse generator 101 for generating a first trigger signal P 1 And apply the first trigger signal P 1 To the first delay unit T D1 And a configuration output unit 400; first delay unit T D1 For being based on the first trigger signal P 1 And a first preset delay time generates a second trigger signal P 2 And apply the second trigger signal P 2 To the bias current source unit 200; second delay unit T D2 For being based on the second trigger signal P 2 And a second preset delay time generates a third trigger signal P 3 And apply the third trigger signal P 3 To the configuration output unit 400.
The first preset delay time and the second preset delay time can be set according to the actual time sequence logic requirement, and specific numerical values of the first preset delay time and the second preset delay time are not limited.
Specifically, the first delay unit T D1 And a second delay unit T D2 The triggering can be performed in a pulse mode. In the first delay unit T D1 Receiving the first trigger signal P 1 After that, the delay time is started, when the delay time reaches the first preset delay time, a first delay unit T D1 For bias current source unit 200 and second delay unit T D2 Send out a second trigger signal P 2 . In the second delay unit T D2 Receiving the second trigger signal P 2 After that, the delay time is started, and when the delay time reaches the second preset delay time, a third trigger signal P is sent to the configuration output unit 400 3 By means of first trigger signals P at different moments 1 And a third trigger signal P 3 Enabling the configuration output unit 400 to sample the state signal at the corresponding time, and enabling the configuration output unit 400 to output the first configuration signal V based on the state signal O1 And a second configuration signal V O2 . The time sequence adjustment of different trigger signals is realized through the time delay circuit, and the circuit has simple structure and is easy to maintain.
As shown in fig. 5 and 6, the configuration output unit 400 includes: first logic memory circuit D 1 For receiving the first trigger signal P 1 And at the first trigger signal P 1 Under the triggering of (a), collecting and storing a first time t 1 Corresponding first status signal M 1 The method comprises the steps of carrying out a first treatment on the surface of the Second logic memory circuit D 2 For receiving the third trigger signal P 3 And at the third trigger signal P 3 Under the triggering of (a), acquiring and storing a second time t 2 Corresponding second status signal M 2 。
Optionally, a first logic storage circuit D 1 And a second logic storage circuit D 2 May be a trigger. The trigger is a storage circuit based on pulse edge triggering. Typically, a flip-flop may be used to store a one-bit binary number.
Specifically, the flip-flop is provided with a data input port D for receiving the first status signal M, an enable port and an output port Q 1 Or a second status signal M 2 The enable port is used for receiving the first trigger signal P 1 Or a third trigger signal P 3 An output port Q for outputting a first configuration signal V O1 Or a second configuration signal V O2 。
As shown in fig. 5 and 6, the connection state detection unit 300 includes: a comparator COMP, a first input terminal (e.g. a positive input terminal) of the comparator COMP is electrically connected to the PAD body PAD, and a second input terminal (e.g. an inverting input terminal) of the comparator COMP is used for receiving the reference voltage V REF The output end of the comparator COMP is respectively connected with the first logic memory circuit D 1 And a second logic storage circuit D 2 Electrically connecting; the comparator COMP is used for determining the pad voltage according to the connection point voltage and the bias current, and the pad voltage V PAD With reference voltage V REF And comparing and outputting a state signal according to the comparison result.
In an embodiment of the present invention, the base reference voltage V REF The bandgap reference voltage (Bandgap Voltage Reference), which is common in circuits, can be used directly. Typically, the reference voltage V REF The voltage value of (2) is equal to about 1.2V.
Specifically, the connection mode of the bonding pad body and the application to the bonding pad at different momentsThe bias current of the body and the comparator COMP acquire the pad voltages V at different moments PAD For example, the pad voltage V PAD May be equipotential with the power supply VDD or ground GND. The comparator COMP applies the pad voltage V at different moments PAD With reference voltage V REF A comparison is made. Receiving a base reference voltage V at an inverting input REF For example, when the pad voltage V PAD Higher than the reference voltage V REF When the state signal output by the comparator COMP is a high level signal; when the bonding pad voltage V PAD Lower than the reference voltage V REF At this time, the state signal output from the comparator COMP is a low level signal. First logic memory circuit D 1 And a second logic storage circuit D 2 The corresponding status signals are sampled based on the trigger signals at different moments.
At a first time t 1 First trigger signal P 1 Occurs, first logic memory circuit D 1 Triggered, sample first time t 1 Corresponding first state signal V COMP1 Latch and output the first configuration signal V O1 The first configuration signal V O1 And a first state signal V COMP1 The level states of (2) are the same; at a second time t 2 Second trigger signal P 2 Occurs, the second logic memory circuit D 2 Triggered, sample the second time t 2 Corresponding second state signal V COMP2 Latch and output the second configuration signal V O2 The second configuration signal V O2 And a second state signal V COMP2 The level states of (2) are the same. Through setting up digital circuit, with the connected state conversion of pad body digital logic signal output, circuit structure is simple, and the reliability is high, is favorable to promoting and detects the rate of accuracy, reduce cost.
Optionally, fig. 7 is a schematic circuit diagram of an operating mode configuration circuit according to a fifth alternative embodiment provided in the first embodiment of the present invention; fig. 8 is a schematic circuit diagram of an operation mode configuration circuit according to a sixth alternative embodiment of the present invention.
As shown in fig. 7 and 8, the timing signal generation unit 100 includes: start-up detection circuit 110, start-up detection circuit 110 is used for performing start detection on the power chip based on a preset time sequence, and generating a first trigger signal P according to a start detection completion signal 1 Second trigger signal P 2 And a third trigger signal P 3 。
In one embodiment, the initiation detection items include, but are not limited to: starting band gap reference voltage, detecting chip temperature, detecting undervoltage protection and starting a clock.
Specifically, the timing signal generating unit 100 of the present invention is operative to provide the first trigger signals P arranged in a predetermined timing 1 Second trigger signal P 2 And a third trigger signal P 3 I.e. first send out a first trigger signal P to the configuration output unit 400 1 Then sends out a second trigger signal P to the controllable switch S of the bias current source unit 200 2 Finally, a third trigger signal P is sent to the configuration output unit 400 3 . When the power chip is started, a series of start-up tests, such as starting a band gap reference voltage, detecting a chip temperature, detecting undervoltage protection, starting a clock, etc., need to be completed in sequence. Each step is completed, a pulse signal is generated to indicate that the current step is completed, and the next step can be entered. Obviously, this series of signals can be used in turn as the first trigger signal P 1 Second trigger signal P 2 And a third trigger signal P 3 Therefore, the delay circuit is omitted completely, which is beneficial to simplifying the circuit structure and reducing the cost.
As shown in fig. 7 and 8, the connection state detection unit 300 includes: a buffer BUF having its input end electrically connected to the PAD body PAD and its output end respectively connected to the first logic memory circuit D 1 And a second logic storage circuit D 2 Electrically connecting; the buffer BUF is used for determining the pad voltage V according to the connection point voltage and the bias current PAD And based on the pad voltage V PAD Outputting a status signal; wherein the pad voltage is approximately a digital signal.
In an embodiment of the present invention, the bonding pad body is connected in such a manner that the bias current applied to the pad body at different timings is equal to the pad voltage V PAD Can be close to the power supply VDD or the ground GNDLike a digital signal. The digital buffer BUF is adopted to replace a comparator, and the bonding pad voltage V PAD Accessing a first logic memory circuit D via a digital buffer BUF 1 And a second logic storage circuit D 2 Is provided. If the bonding pad voltage V PAD Is pulled up to the same potential as the power supply VDD, the status signal outputted from the buffer BUF is a high level signal, and is stored in the first logic memory circuit D 1 Or a second logic storage circuit D 2 After being triggered, the high-level signal is sent to a corresponding data input port; if the bonding pad voltage V PAD Is pulled down to the same potential as the ground GND, the status signal outputted by the buffer BUF is a low level signal, and is stored in the first logic memory circuit D 1 Or a second logic storage circuit D 2 After being triggered, a low level signal is sent to the corresponding data input port. By simplifying the circuit of the connection state detecting unit 300, the circuit area is saved and there is no static power consumption.
In other embodiments, pad voltage V PAD The data input port of the trigger can be directly accessed, which is beneficial to simplifying the circuit structure, saving the area and reducing the cost.
Example two
Based on any of the foregoing embodiments, a second embodiment of the present invention provides a power supply apparatus, including: a power chip, and a working mode configuration circuit provided by any of the above embodiments.
The working mode configuration circuit is used for detecting the connection mode of the PAD body PAD, generating a first configuration signal and a second configuration signal according to the connection mode, and the first configuration signal and the second configuration signal are used for configuring the working mode of the power supply chip.
The power supply device of the embodiment of the invention is provided with a working mode configuration circuit, wherein the configuration circuit is provided with a time sequence signal generation unit, a bias current source unit, a connection state detection unit and a configuration output unit, a plurality of trigger signals are output through the time sequence signal generation unit, the bias current source unit receives a second trigger signal and triggers a controllable switch based on the second trigger signal, and bias current applied to a bonding pad body is adjusted; the connection state detection unit outputs a state signal according to the connection point voltage of the bonding pad body and the bias current applied to the bonding pad body, the configuration output unit receives a first trigger signal at a first moment, outputs a first configuration signal based on the state signal corresponding to the first moment, receives a third trigger signal at a second moment, outputs a second configuration signal based on the state signal corresponding to the second moment, outputs the connection state of the bonding pad body as a digital logic signal after time sequence processing, solves the problems that the cost of an analog circuit is high, and fault tolerance is poor due to circuit matching or offset voltage in the existing power chip working mode configuration, is beneficial to improving the reliability of the circuit, improving the detection accuracy and reducing the circuit cost.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (9)

1. An operation mode configuration circuit for a power chip for detecting a connection mode of a pad body, the configuration circuit comprising:
the time sequence signal generation unit is used for sequentially outputting a first trigger signal, a second trigger signal and a third trigger signal based on a preset time sequence;
a bias current source unit provided with a controllable switch, the bias current source unit being configured to receive the second trigger signal and trigger the controllable switch based on the second trigger signal to adjust a bias current applied to the pad body;
a connection state detection unit for outputting a state signal according to the connection point voltage of the pad body and the bias current;
the configuration output unit is used for receiving the first trigger signal at a first moment, outputting a first configuration signal based on a state signal corresponding to the first moment, receiving a third trigger signal at a second moment, and outputting a second configuration signal based on a state signal corresponding to the second moment;
wherein the first time occurs before the controllable switch is triggered and the second time occurs after the controllable switch is triggered;
the timing signal generation unit includes: the pulse generator, the first delay unit and the second delay unit;
the pulse generator is used for generating a first trigger signal and sending the first trigger signal to the first delay unit and the configuration output unit;
the first delay unit is used for generating the second trigger signal based on the first trigger signal and a first preset delay time and sending the second trigger signal to the bias current source unit;
the second delay unit is configured to generate the third trigger signal based on the second trigger signal and a second preset delay time, and send the third trigger signal to the configuration output unit.
2. The configuration circuit according to claim 1, wherein the bias current source unit includes: a pull-up current source, a first controllable switch and a pull-down current source;
the first controllable switch is arranged between the pull-up current source and the bonding pad body, and is used for receiving the second trigger signal and switching on or switching off according to the second trigger signal;
the pull-up current source is used for applying a first pull-up bias current to the pad body after the first controllable switch is triggered;
the pull-down current source is used for applying a first pull-down bias current to the bonding pad body;
wherein the current value of the first pull-up bias current is greater than the current value of the first pull-down bias current.
3. The configuration circuit according to claim 1, wherein the bias current source unit includes: a pull-up current source, a second controllable switch and a pull-down current source;
the second controllable switch is arranged between the pull-down current source and the bonding pad body, and is used for receiving the second trigger signal and switching on or switching off according to the second trigger signal;
the pull-up current source is used for applying a second pull-up bias current to the bonding pad body;
the pull-down current source is used for applying a second pull-down bias current to the pad body after the second controllable switch is triggered;
the current value of the second pull-up bias current is smaller than that of the second pull-down bias current.
4. A configuration circuit according to any of claims 2 or 3, wherein the pull-up current source and the pull-down current source are mirror constant current sources.
5. A configuration circuit according to any one of claims 1 to 3, wherein the timing signal generation unit includes: and the starting detection circuit is used for starting detection on the power chip based on the preset time sequence and generating the first trigger signal, the second trigger signal and the third trigger signal according to a starting detection completion signal.
6. A configuration circuit according to any one of claims 1-3, wherein the configuration output unit comprises:
the first logic storage circuit is used for receiving the first trigger signal and acquiring and storing a state signal corresponding to the first moment under the triggering of the first trigger signal;
and the second logic storage circuit is used for receiving the third trigger signal and acquiring and storing the state signal corresponding to the second moment under the triggering of the third trigger signal.
7. The configuration circuit according to claim 6, wherein the connection state detection unit includes: the first input end of the comparator is electrically connected with the bonding pad body, the second input end of the comparator is used for receiving a base reference voltage, and the output end of the comparator is electrically connected with the first logic storage circuit and the second logic storage circuit respectively;
the comparator is used for determining a pad voltage according to the connection point voltage and the bias current, comparing the pad voltage with the base reference voltage and outputting the state signal according to a comparison result.
8. The configuration circuit according to claim 6, wherein the connection state detection unit includes: the input end of the buffer is electrically connected with the bonding pad body, and the output end of the buffer is electrically connected with the first logic storage circuit and the second logic storage circuit respectively;
the buffer is used for determining a pad voltage according to the connection point voltage and the bias current and outputting the state signal based on the pad voltage;
wherein the pad voltage is approximately a digital signal.
9. A power supply apparatus, characterized by comprising: a power chip, and an operating mode configuration circuit as claimed in any one of claims 1 to 8;
the working mode configuration circuit is used for detecting the connection mode of the bonding pad body and generating a first configuration signal and a second configuration signal according to the connection mode, wherein the first configuration signal and the second configuration signal are used for configuring the working mode of the power supply chip.
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