CN112290929B - Signal transmission circuit and electronic equipment - Google Patents
Signal transmission circuit and electronic equipment Download PDFInfo
- Publication number
- CN112290929B CN112290929B CN202011124746.5A CN202011124746A CN112290929B CN 112290929 B CN112290929 B CN 112290929B CN 202011124746 A CN202011124746 A CN 202011124746A CN 112290929 B CN112290929 B CN 112290929B
- Authority
- CN
- China
- Prior art keywords
- voltage
- resistor
- signal
- capacitor
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000008054 signal transmission Effects 0.000 title claims abstract description 51
- 239000003990 capacitor Substances 0.000 claims abstract description 76
- 238000007599 discharging Methods 0.000 claims abstract description 17
- 230000008859 change Effects 0.000 claims abstract description 12
- 238000012545 processing Methods 0.000 claims description 20
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 7
- 230000007704 transition Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention provides a signal transmission circuit and electronic equipment, which are beneficial to interface simplification by newly adding a circuit function through multiplexing a power input pin. The signal transmission circuit is provided with a power supply input pin and is used for receiving a superposed signal which is obtained by superposing an input voltage and a digital signal; the signal transmission circuit comprises a reference voltage generator, a capacitor, a resistor and a hysteresis comparator; the reference voltage generator provides a reference voltage to a first end of the resistor; the first end of the capacitor is connected with the power input pin, the second end of the capacitor is connected with the second end of the resistor, and the voltage of the second end of the capacitor changes correspondingly when the level jump of the superposed signal occurs; the resistor and the capacitor form a charge-discharge circuit which is used for charging or discharging when the voltages at the two ends of the resistor are different until the voltages at the two ends of the resistor are the same; two input ends of the hysteresis comparator are respectively connected with two ends of the resistor and used for outputting a target signal according to the voltage difference change of the two ends of the resistor, and the target signal is used for representing the digital signal.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a signal transmission circuit and an electronic device.
Background
With the rise of real wireless bluetooth headset (TWS), wearable watch/bracelet, internet of things small equipment and the like, the requirements for such equipment are also higher and higher, and especially, the size of the internal chip in such equipment is more and more expected to be as small as possible. For a small-sized chip, considering that the pin pitch cannot be smaller (for example, the pin pitch of a WLP (Wafer Level Package) is usually 0.4mm at the minimum), the number of pins required to realize all functions of the chip becomes a key factor that restricts the chip area.
Therefore, it is increasingly desirable for such devices to interact with external devices by using as few pins (or pins) or contacts as possible, and if functions other than the original functions can be implemented by using pins already existing in the interface, such as signal control and data information interaction other than power supply by using power input pins, the use of the interface pins can be reduced, and the requirement for interface simplification is met.
Disclosure of Invention
The invention provides a signal transmission circuit and electronic equipment, which are beneficial to interface simplification by newly adding a circuit function through multiplexing a power input pin.
A first aspect of the present invention provides a signal transmission circuit, which has a power input pin, wherein the power input pin is used for receiving a superimposed signal, and the superimposed signal is a signal obtained by superimposing an input voltage and a digital signal; the signal transmission circuit includes at least: a reference voltage generator, a capacitor, a resistor, and a hysteresis comparator;
the output end of the reference voltage generator is connected with the first end of the resistor and used for providing reference voltage to the first end of the resistor;
the first end of the capacitor is connected with the power input pin, the second end of the capacitor is connected with the second end of the resistor, and the voltage of the second end of the capacitor changes when the level jump of a superposed signal received by the power input pin occurs, so that the voltages of the two ends of the resistor are different; the resistor and the capacitor form a charge-discharge circuit, the charge-discharge circuit is used for charging or discharging when voltages at two ends of the resistor are different until the voltages at the two ends of the resistor are the same, and the one-time charging or discharging duration of the charge-discharge circuit is shorter than the period of the digital signal;
the first input end of the hysteresis comparator is connected with the first end of the resistor, the second input end of the hysteresis comparator is connected with the second end of the resistor, the hysteresis comparator is used for outputting a target signal according to the voltage difference change of the two ends of the resistor, and the target signal is used for representing the digital signal.
According to an embodiment of the present invention, the signal transmission circuit further includes: a switch module;
the first end of the switch module is connected with the second end of the capacitor, the second end of the switch module receives a specified voltage, and the third end of the switch module is connected with the second end of the resistor;
when the first end and the second end of the switch module are conducted, the first end and the third end of the switch module are switched off, and the second end of the capacitor receives the specified voltage;
when the first end and the third end of the switch module are connected, the first end and the second end of the switch module are switched off, and the second end of the capacitor is connected with the second end of the resistor.
In accordance with one embodiment of the present invention,
the first input end is a non-inverting input end, and the second input end is an inverting input end;
when the switch module is switched from the first end to the second end to the first end and the third end, the first input end of the hysteresis comparator receives the specified voltage to realize the output initialization of the hysteresis comparator;
the superposition signal is input to the power input pin after initialization of the output of the hysteresis comparator is achieved.
In accordance with one embodiment of the present invention,
the specified voltage is greater than the reference voltage, and a difference between the specified voltage and the reference voltage is greater than a hysteresis voltage of the hysteresis comparator;
or,
the specified voltage is less than the reference voltage, and a difference between the reference voltage and the specified voltage is greater than a hysteresis voltage of the hysteresis comparator.
In accordance with one embodiment of the present invention,
the specified voltage is a voltage supported inside the device where the signal transmission circuit is located.
According to one embodiment of the invention, the switch module is a single pole double throw switch;
the first end of the switch module is the moving end of the single-pole double-throw switch, and the second end and the third end of the switch module are two fixed ends of the single-pole double-throw switch.
In accordance with one embodiment of the present invention,
the difference between the high level and the low level of the digital signal is greater than the hysteresis voltage of the hysteresis comparator.
In accordance with one embodiment of the present invention,
the target signal has the same period as the digital signal, and the target signal is in phase with or in anti-phase with the digital signal.
In accordance with one embodiment of the present invention,
the reference voltage generator provides a reference voltage independent of the input voltage, and the voltage received by the reference voltage generator for generating the reference voltage is independent of the input voltage.
A second aspect of the present invention provides an electronic device including the signal transmission circuit according to the foregoing embodiments.
The invention has the following beneficial effects:
in the embodiment of the invention, a superposed signal obtained by superposing an input voltage and a digital signal is received by a multiplexing power input pin, the input voltage in the superposed signal is isolated by using the DC blocking characteristic of a capacitor, and the level jump condition of the digital signal modulated by the input voltage is transmitted by using the non-abrupt change characteristic of the voltage difference between two ends of the capacitor, the level jump of the digital signal means the jump of the superposed signal, the voltage of the second end of the capacitor correspondingly jumps to maintain the voltage difference between two ends of the capacitor each time the jump is carried out, namely the voltage of one end of the resistor connected with the capacitor jumps, but the reference voltage of a reference voltage generator is unchanged, namely the voltage of one end of the resistor connected with the reference voltage generator is unchanged, so the voltages of two ends of the resistor become different, namely the voltage difference between two input ends of a hysteresis comparator is increased, therefore, the target signal output by the hysteresis comparator can also jump, therefore, the target signal output by the hysteresis comparator can represent a digital signal, the voltage at two ends of the resistor can be charged or discharged through a charge-discharge circuit consisting of the resistor and the capacitor to achieve the same, the one-time charge or discharge duration of the charge-discharge circuit can be far shorter than the period of the digital signal, and the transmission of the next jump of the digital signal can not be influenced, in the mode, the signal transmission function realized by the input pin of the multiplexing power supply is realized, in addition, the reference voltage input into the comparator does not need to be closely related to the input voltage and can be a fixed voltage irrelevant to the size of the input voltage, so that the design of the reference voltage generator is more flexible, the reference voltage generator can be realized by the mode of smaller power consumption and lower circuit cost, and the working voltage of the comparator does not need to be matched with the input voltage, the leakage and withstand voltage requirements for the comparator and related circuits can be reduced, thereby reducing cost.
Because the resistor is short-circuited with the non-inverting input end and the inverting input end of the hysteresis comparator, after each logic jump of the digital signal is captured by the hysteresis comparator, the voltage of the non-inverting input end and the voltage of the inverting input end of the hysteresis comparator can be quickly pulled to be consistent after the charging or discharging of the charging and discharging circuit is finished, so that the hysteresis comparator can wait for accurately capturing the next signal jump, and the logic of a target signal output by the hysteresis comparator can be kept consistent with the logic of the digital signal.
The hysteresis comparator has a certain hysteresis voltage, which can support the hysteresis comparator to realize the jump of the output logic when the digital signal generates logic jump, but does not support the logic jump of ripple (the ripple is usually small in amplitude, and the jump of the ripple is not enough to change the absolute value of the voltage difference between two input ends of the hysteresis comparator from being smaller than the hysteresis voltage to being larger than the hysteresis voltage) to realize the jump of the output logic, so that the hysteresis comparator can be used for capturing and maintaining the logic of the digital signal, and the hysteresis comparator can be used for filtering out error signals possibly caused by the ripple.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit diagram of a signal transmission circuit according to an embodiment of the invention;
FIG. 2 is a circuit diagram of a signal transmission circuit according to another embodiment of the present invention; (ii) a
Fig. 3 is a schematic waveform diagram of the superimposed signal VIN and the target signal RX _ COMM according to an embodiment of the present invention;
fig. 4 is a circuit diagram of a first processing module and a second processing module that need to communicate and a signal transmission circuit according to an embodiment of the invention.
Description of reference numerals:
a capacitor 101; a resistor 102; a reference voltage generator 103; a hysteresis comparator 104; a switch module 105; a first processing module 200; a second processing module 300; superimposing the signal VIN; the voltage VC _ IN at the second end of the capacitor 101; a specified voltage VC _ INIT; the voltage VC at the second end of the resistor 102; a voltage VCC; a reference voltage Vref; the target signal RX _ COMM.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In a related manner, in order to multiplex the power input pins, the input voltage and the digital signal are mixed to obtain a superimposed signal, the superimposed signal is input to a non-inverting input terminal of a common comparator, then an average voltage of the superimposed signal is taken as a reference voltage and input to an inverting input terminal of the comparator, and the digital signal logic superimposed on the input voltage is output through an output terminal of the comparator. In this method, although the transmission of the digital signal can be realized by multiplexing the power input pins, there are the following drawbacks:
1) the reference voltage input to the comparator must be directly closely related to the input voltage, which makes the design of the reference voltage generator inflexible and cannot be realized in a way of minimizing power consumption and circuit cost;
2) the operating voltage of the comparator must be matched with the voltage range of the input power supply providing the input voltage, so that when the input voltage is relatively high or the voltage range is relatively large, the requirements of electric leakage and voltage resistance of the comparator and related circuits are increased, and further the cost is increased.
In the embodiment of the invention, a superposed signal obtained by superposing an input voltage and a digital signal is received by a multiplexing power input pin, the input voltage in the superposed signal is isolated by using the DC blocking characteristic of a capacitor, and the level jump condition of the digital signal modulated by the input voltage is transmitted by using the non-abrupt change characteristic of the voltage difference between two ends of the capacitor, the level jump of the digital signal means that the superposed signal jumps, and the voltage of the second end of the capacitor correspondingly jumps to maintain the voltage difference between two ends of the capacitor each time the superposed signal jumps, namely the voltage of one end of the resistor connected with the capacitor jumps, but the reference voltage of a reference voltage generator is unchanged, namely the voltage of one end of the resistor connected with the reference voltage generator is unchanged, so the voltages of two ends of the resistor become different, namely the voltage difference between two input ends of a hysteresis comparator is increased, therefore, the target signal output by the hysteresis comparator can also jump, therefore, the target signal output by the hysteresis comparator can represent a digital signal, the voltage at two ends of the resistor can be charged or discharged through a charge-discharge circuit consisting of the resistor and the capacitor to achieve the same, the one-time charge or discharge duration of the charge-discharge circuit can be far shorter than the period of the digital signal, so the transmission of the next jump of the digital signal can not be influenced, in the mode, the signal transmission function is realized through the input pin of the multiplexing power supply, in addition, the reference voltage input into the comparator does not need to be closely related to the input voltage and can be a fixed voltage unrelated to the input voltage, so that the design of the reference voltage generator is more flexible, the reference voltage generator can be realized by the mode of smaller power consumption and lower circuit cost, and the working voltage of the comparator does not need to be matched with the input voltage or the voltage, the leakage and withstand voltage requirements for the comparator and related circuits can be reduced, thereby reducing cost.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a schematic circuit diagram of a signal transmission circuit according to an embodiment of the invention. The signal transmission circuit is provided with a power supply input pin, the power supply input pin originally has the function of receiving input voltage, in the embodiment of the invention, the function of the power supply input pin is expanded, a superposed signal VIN superposed by the input voltage and a digital signal is received through the power supply input pin, and the signal transmission is realized on the basis.
The signal transmission circuit may be an improvement or addition on any circuit with a power input pin, for example, a circuit with an IIC interface may be added, but is not limited thereto as long as the signal transmission circuit has a power input pin.
The superimposed signal VIN received by the power input pin is a signal obtained by superimposing the input voltage and the digital signal. The input voltage is a direct current voltage, for example, a voltage of 5V; the digital signal may be a control command or data information, and may be composed of a high level and a low level, where the high level and the low level are logic levels, and the specific size is not limited.
Referring to fig. 1, the signal transmission circuit includes at least: a capacitor 101, a resistor 102, a reference voltage Vref generator 103, and a hysteresis comparator 104. An output terminal of the reference voltage Vref generator 103 is connected to a first terminal of the resistor 102, a first terminal of the capacitor 101 is connected to the power input pin, a second terminal of the capacitor 101 is connected to a second terminal of the resistor 102, a first input terminal of the hysteresis comparator 104 is connected to the first terminal of the resistor 102, and a second input terminal of the hysteresis comparator 104 is connected to the second terminal of the resistor 102.
The reference voltage Vref generator 103 may generate the reference voltage Vref according to the input voltage VCC, and the reference voltage Vref may be generated in various ways, for example, the reference voltage Vref may be implemented by a reference voltage buffer output, a resistor 102 and capacitor 101 filter output, a voltage-dividing resistor-dividing output, or an LDO (low dropout regulator) output, and is not limited thereto. Taking the voltage-dividing output of the voltage-dividing resistor as an example, the reference voltage Vref generator 103 may include a voltage-dividing resistor network (for example, may be formed by connecting at least two resistors in parallel), one end of the voltage-dividing resistor network receives the input voltage VCC, the other end of the voltage-dividing resistor network is grounded, and a voltage-dividing point of the voltage-dividing resistor network outputs the reference voltage Vref.
The reference voltage Vref is fixed and constant, so the voltage VC at the second end of the resistor 102 can be always kept constant, i.e., the voltage at the first input end of the hysteresis comparator 104 can be always kept constant. By using the dc blocking characteristic of the capacitor 101, the voltage at the first end of the capacitor 101 is the voltage after isolating the input voltage, and accordingly jumps along with the jump of the digital signal, and according to the characteristic that the voltage difference between the two ends of the capacitor 101 does not suddenly change, the voltage VC _ IN at the second end of the capacitor 101 also changes along with the first end, so the voltage VC at the second end of the resistor 102 can also change correspondingly, that is, the voltage at the second input end of the hysteresis comparator 104 changes.
The capacitor 101 and the resistor 102 may form a charge/discharge circuit, and when the voltages at the two ends of the resistor 102 are different, the charge/discharge circuit may perform charging or discharging until the voltages at the two ends of the resistor 102 are the same. For example, when the second terminal voltage VC of the resistor 102 (IN the case where the resistor 102 is connected to the capacitor 101, the second terminal voltage VC of the resistor 102, i.e., the second terminal voltage VC _ IN of the capacitor 101) is higher than the first terminal voltage, the capacitor 101 may be discharged through the resistor 102.
When the level of the digital signal jumps, since the superimposed signal VIN is obtained by superimposing the digital signal and the input voltage, the superimposed signal VIN also jumps accordingly, and thus the voltage at the first end of the capacitor 101 inevitably jumps accordingly, and since the voltage difference between the two ends of the capacitor 101 does not jump suddenly, the voltage VC _ IN at the second end of the capacitor 101 also changes accordingly, that is, the voltage VC at the second end of the resistor 102 also changes accordingly, so that the voltages at the two ends of the resistor 102 may become different IN this case.
Specifically, when the digital signal jumps from a low level to a high level, the voltage at the first end of the capacitor 101 increases, and correspondingly, the voltage VC _ IN at the second end of the capacitor 101 also increases, so that the voltage VC at the second end of the resistor 102 is higher than the voltage at the first end; similarly, when the digital signal jumps from a high level to a low level, the voltage at the first terminal of the capacitor 101 decreases, and correspondingly, the voltage VC _ IN at the second terminal of the capacitor 101 also decreases, so that the voltage VC at the second terminal of the resistor 102 is lower than the voltage at the first terminal.
The voltage difference across the resistor 102 is only temporary, and after the capacitor 101 is charged or discharged through the resistor 102, the voltage across the resistor 102 returns to the same value.
The one-time charging or discharging duration of the charging and discharging circuit can be much shorter than the period of the digital signal, so that the charging and discharging circuit can complete charging or discharging firstly after the digital signal generates one-time level jump, and when the charging or discharging is completed, the voltage of the two input ends of the hysteresis comparator 104 is the same, so that the level output by the hysteresis comparator 104 can be maintained; the next level jump of the digital signal is only then initiated, so that the charging or discharging does not affect the next level jump of the digital signal.
That is, since the resistor 102 short-circuits the non-inverting input terminal and the inverting input terminal of the hysteresis comparator 104, after each logic transition of the digital signal is captured by the hysteresis comparator 104, the voltage at the non-inverting input terminal and the inverting input terminal of the hysteresis comparator 104 can be quickly pulled to be consistent after the charging or discharging circuit is finished, so that the hysteresis comparator 104 can wait for accurately capturing the next signal transition, and thus the logic of the target signal RX _ COMM output by the hysteresis comparator 104 can be consistent with the logic of the digital signal.
Of course, there may be some delay.
The first input of the hysteresis comparator 104 may be a non-inverting input, and correspondingly, the second input of the hysteresis comparator 104 may be an inverting input; alternatively, the first input terminal of the hysteresis comparator 104 may be an inverting input terminal, and the second input terminal of the hysteresis comparator 104 is a communication input terminal, which is not limited in particular.
The hysteresis comparator 104 may output a target signal RX _ COMM according to a change in a voltage difference across the resistor 102, the target signal RX _ COMM being used to represent a digital signal.
Taking the first input terminal as the non-inverting input terminal and the second input terminal as the inverting input terminal as an example, when the digital signal jumps from the low level to the high level, the voltage VC at the second terminal of the resistor 102 is higher than the voltage at the first terminal, and at this time, the voltage at the inverting input terminal of the hysteresis comparator 104 is higher than the voltage at the non-inverting input terminal, so that the hysteresis comparator 104 outputs the low level, and the charge and discharge circuit discharges until the voltages at the two terminals of the resistor 102 are the same, and at this time, the voltages at the two input terminals of the hysteresis comparator 104 are also the same, so that the hysteresis comparator 104 maintains outputting the low level; when the digital signal jumps from high level to low level, the voltage VC at the second end of the resistor 102 is lower than the voltage VC at the first end, and the voltage at the inverting input of the hysteresis comparator 104 is lower than the voltage at the non-inverting input, so the hysteresis comparator 104 outputs high level, and the charging and discharging circuit charges until the voltages at the two ends of the resistor 102 are the same, and the voltages at the two inputs of the hysteresis comparator 104 are also the same, so the hysteresis comparator 104 keeps outputting high level, and the high and low levels output by the hysteresis comparator 104 constitute the target signal RX _ COMM. In this example, the target signal RX _ COMM has the same period as the digital signal, and the target signal RX _ COMM is opposite in phase to the digital signal.
In the embodiment of the present invention, the target signal RX _ COMM is inverted from the digital signal, which means that the level of the digital signal is opposite to that of the target signal RX _ COMM, for example, the level of the digital signal is high-low-high, and the level of the target signal RX _ COMM is low-high-low. The target signal RX _ COMM is in phase with the digital signal, which means that the digital signal and the target signal RX _ COMM have the same level, for example, the level of the digital signal is high-low-high, and the level of the target signal RX _ COMM is also high-low-high.
The difference between the high level and the low level of the digital signal is greater than the hysteresis voltage of the hysteresis comparator 104. The specific magnitude of the hysteresis voltage is not limited, and may be determined according to the requirement, for example, may be 50mV, although this is only an example.
Because the hysteresis comparator 104 has a certain hysteresis voltage, which can support the hysteresis comparator 104 to implement the transition of the output logic when the digital signal makes a logic transition, but does not support the logic transition of the ripple (the ripple is usually small in amplitude, and the transition of the ripple is not enough to change the absolute value of the voltage difference between the two input terminals of the hysteresis comparator 104 from being smaller than the hysteresis voltage to being larger than the hysteresis voltage) to implement the transition of the output logic, the hysteresis comparator 104 can be used to capture and maintain the logic of the digital signal, and the hysteresis comparator 104 can be used to filter out error signals that may cause the ripple.
Due to the presence of the capacitor 101, the input voltage is isolated by the capacitor 101 and is not transmitted to the hysteresis comparator 104, so the requirement for the hysteresis comparator 104 is no longer limited by the input voltage or the voltage range of the input voltage. Accordingly, the reference voltage Vref may be independent of the input voltage, in other words, the signal transmission circuit of the embodiment of the present invention is decoupled from the reference voltage Vref.
Thus, optionally, the reference voltage Vref of the reference voltage Vref generator 103 is independent of the input voltage, and the voltage VCC received by the reference voltage generator for generating the reference voltage Vref is independent of the input voltage. The voltage VCC is preferably a voltage lower than the input voltage. Accordingly, the reference voltage Vref may be a fixed voltage independent of the input voltage, for example, 0.7V, which is merely an example and is not limited.
Optionally, with continued reference to fig. 1, the signal transmission circuit may further include: a switch module 105. The second terminal of the capacitor 101 and the second terminal of the resistor 102 are connected through a switch module 105, specifically, the first terminal of the switch module 105 is connected to the second terminal of the capacitor 101, the second terminal of the switch module 105 receives the specified voltage VC _ INIT, and the third terminal of the switch module 105 is connected to the second terminal of the resistor 102.
When the first end and the second end of the switch module 105 are connected, the first end and the third end of the switch module 105 are disconnected, and the second end of the capacitor 101 receives the specified voltage VC _ INIT; when the first terminal and the third terminal of the switch module 105 are turned on, the first terminal and the second terminal of the switch module 105 are turned off, and the second terminal of the capacitor 101 is connected to the second terminal of the resistor 102.
Fig. 2 shows a signal transmission circuit according to another embodiment of the present invention, and on the basis of fig. 1, the switch module 105 in fig. 2 is further a single-pole double-throw switch. The first terminal of the switch module 105 is a moving terminal of the single-pole double-throw switch, and the second terminal and the third terminal of the switch module 105 are two stationary terminals of the single-pole double-throw switch.
It is understood that the switch module 105 is not limited to a single-pole double-throw switch, and may be implemented by two switches, for example, one switch is connected between the capacitor 101 and the output terminal of the specified voltage VC _ INIT, and the other switch is connected between the capacitor 101 and the resistor 102, which is not limited in particular.
Optionally, the first input end is a non-inverting input end, and the second input end is an inverting input end; on this basis, when the switch module 105 switches from the first terminal to the second terminal to the first terminal and the third terminal, the first input terminal of the hysteresis comparator 104 receives the specified voltage VC _ INIT to initialize the output of the hysteresis comparator 104; the superimposed signal VIN is input to the power input pin after the initialization of the output of the hysteresis comparator 104 is implemented.
The switch module 105 may be controlled by an external device, or may be controlled by a system in which the signal transmission circuit is located, for example, the first terminal and the second terminal may be turned on before the digital signal needs to be transmitted, the first terminal and the third terminal may be turned on again, and then the digital signal transmission may be started again.
Optionally, the designated voltage VC _ INIT is greater than the reference voltage Vref, and a difference between the designated voltage VC _ INIT and the reference voltage Vref is greater than the hysteresis voltage of the hysteresis comparator 104; alternatively, the designated voltage VC _ INIT is less than the reference voltage Vref, and the difference between the reference voltage Vref and the designated voltage VC _ INIT is greater than the hysteresis voltage of the hysteresis comparator 104.
The output of the hysteresis comparator 104 may be initialized to a logic low level or a logic low level, which may be determined by setting the magnitude of the designated voltage VC _ INIT.
Taking the example that the designated voltage VC _ INIT is greater than the reference voltage Vref and the difference between the designated voltage VC _ INIT and the reference voltage Vref is greater than the hysteresis voltage of the hysteresis comparator 104, the first terminal and the second terminal of the switch module 105 are turned on, so the second terminal of the capacitor 101 receives the designated voltage VC _ INIT, and then the first terminal and the third terminal of the switch module 105 are turned on, at this time, the second terminal voltage VC _ IN of the capacitor 101 is equal to the designated voltage VC _ INIT, correspondingly, the second terminal voltage VC of the resistor 102 is also equal to the designated voltage VC _ INIT, so the voltage difference of the first terminal voltage VC of the second terminal of the resistor 102 is the difference between the designated voltage VC _ INIT and the reference voltage Vref, and the difference is greater than the hysteresis voltage, so the hysteresis comparator 104 is controlled to output a low level at this time, thereby implementing the output initialization.
Optionally, the designated voltage VC _ INIT is a voltage supported inside a device in which the signal transmission circuit is located. Of course, the designated voltage VC _ INIT is preferably, but not limited to, other suitable voltages.
The following example illustrates the operation of the signal transmission circuit according to the embodiment of the present invention:
before transmitting a digital signal, a first terminal of the capacitor 101 may receive an input voltage through a power input pin, a first terminal and a second terminal of the switch module 105 are turned on, and a second terminal of the capacitor 101 may be connected to an output terminal of a specified voltage VC _ INIT through the switch module 105 to receive the specified voltage VC _ INIT, where the specified voltage VC _ INIT may be, for example, a voltage inside a system, and specifically may be 1.4V;
once the digital signal transmission is ready, the switch module 105 switches from the first terminal and the second terminal conduction to the first terminal and the third terminal conduction, the second terminal of the capacitor 101 is connected to the second terminal of the resistor 102 through the switch module 105 (in this example, the second terminal of the resistor 102 may be an inverting input terminal of the hysteresis comparator 104), at this time, since the voltage difference between the two terminals of the capacitor 101 does not suddenly change, the voltage VC at the second terminal of the resistor 102 is equal to the specified voltage VC _ INIT, that is, 1.4V, the hysteresis voltage of the hysteresis comparator 104 may be, for example, 50mV, and VC-Vref-0.7V is greater than the hysteresis voltage of the hysteresis comparator 104, at this time, the hysteresis comparator 104 outputs a logic low level, that is, the hysteresis comparator 104 enters a ready stage of waiting for receiving the superimposed signal VIN from the power input pin; in practical application, the variation period of the digital signal modulated by the input voltage is set to be much longer than the charging or discharging time of the capacitor 101 through the resistor 102, so that after the capacitor 101 is charged or discharged through the resistor 102, VC equals to Vref equals to 0.7, and at this time, the voltage difference between VC and Vref is zero and less than 50mV, so that the output of the hysteresis comparator 104 remains unchanged;
when the signal transmission is started, the power input pin receives the superposed signal VIN, if the digital signal jumps from a high level to a low level, the superimposed signal VIN is pulled down by a voltage from the initial state, for example, from VIN-5.0V to VIN-4.8V, i.e. the superimposed signal VIN is decreased by 0.2V, since the voltage difference between the two terminals of the capacitor 101 will not change abruptly, the voltage VC _ IN at the second terminal of the capacitor 101 and the voltage VC at the second terminal of the resistor 102 (at this time, the voltage between the second terminal of the capacitor 101 and the second terminal of the resistor 102 is IN a conducting state) will also decrease by 0.2V, i.e., VC _ IN is 0.5V, and Vref-VC is 0.2V over 50mV, the hysteresis comparator 104 outputs a logic high level, that is, the target signal RX _ COMM changes to logic high level, and at the same time, the capacitor 101 is charged through the resistor 102, the charging process is terminated soon, and the second terminal voltage VC _ IN of the capacitor 101 continues to be equal to the reference voltage Vref; similarly, if the digital signal jumps from a low level to a high level, i.e., the superimposed signal VIN returns from 4.8V to 5.0V, the hysteresis comparator 104 outputs back to a logic low level, i.e., the target signal RX _ COMM changes to a logic low level.
In this way, the signal transmission circuit realizes the purpose of capturing the output of the digital signal changed on the power supply input pin through the hysteresis comparator 104.
Fig. 3 shows a relationship between a digital signal and a target signal RX _ COMM, where the superimposed signal VIN is superimposed with the digital signal to be transmitted, and a waveform of the target signal RX _ COMM is obtained through Propagation Delay (Propagation Delay) and Logic inversion (Logic Inverter) of the signal transmission circuit according to the embodiment of the present invention, that is, capture and reception of the digital signal on the power input pin are achieved.
Fig. 4 is a circuit schematic diagram of a first processing module 200 and a second processing module 300 that need to communicate and a signal transmission circuit according to an embodiment of the present invention, in an application scenario, the first processing module 200 may be, for example, a processor in a charging device, and the second processing module 300 may be, for example, a processor in a device to be charged, such as a wireless bluetooth headset, and is not limited thereto. The signal transmission circuit may be in the same device or belong to the same system as any one of the first processing module 200 or the second processing module 300, for example. When the first processing module 200 needs to communicate with the second processing module 300, for example, to perform signal control or data information interaction, the first processing module 200 may implement superposition of an input voltage and a digital signal, output the superposed signal VIN to a power input pin of a signal transmission circuit, and output a target signal RX _ COMM to the second processing module 300 through transmission of the signal transmission circuit, where communication between the first processing module 200 and the second processing module 300 is implemented because the target signal RX _ COMM represents a digital signal.
The invention also provides an electronic device comprising the signal transmission circuit in the embodiment. Of course, the electronic device may further include at least one of the first processing module 200 and the second processing module 300, which may specifically refer to the contents in the foregoing embodiments, and will not be described herein again.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A signal transmission circuit is characterized by comprising a power supply input pin, a signal processing circuit and a signal processing circuit, wherein the power supply input pin is used for receiving a superposed signal, and the superposed signal is a signal obtained by superposing an input voltage and a digital signal; the signal transmission circuit includes at least: a reference voltage generator, a capacitor, a resistor, and a hysteresis comparator;
the output end of the reference voltage generator is connected with the first end of the resistor and used for providing reference voltage to the first end of the resistor;
the first end of the capacitor is connected with the power input pin, the second end of the capacitor is connected with the second end of the resistor, and the voltage of the second end of the capacitor changes when the level jump of a superposed signal received by the power input pin occurs, so that the voltages of the two ends of the resistor are different; the resistor and the capacitor form a charge-discharge circuit, the charge-discharge circuit is used for charging or discharging when voltages at two ends of the resistor are different until the voltages at the two ends of the resistor are the same, and the one-time charging or discharging duration of the charge-discharge circuit is shorter than the period of the digital signal;
a first input end of the hysteresis comparator is connected with a first end of the resistor, a second input end of the hysteresis comparator is connected with a second end of the resistor, the hysteresis comparator is used for outputting a target signal according to the voltage difference change of the two ends of the resistor, and the target signal is used for representing the digital signal;
the difference between the high level and the low level of the digital signal is greater than the hysteresis voltage of the hysteresis comparator.
2. The signal transmission circuit of claim 1, wherein the signal transmission circuit further comprises: a switch module;
the first end of the switch module is connected with the second end of the capacitor, the second end of the switch module receives a specified voltage, and the third end of the switch module is connected with the second end of the resistor;
when the first end and the second end of the switch module are conducted, the first end and the third end of the switch module are switched off, and the second end of the capacitor receives the specified voltage;
when the first end and the third end of the switch module are connected, the first end and the second end of the switch module are switched off, and the second end of the capacitor is connected with the second end of the resistor.
3. The signal transmission circuit of claim 2,
the first input end is a non-inverting input end, and the second input end is an inverting input end;
when the switch module is switched from the first end to the second end to the first end and the third end, the first input end of the hysteresis comparator receives the specified voltage to realize the output initialization of the hysteresis comparator;
the superposition signal is input to the power input pin after initialization of the output of the hysteresis comparator is achieved.
4. The signal transmission circuit of claim 2,
the specified voltage is greater than the reference voltage, and a difference between the specified voltage and the reference voltage is greater than a hysteresis voltage of the hysteresis comparator;
or,
the specified voltage is less than the reference voltage, and a difference between the reference voltage and the specified voltage is greater than a hysteresis voltage of the hysteresis comparator.
5. The signal transmission circuit of claim 2,
the specified voltage is a voltage supported inside the device where the signal transmission circuit is located.
6. The signal transmission circuit of claim 2, wherein the switch module is a single pole double throw switch;
the first end of the switch module is the moving end of the single-pole double-throw switch, and the second end and the third end of the switch module are two fixed ends of the single-pole double-throw switch.
7. The signal transmission circuit of claim 1,
the target signal has the same period as the digital signal, and the target signal is in phase with or in anti-phase with the digital signal.
8. The signal transmission circuit of claim 1,
the reference voltage generator provides a reference voltage independent of the input voltage, and the voltage received by the reference voltage generator for generating the reference voltage is independent of the input voltage.
9. An electronic device, characterized in that it comprises a signal transmission circuit according to any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011124746.5A CN112290929B (en) | 2020-10-20 | 2020-10-20 | Signal transmission circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011124746.5A CN112290929B (en) | 2020-10-20 | 2020-10-20 | Signal transmission circuit and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112290929A CN112290929A (en) | 2021-01-29 |
| CN112290929B true CN112290929B (en) | 2021-07-02 |
Family
ID=74424090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011124746.5A Active CN112290929B (en) | 2020-10-20 | 2020-10-20 | Signal transmission circuit and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112290929B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113342112B (en) * | 2021-06-23 | 2023-05-12 | 江苏应能微电子有限公司 | Reference voltage control device and method and electronic equipment |
| CN113612472B (en) * | 2021-07-01 | 2024-05-10 | 上海爻火微电子有限公司 | Level conversion circuit and electronic equipment |
| CN113538882B (en) * | 2021-07-16 | 2022-12-13 | 上海爻火微电子有限公司 | Signal transmission circuit and electronic equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102831093A (en) * | 2010-02-04 | 2012-12-19 | 矽力杰半导体技术(杭州)有限公司 | Multiplexing circuit and multiplexing method for chip pin |
| CN210075195U (en) * | 2019-06-19 | 2020-02-14 | 深圳市三旺通信股份有限公司 | Digital signal isolation transmission circuit based on capacitor and forward buffer |
| CN210075196U (en) * | 2019-06-19 | 2020-02-14 | 深圳市三旺通信股份有限公司 | Digital signal isolation transmission circuit based on capacitor and operational amplifier |
| CN209930234U (en) * | 2019-06-19 | 2020-01-10 | 深圳市三旺通信股份有限公司 | Digital signal isolation transmission circuit based on capacitor and Schmitt trigger |
-
2020
- 2020-10-20 CN CN202011124746.5A patent/CN112290929B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112290929A (en) | 2021-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112290929B (en) | Signal transmission circuit and electronic equipment | |
| CN110333767B (en) | Multiphase power converter | |
| US10741112B2 (en) | Display apparatus and protection circuit thereof | |
| CN115395762B (en) | Single-inductor voltage transformation multi-voltage independent output circuit and related product | |
| KR20210045912A (en) | An electronic device comprising a resonant charging circuit | |
| CN206003410U (en) | A kind of disappearing for button trembles the circuit module of experimental demonstration teaching | |
| US8058912B2 (en) | Electronic device and signal generator thereof | |
| CN116247933B (en) | Power supply device and working mode configuration circuit for power supply chip | |
| CN104536314B (en) | Start control circuit, method and electronic equipment based on near-field communication NFC | |
| US20210119465A1 (en) | Electronic device including resonant charging circuit | |
| CN114914967A (en) | Charging box circuit, wireless earphone and wireless earphone system | |
| CN116908743A (en) | Charge pump fault detection circuit, detection method and electronic equipment | |
| CN109489844A (en) | Temperature sensing circuit | |
| CN109394169B (en) | Medical Devices with hysteresis module | |
| US20230123847A1 (en) | Handshake controllers for charging protocols related to multiport chargers and methods thereof | |
| US20230058715A1 (en) | Adding circuit for multi-channel signals and implementation method of adding circuit for multi-channel signals | |
| CN101546205B (en) | Power management circuit and frequency compensation method thereof | |
| CN107181290B (en) | Battery management system | |
| EP3545624B1 (en) | Phase interpolator and interpolating method | |
| CN112787504B (en) | Charge pump step-down IC and electronic device | |
| CN208849505U (en) | Medical Devices with hysteresis module | |
| JP2006135888A (en) | Data communication apparatus, data communication system and data communication method | |
| CN114839444A (en) | Circuit for detecting resistance value and apparatus for detecting resistance value | |
| CN113447697A (en) | Signal detection circuit, signal detection method, touch panel and display device | |
| CN220473673U (en) | Charge pump fault detection circuit, charging plug, charging system and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |