CN116247633A - Static protection circuit with stable discharge mechanism - Google Patents

Abstract

An electrostatic protection circuit with a stable discharge mechanism. The voltage dividing circuit generates a detection signal according to the voltage input end, and the first inverter outputs an inverted detection signal. The first P-type and N-type transistor circuits are connected in series between the voltage input terminal and the ground terminal through the first terminal. The second N-type transistor circuit is coupled between the second terminal and the ground terminal. The first P-type transistor control terminal is coupled to the second terminal, and the first and second N-type transistor control terminals respectively receive the inverted detection signal and the detection signal. The resistor and the capacitor of the capacitance-resistance circuit are connected in series between the voltage input end and the grounding end through the control end, and the control end is coupled to the second end. The second inverter receives the inverted lifting detection signal from the control end and outputs the inverted lifting detection signal as a lifting detection signal in an inverted mode. The electrostatic discharge transistor is controlled by the lifting detection signal to discharge the voltage input end when being conducted.

Description

Static protection circuit with stable discharge mechanism

Technical Field

The present invention relates to electrostatic protection technology, and more particularly, to an electrostatic protection circuit with a stable discharging mechanism.

Background

Static discharge (electrostatic discharge; ESD) can cause permanent damage to electronic components, equipment, and so affect the circuit function of integrated circuits, rendering the product incapable of functioning properly.

The phenomenon of electrostatic discharge may occur in the context of chip manufacturing, packaging, testing, storage or handling. In order to reproduce and prevent electrostatic discharge, the integrated circuit product can pass through the electrostatic protection element or circuit and match with test to enhance the protection capability of the integrated circuit to electrostatic discharge, thereby improving the yield of the electronic product.

Disclosure of Invention

In view of the above problems, it is an objective of the present invention to provide an electrostatic protection circuit with a stable discharging mechanism, so as to improve the prior art.

The invention includes an electrostatic protection circuit with a stable discharge mechanism, comprising: the device comprises a voltage dividing circuit, a first inverter, a voltage lifting circuit, a capacitance resistance circuit, a second inverter and an electrostatic discharge transistor. The voltage dividing circuit is electrically coupled to a voltage input terminal configured to receive the power signal, so as to generate a detection signal at the voltage dividing terminal. The first inverter is configured to receive the detection signal and output the detection signal as an inverted detection signal. The voltage boost circuit includes: a first P-type transistor circuit, a first N-type transistor circuit, and a second N-type transistor circuit. The first P-type transistor circuit and the first N-type transistor circuit are connected in series between the voltage input end and the grounding end through a first end, and are respectively provided with a first P-type transistor control end electrically coupled to a second end and a first N-type transistor control end configured to receive an inversion detection signal. The second N-type transistor circuit is electrically coupled between the second terminal and the ground terminal and has a second N-type transistor control terminal configured to receive the detection signal. The capacitance resistance circuit comprises a resistor electrically coupled between the voltage input end and the control end and a capacitor electrically coupled between the control end and the ground end, wherein the control end is electrically coupled to the second end. The second inverter is electrically coupled between the voltage input terminal and the ground terminal, and is configured to receive the inverted lift detection signal from the control terminal and output the inverted lift detection signal as a lift detection signal. The electrostatic discharge transistor is electrically coupled between the voltage input end and the grounding end, and is configured to be controlled by the lifting detection signal so as to discharge the voltage input end when the electrostatic discharge transistor is turned on.

The features, implementation and functions of the present invention are described in detail below with reference to the preferred embodiments shown in the drawings.

Drawings

FIG. 1 is a circuit diagram of an electrostatic discharge protection circuit with a stable discharge mechanism according to an embodiment of the present invention; and

FIG. 2 is a circuit diagram of an ESD protection circuit with a stable discharging mechanism according to another embodiment of the present invention.

Detailed Description

One of the objectives of the present invention is to provide an electrostatic protection circuit with a stable discharging mechanism, which can directly detect the voltage variation through the arrangement of a voltage dividing circuit to achieve a fast reaction and maintain a long enough discharging time, so as to stabilize the discharging of a discharging transistor, and to stabilize the switching of the electrostatic discharging transistor through a resistance capacitance circuit arranged at the rear end.

Please refer to fig. 1. Fig. 1 shows a circuit diagram of an esd protection circuit 100 with a stable discharging mechanism according to an embodiment of the invention. The electrostatic protection circuit 100 includes: the voltage divider 110, the first inverter 120, the voltage boosting circuit 130, the capacitance-resistance circuit 140, the second inverter 150, and the electrostatic discharge transistor 160.

The voltage divider 110 is electrically coupled to a voltage input terminal IO configured to receive the power signal PS, so as to generate a detection signal DS at a voltage divider terminal DT.

In one embodiment, the voltage dividing circuit 110 includes a first resistive circuit 115A and a second resistive circuit 115B connected in series between the voltage input terminal IO and the ground terminal GND through the voltage dividing terminal DT.

The first resistive circuit 115A includes a resistor, a diode-connected transistor, or a combination thereof. The number of the above-mentioned elements may be one or more, and may be connected in series when the number is plural. In fig. 1, the first resistive circuit 115A is exemplarily shown as a plurality of diode-connected P-type transistors, and the second resistive circuit 115B is exemplarily shown as a resistor. In other embodiments, the above-described other elements, diode-connected N-type transistors, or combinations of the above elements may be implemented. The present invention is not limited thereto.

In an embodiment, the esd protection circuit 100 is disposed in an electronic device (not shown), and receives the power signal PS through the voltage input terminal IO when the electronic device is operating, and generates the detection signal DS at the voltage dividing terminal DT according to the resistance ratio between the first resistive circuit 115A and the second resistive circuit 115B.

The first inverter 120 operates according to the first voltage VDD 1. The voltage boosting circuit 130, the second inverter 150 and the electrostatic discharge transistor 160 operate according to the second voltage VDD2. Wherein the first voltage VDD1 is smaller than the second voltage VDD2. In one embodiment, the first voltage VDD1 is, for example, but not limited to, 0.9, 1.2, or 1.8 volts. The second voltage VDD2 is, for example, but not limited to, 3.3 volts.

The second voltage VDD2 is generated according to the power signal PS in the present embodiment. In more detail, in one embodiment, the voltage boosting circuit 130, the second inverter 150 and the esd transistor 160 can be electrically coupled to the voltage input terminal IO to receive the power signal PS. The components and the voltage input terminal IO may include other circuit components without affecting the function of the overall esd protection circuit 110.

In various embodiments, the first voltage VDD1 may be selectively generated by another independent power signal (not shown) or generated according to the voltage division of the power signal PS.

Accordingly, the internal components (e.g., transistors) of the first inverter 120 have relatively low threshold voltages, while the internal components (e.g., transistors) of the voltage boost circuit 130, the second inverter 150, and the electrostatic discharge transistor 160 have relatively high threshold voltages. The first inverter 120 has a higher response speed than the voltage boosting circuit 130, the second inverter 150, and the electrostatic discharge transistor 160.

The first inverter 120 is configured to receive the detection signal DS and invert the output as an inverted detection signal IDS.

The voltage boost circuit 130 is configured to generate an inverted boost detection signal IBDS according to the detection signal DS and the inverted detection signal IDS. In one embodiment, the voltage boost circuit 130 comprises: a first P-type transistor circuit 170A, a first N-type transistor circuit 170B, and a second N-type transistor circuit 180A.

In the embodiment of fig. 1, the first P-type transistor circuit 170A includes a P-type transistor MP1, the first N-type transistor circuit 170B includes two first N-type transistors MN1 and MN2 connected in series, and the second N-type transistor circuit 180A includes two first N-type transistors MN3 and MN4 connected in series.

The first P-type transistor circuit 170A and the first N-type transistor circuit 170B are connected in series between the voltage input terminal IO and the ground terminal GND through the first terminal T1, and respectively have a first P-type transistor control terminal electrically coupled to the second terminal T2 and a first N-type transistor control terminal configured to receive the inverted detection signal IDS.

In more detail, in the embodiment of fig. 1, the source of the P-type transistor MP1 is electrically coupled to the voltage input terminal IO, the drain is electrically coupled to the first terminal T1, and the gate is electrically coupled to the second terminal T2 as the control terminal of the first P-type transistor. The drain of the first N-type transistor MN1 is electrically coupled to the first terminal T1, and the source is electrically coupled to the drain of the N-type transistor MN 2. The drain of the second N-type transistor MN2 is electrically coupled to the source of the N-type transistor MN1, and the source is electrically coupled to the ground GND. The gates of the first N-type transistor MN1 and the second N-type transistor MN2 are electrically coupled and used as a control terminal of the first N-type transistor to receive the inverted detection signal IDS.

The second N-type transistor circuit 180A is electrically coupled between the second terminal T2 and the ground terminal GND, and has a second N-type transistor control terminal configured to receive the detection signal DS.

In more detail, in the embodiment of fig. 1, the drain of the N-type transistor MN3 is electrically coupled to the second terminal T2, and the source is electrically coupled to the drain of the N-type transistor MN4. The drain of the N-type transistor MN4 is electrically coupled to the source of the N-type transistor MN3, and the source is electrically coupled to the ground GND. The gates of the N-type transistor MN3 and the N-type transistor MN4 are electrically coupled and serve as a second N-type transistor control terminal for receiving the detection signal DS.

In one embodiment, the first N-type transistors MN1 and MN3 are I/O devices (I/O devices) having a higher voltage withstand (e.g., 3.3 volts) capability, and the second N-type transistors MN2 and MN4 are core devices (core devices) having a lower voltage withstand (e.g., 0.9, 1.2 or 1.8 volts). With this configuration, the first N-type transistor circuit 170B and the second N-type transistor circuit 180A can have better reliability.

In an embodiment, the first N-type transistor circuit 170B may be selectively connected in series with the first N-type transistor MN1 and the second N-type transistor MN2 and controlled by an N-type transistor (not shown) of another control signal, so that the first N-type transistor circuit 170B is turned on according to the control signal after the first voltage VDD1 and the second voltage VDD2 are powered up when the source of the first voltage VDD1 and the source of the second voltage VDD2 are different, so that the unknown signal state in the circuit is not caused by the sequence of the power up. Similarly, the second N-type transistor 180A may have the same configuration, and will not be described herein.

The capacitance-resistance circuit 140 includes a resistor R electrically coupled between the voltage input terminal IO and the control terminal CT and a capacitor C electrically coupled between the control terminal CT and the ground terminal GND, wherein the control terminal TC is electrically coupled to the second terminal T2.

The second inverter 150 is electrically coupled between the voltage input terminal IO and the ground terminal GND, and is configured to receive the inverted lift detection signal IBDS from the control terminal TC and output the same as the lift detection signal BDS in an inverted manner.

The esd transistor 160 is electrically coupled between the voltage input terminal IO and the ground terminal GND, and is configured to be controlled by the lifting detection signal BDS to discharge the voltage input terminal IO when turned on. In the present embodiment, the esd transistor 160 is an N-type transistor. In other embodiments, the esd protection circuit 100 may further include another inverter between the esd transistor 150 and the second inverter 140, and the esd transistor 150 is implemented as a P-type transistor. The invention is not limited thereto.

The following description will be made on the normal operation mode and the discharge mode of the esd protection circuit 100 according to the voltage level of the voltage input terminal IO. In fig. 1, according to the logic level of the voltage, a "1" is marked as a high level, a "0" is marked as a low level, and the logic levels in the normal operation mode and the discharge mode are marked in sequence at each circuit node.

When the voltage level of the voltage input terminal IO does not exceed the predetermined level, for example, only the power signal PS is received and the electrostatic input ES is not received, for example, due to the actual electrostatic generation or excessive electrical stress (electrical over shoot; EOS), the electrostatic protection circuit 100 operates in the normal operation mode. At this time, the detection signal DS generated by the voltage divider 110 at the voltage divider terminal DT is at the low level (0), and the inverted detection signal IDS is at the high level (1) due to the operation of the first inverter 120.

According to the inverted detection signal IDS at the high level and the detection signal DS at the low level, the first N-type transistor circuit 170B is turned on, and the first P-type transistor circuit 170A and the second N-type transistor circuit 180A are turned off.

In more detail, the first N-type transistor MN1 and the second N-type transistor MN2 in the first N-type transistor circuit 170B are turned on by the inversion detection signal IDS at the high level, and draw a current to the first terminal T1 to lower the voltage of the first terminal T1 to the low level (0). The first N-type transistor MN3 and the second N-type transistor MN4 in the second N-type transistor circuit 180A are turned off due to the detection signal DS at the low level.

The capacitor C in the resistance-capacitance circuit 140 receives the charge of the voltage input terminal IO through the resistor R, so that the voltage of the control terminal CT rises to the high level (1). Since the second N-type transistor circuit 180A is turned off, the control terminal CT will not discharge through the second terminal T2. Therefore, the voltage at the second terminal T2 will rise to the high level (1) along with the control terminal CT, thereby turning off the P-type transistor MP1 in the first P-type transistor circuit 170A.

The anti-phase-rise detection signal IBDS generated by the control terminal CT is thus at the high level (1). The lifting detection signal BDS is at a low level (0) due to the operation of the second inverter 150, thereby turning off the ESD transistor 160.

On the other hand, when the voltage level of the voltage input terminal IO exceeds the predetermined level, for example, the power signal PS is received and the electrostatic input ES with the instantaneous large voltage is also received, the electrostatic protection circuit 100 operates in the discharging mode. At this time, the detection signal DS generated by the voltage divider 110 at the voltage divider terminal DT is at the high level (1), and the inverted detection signal IDS is at the low level (0) due to the operation of the first inverter 120.

According to the inverted detection signal IDS at the low level and the detection signal DS at the high level, the first N-type transistor circuit 170B is turned off, and the first P-type transistor circuit 170A and the second N-type transistor circuit 180A are turned on.

In more detail, the first N-type transistor MN3 and the second N-type transistor MN4 in the second N-type transistor circuit 180A are turned on by the detection signal DS at the high level, and draw a current to the second terminal T2 to lower the voltage of the second terminal T2 to the low level (0), so that the P-type transistor MP1 in the first P-type transistor circuit 170A is turned on. The first N-type transistor MN1 and the second N-type transistor MN2 in the first N-type transistor circuit 170B are turned off due to the inverted detection signal IDS at the low level, so that the first terminal T1 receives the current of the P-type transistor MP1 and the voltage of the first terminal T1 rises to the high level (1).

The capacitor C in the resistance-capacitance circuit 140 discharges under the conduction of the second N-type transistor circuit 180A through the control terminal CT and the second terminal T2, so that the voltage of the control terminal CT drops to the low level (0).

The anti-phase-up detection signal IBDS generated by the second terminal T2 is thus at the low level (0). The lifting detection signal BDS is at the high level (1) due to the operation of the second inverter 150, so that the ESD transistor 160 is turned on to discharge the voltage input terminal IO.

In the above operation, the time constant (the product of the resistance value of the resistor R and the capacitance value of the capacitor C) of the capacitance circuit 140 determines the high-frequency response time of the electrostatic protection circuit 100, and the voltage divider circuit 110 and the first inverter 120 determine the low-frequency response time of the electrostatic protection circuit 100.

It should be noted that, when the esd transistor 150 discharges the voltage input terminal IO for a period of time, the voltage of the voltage input terminal IO drops, so that the detection signal DS generated by the voltage division returns to the low level (0), the esd protection circuit 110 will also return to the normal operation mode.

In some technologies, the electrostatic protection circuit is connected to the electrostatic input terminal by a capacitance-resistance circuit, so as to control the inverter to determine whether to start the discharge transistor. The capacitance-resistance circuit is set based on the frequency of electrostatic input as the basis of whether to start the electrostatic discharge mechanism. When the electrostatic input is not long enough or the energy input is not large enough, the charged Rong Zu circuit will make the inverter react slowly, and not only the turn-on time is late, but also the discharge mechanism cannot be maintained for a long enough time. Also, in such a situation, the discharge transistor often needs to operate by means of a breakdown (breakdown) mechanism, resulting in non-uniform conduction.

Therefore, the static protection circuit can directly detect the voltage change through the arrangement of the voltage dividing circuit to achieve quick response and maintain enough discharge time, so that the discharge of the discharge transistor is stable, and the switch of the static discharge transistor is more stable through the capacitance-resistance circuit arranged at the rear end.

It should be noted that the number of transistors included in the first P-type transistor circuit 170A, the first N-type transistor circuit 170B, and the second N-type transistor circuit 180A is only an example. In other embodiments, the number of transistors included in the above-mentioned circuit can be adjusted according to practical requirements, and the invention is not limited thereto.

Please refer to fig. 2. Fig. 2 shows a circuit diagram of an esd protection circuit 200 with a stable discharging mechanism according to another embodiment of the invention.

Similar to the esd protection circuit 100 of fig. 1, the esd protection circuit 200 of fig. 2 includes: the voltage divider 110, the first inverter 120, the voltage boosting circuit 130, the second inverter 150, and the electrostatic discharge transistor 160. The voltage boost circuit 130 also includes: a first P-type transistor circuit 170A, a first N-type transistor circuit 170B, and a second N-type transistor circuit 180A. Therefore, the elements of the same structure and operation will not be described herein.

In this embodiment, the esd protection circuit 100 further includes a second P-type transistor 180B. The second P-type transistor circuit 180B includes a P-type transistor MP2 electrically coupled between the voltage input terminal IO and the second terminal T2 to be connected in series with the second N-type transistor circuit 180A, and has a second P-type transistor control terminal electrically coupled to the first terminal T1.

When the esd protection circuit 100 is operating in the normal operation mode, since the first terminal T1 is at the low level (0), the P-type transistor MP2 in the second P-type transistor 170A is turned on to enable the second terminal T2 to receive the current, so as to enhance the voltage of the second terminal T2 to rise to the high level (1). In contrast, when the esd protection circuit 100 is operated in the discharging mode, since the first terminal T1 is at the high level (1), the P-type transistor MP2 in the second P-type transistor circuit 170A is turned off, so that the operation of the second terminal T2 for drawing current from the second N-type transistor circuit 180A is reduced to the low level (0).

It should be noted that the number of transistors included in the second P-type transistor circuit 180B is only an example. In other embodiments, the number of the transistors included in the second P-type transistor circuit 180B can be adjusted according to practical requirements, and the invention is not limited thereto.

It should be noted that the above embodiment is only an example. In other embodiments, those skilled in the art will appreciate that modifications may be made without departing from the spirit of the invention.

In summary, the electrostatic protection circuit with the stable discharging mechanism can directly detect the voltage change through the arrangement of the voltage dividing circuit to achieve quick response and maintain enough discharging time, so that the discharging of the discharging transistor is stable, and the switch of the electrostatic discharging transistor is more stable through the capacitance-resistance circuit arranged at the rear end.

Although the embodiments of the present disclosure have been described above, these embodiments are not limited thereto, and those skilled in the art can make various changes to the technical features of the present disclosure according to the explicit or implicit disclosure of the present disclosure, where the various changes may be within the scope of protection sought herein, in other words, the scope of protection of the present disclosure shall be defined by the claims of the present disclosure.

[ symbolic description ]

100: static electricity protection circuit

110: voltage dividing circuit

115A: first resistive circuit

115B: second resistive circuit

120: first inverter

130: voltage lifting circuit

140: capacitance-resistance circuit

150: second inverter

160: electrostatic discharge transistor

170A: first P-type transistor circuit

170B: first N-type transistor circuit

180A: second N-type transistor circuit

180B: second P-type transistor circuit

200: static electricity protection circuit

BDS: lifting detection signal

C: capacitance device

CT: control terminal

DS: detecting a signal

DT: partial pressure end

GND: grounding end

IBDS: inverse phase lifting detection signal

IDS: inverse sense signal

IO: voltage input terminal

MN1, MN3: first N-type transistor

MN2, MN4: second N-type transistor

MP1, MP2: p-type transistor

PS: power supply signal

R: resistor

T1: first end

T2: second end

VDD1: first voltage

VDD2: a second voltage.

Claims (10)

1. An electrostatic protection circuit with a stable discharge mechanism, comprising:

the voltage dividing circuit is electrically coupled to a voltage input end configured to receive a power signal so as to generate a detection signal at a voltage dividing end;

a first inverter configured to receive the detection signal and output the detection signal as an inverted detection signal;

a voltage boost circuit comprising:

the first P-type transistor circuit and the first N-type transistor circuit are connected in series between the voltage input end and a grounding end through a first end, and are respectively provided with a first P-type transistor control end electrically coupled with a second end and a first N-type transistor control end configured to receive the reverse phase detection signal; and

a second N-type transistor circuit electrically coupled between the second terminal and the ground terminal and having a second N-type transistor control terminal configured to receive the detection signal;

a capacitance resistance circuit, which comprises a resistor electrically coupled between the voltage input end and a control end and a capacitor electrically coupled between the control end and a grounding end, wherein the control end is electrically coupled to the second end;

the second inverter is electrically coupled between the voltage input end and the grounding end and is configured to receive an inverted lifting detection signal from the control end and output the inverted lifting detection signal as a lifting detection signal; and

and the electrostatic discharge transistor is electrically coupled between the voltage input end and the grounding end and is configured to be controlled by the lifting detection signal so as to discharge the voltage input end when being conducted.

2. The esd protection circuit of claim 1, wherein the first inverter operates according to a first voltage, the voltage boosting circuit, the second inverter and the esd transistor operate according to a second voltage generated by the power signal, wherein the first voltage is less than the second voltage, and the first voltage is 0.9, 1.2 or 1.8 volts, and the second voltage is 3.3 volts.

3. The esd protection circuit of claim 2, wherein the second voltage is generated by the power signal and the first voltage is generated by another independent power signal.

4. The esd protection circuit of claim 2, wherein the second voltage is generated by the power signal and the first voltage is generated by dividing the power signal.

5. The electrostatic protection circuit of claim 1, wherein the voltage divider comprises a first resistive circuit and a second resistive circuit connected in series between the voltage input terminal and the ground terminal through the voltage divider, wherein the first resistive circuit and the second resistive circuit comprise a resistor, a diode-connected transistor, or a combination thereof, respectively.

6. The esd protection circuit of claim 1, wherein in a normal operation mode in which the voltage level at the voltage input does not exceed a predetermined level, the detection signal is at a low level, the inversion detection signal is at a high level, the first N-type transistor is turned on and the first P-type transistor and the second N-type transistor are turned off, the inversion lift detection signal is at the high level, and the lift detection signal is at the low level, thereby turning off the esd transistor.

7. The esd protection circuit of claim 1, wherein in a discharge mode in which the voltage at the voltage input exceeds a predetermined level due to receiving an esd input, the detection signal is at a high level, the inversion detection signal is at a low level, the first N-type transistor is turned off and the first P-type transistor and the second N-type transistor are turned on, the inversion lift detection signal is at the low level, and the lift detection signal is at the high level, thereby turning on the esd transistor.

8. The electrostatic protection circuit of claim 1, wherein the first N-type transistor circuit and the second N-type transistor circuit comprise a first N-type transistor and a second N-type transistor connected in series, respectively, wherein the first N-type transistor is an input/output device and the second N-type transistor is a core device.

9. The esd protection circuit of claim 1, further comprising a second P-type transistor circuit electrically coupled between the voltage input terminal and the second terminal for being connected in series with the second N-type transistor circuit and having a second P-type transistor control terminal electrically coupled to the first terminal.

10. The electrostatic protection circuit of claim 1, wherein a time constant of the resistance-capacitance circuit determines a high frequency response time of the electrostatic protection circuit, and the voltage divider circuit and the first inverter determine a low frequency response time of the electrostatic protection circuit.

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