CN116247084A - Trench gate power device and silicide gate manufacturing method - Google Patents

Trench gate power device and silicide gate manufacturing method Download PDF

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CN116247084A
CN116247084A CN202111485978.8A CN202111485978A CN116247084A CN 116247084 A CN116247084 A CN 116247084A CN 202111485978 A CN202111485978 A CN 202111485978A CN 116247084 A CN116247084 A CN 116247084A
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trench
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曾大杰
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Nantong Shangyangtong Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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Abstract

The invention discloses a trench gate power device and a method for manufacturing a silicide gate, which comprises a device main body, a front metal layer, a metalized drain electrode and a plurality of trench gates, wherein: the top end of the device main body is covered with a front metal layer, a plurality of grid grooves are concavely arranged at the top end of the device main body, the area between every two adjacent grid grooves is a semiconductor platform area, and the semiconductor platform area is connected with a metal source electrode; each trench gate comprises a gate dielectric layer and a gate conducting layer, the gate conducting layer is positioned in the gate trench, the top of the gate conducting layer is lower than the upper surface of the semiconductor platform region, and a dielectric groove is formed in the portion, higher than the gate conducting layer, of the gate trench; the top of the gate conducting layer is covered with a first medium, the first medium is connected with the metal gate, and a diffusion layer is formed at the joint of the first medium and the gate conducting layer. The trench gate power device and the method for manufacturing the silicide gate can reduce the gate square resistance of the trench gate device.

Description

Trench gate power device and silicide gate manufacturing method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench gate power device and a silicide gate manufacturing method.
Background
The larger the gate resistance, the slower the switching speed of the trench gate device during trench gate device switching. Therefore, in the chip design, the gate resistance needs to be reduced as much as possible. In addition, the trench gate device is formed by connecting a plurality of cells in parallel, and tens of thousands or even millions of cells are connected in parallel. There may be time delays at different places on the chip due to the gate resistance. The gate resistance is reduced, so that the on and off time of each cell can be synchronized as much as possible.
In the related art, the mode of reducing the gate resistance is mainly to increase a gate bus, and the gate bus is a metal wiring and is added with a plurality of gate metal feeder lines, so that the gate resistance can be reduced. This is a method for reducing gate resistance by layout, which is widely used in large chips, such as chips with chip areas exceeding 100 mm square, and typically uses 3 or even more than 4 gate metal feeder lines, and the width of the metal feeder lines is also very wide, typically greater than 50 μm or even more than 100 μm, in order to reduce the resistance of the metal feeder lines. The metal thickness used is also very thick, typically 4 μm and above. Too wide and too many metal feed lines can result in wasted active area. And it is not enough to use only metal feed lines, and it is also necessary to reduce the sheet resistance of the gate polysilicon.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a trench gate power device which is used for solving the problem of large square resistance of gate polysilicon of the trench gate device in the prior art.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: a trench gate power device comprising: device body, front side metal layer, metalized drain and a plurality of trench gates, wherein: the top end of the device main body covers the front metal layer, the front metal layer comprises a metal grid electrode and a metal source electrode, the bottom end of the device main body is connected with the metallized drain electrode, a plurality of grid grooves are concavely arranged at the top end of the device main body, a semiconductor platform area is arranged in an area between every two adjacent grid grooves, and the semiconductor platform area is connected with the metal source electrode; each trench gate comprises a gate dielectric layer and a gate conducting layer, the gate conducting layer is positioned in the gate trench, the top of the gate conducting layer is lower than the upper surface of the semiconductor platform region, a dielectric groove is formed in the portion, higher than the gate conducting layer, of the gate trench, and the gate dielectric layer is filled in a gap between the gate trench and the gate conducting layer; the top of the gate conducting layer is covered with a first medium, the first medium is connected with the metal gate, and a diffusion layer is formed at the joint of the first medium and the gate conducting layer.
Preferably, a partition gap is formed between the first medium and the side wall of the medium groove.
Preferably, the device body is divided into the semiconductor platform region, the first conductive type channel region, the second conductive type drift region and the semiconductor substrate from top to bottom in sequence.
Preferably, a buffer layer is further disposed between the second conductivity type drift region and the semiconductor substrate, and the doping concentration of the buffer layer is the same as that of the second conductivity type drift region.
Preferably, the semiconductor platform region includes a plurality of first heavily doped half regions and a plurality of second heavily doped half regions, one first heavily doped half region is respectively disposed at two sides of the gate trench, and each second heavily doped half region is located between two adjacent corresponding first heavily doped half regions.
Preferably, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N type, and the second conductivity type is P type.
Preferably, the first medium also covers the semiconductor mesa region.
Preferably, the gate dielectric layer is a gate oxide layer, and the gate conductive layer is a polysilicon gate.
The invention also provides a method for manufacturing the silicide grid of the trench gate power device, which comprises the following steps:
s1, carrying out self-aligned back etching on a gate conducting layer, back etching the top surface of the gate conducting layer in a gate groove to be lower than a first surface and forming a medium groove, wherein the medium groove has a first depth;
s2, depositing an intermediate medium in the medium groove, and carrying out back etching to enable the side wall of the medium groove to form a side wall composed of the intermediate medium, wherein the side wall has a first thickness;
s3, depositing a first medium on the first surface side, enabling the first medium to be combined with the gate conducting layer at the bottom of the side wall, and forming a diffusion layer at the combination position, wherein the first medium has a second thickness;
and S4, removing the side wall through etching to form a partition gap.
Preferably, the semiconductor platform region of the trench gate power device is a silicon substrate, and the step S3 further includes: the first medium is also deposited on the semiconductor platform region.
Preferably, the trench gate power device is an IGBT device, and the method for manufacturing a silicide gate of the trench gate power device further includes the following steps:
s5, removing the first medium deposited on the surface of the semiconductor platform region through photoetching.
Preferably, the first depth is 0.20 μm to 0.30 μm.
Preferably, the side wall is made of silicon nitride or silicon dioxide, and the first thickness is
Figure BDA0003397545980000031
Figure BDA0003397545980000032
Preferably, the first medium is metal and the second thickness is
Figure BDA0003397545980000033
Preferably, the combination reaction temperature of the first medium and the gate conductive layer is 800-1000 ℃ and the reaction time is 25-35 minutes.
Preferably, the first medium and the gate conductive layer are combined by adopting a rapid thermal annealing process, wherein the annealing temperature is 700-950 ℃ and the duration is 25-35 seconds.
Compared with the prior art, the invention has the beneficial effects that: the top of the device main body is concavely provided with a plurality of gate grooves, a semiconductor platform region is arranged between the adjacent gate grooves, a gate dielectric layer and a gate conducting layer are formed in the gate grooves, and the top of the gate conducting layer is lower than the semiconductor platform region, so that a dielectric groove is formed by surrounding the top of the gate conducting layer and the side wall of the semiconductor platform region, self-alignment back etching is convenient to carry out subsequently, the top of the gate conducting layer also covers a first dielectric, a diffusion layer is formed at the joint of the first dielectric and the gate conducting layer, the device main body is covered with a front metal layer to form a metal gate and a metal source electrode, the first dielectric is also connected with the metal gate, and the resistivity of the diffusion layer is between that of the polysilicon gate and the metal gate electrode, therefore, compared with the traditional polysilicon gate electrode, the square resistance of the gate polysilicon of the device is greatly reduced.
Drawings
FIG. 1 is a flow chart of a method for fabricating a silicide gate of a trench gate power device according to the present invention;
fig. 2 is a schematic diagram of a trench gate power device according to the present invention;
FIG. 3 is a schematic diagram of a trench gate power device according to the present invention after deposition of an intermediate medium;
fig. 4 is a schematic diagram of a trench gate power device according to the present invention after a first dielectric is deposited;
fig. 5 is a schematic diagram of a structure of a trench gate power device after removing a first medium in a semiconductor platform region;
reference numerals: 1-device body, 2-front side metal layer, 3-trench gate, 4-first dielectric, 5-intermediate dielectric, 11-gate trench, 12-semiconductor mesa region, 13-first conductivity type channel region, 14-second conductivity type drift region, 15-semiconductor substrate, 31-gate dielectric layer, 32-gate conductive layer, 33-dielectric trench, 121-first heavily doped half region, 122-second heavily doped half region.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1 and 2, the present embodiment provides a trench gate power device, which includes: a device body 1, a front side metal layer 2, a metalized drain, and a plurality of trench gates 3, wherein:
the top of the device main body 1 covers the front metal layer 2, the front metal layer 2 comprises a metal grid electrode and a metal source electrode, the bottom of the device main body 1 is connected with a metallized drain electrode, a plurality of grid grooves 11 are concavely arranged at the top of the device main body 1, a semiconductor platform area 12 is arranged in an area between every two adjacent grid grooves 11, and the semiconductor platform area 12 is connected with the metal source electrode.
As a preferred embodiment, the gate trench 11 is formed by using a photolithography and etching process, such as an anisotropic etching process, in order to ensure that the bottom of the gate trench 11 is as smooth as possible (because of the large electric field to be sustained), and the etching is adjusted to an isotropic etching process toward the end of the anisotropic etching process. Or oxidizing after etching is completed to make the top as smooth as possible. The width of the opening (i.e., the top) of the gate trench 11, which is typically formed last, will be greater than 0.2 μm.
As a preferred embodiment, the front metal layer 2 is patterned to form a metal gate and a metal source, which can greatly shorten the manufacturing period and improve the production efficiency. The front metal layer 2 is usually made of aluminum metal, and has a thickness of about 4 micrometers, so that the resistance of the source electrode can be reduced by increasing the thickness of the source electrode metal, and the heat capacity of the trench gate power device can be increased, thereby being beneficial to heat dissipation in transient state.
Each trench gate 3 includes a gate dielectric layer 31 and a gate conductive layer 32, the gate conductive layer 32 is located in the gate trench 11, the top of the gate conductive layer 32 is lower than the upper surface of the semiconductor mesa region 12, a dielectric groove 33 is formed in a portion of the gate trench 11 higher than the gate conductive layer 32, and the gate dielectric layer 31 fills a gap between the gate trench 11 and the gate conductive layer 32. The gate conductive layer 32 is a silicon substrate and is doped with different elements depending on the type of trench gate power device, for example: if the trench gate power device is an N-type trench gate, the gate conductive layer 32 is N-type heavily doped, and if the trench gate power device is a P-type trench gate, the gate conductive layer 32 is P-type heavily doped.
The top of the gate conductive layer 32 is covered with the first dielectric 4, and in a preferred embodiment, the first dielectric 4 is metal, for example, titanium, and the first dielectric 4 reacts with the silicon substrate of the gate conductive layer 32 to form a metal silicide diffusion layer, and the metal silicide diffusion layer is connected with the front metal layer 2, so that the connection resistance between the front metal layer 2 and the gate conductive layer 32 can be effectively reduced.
As a preferred embodiment, a blocking gap is formed between the first dielectric 4 and the sidewall of the dielectric trench 33 to prevent the first dielectric 4 from conducting with the semiconductor substrate 15, the first dielectric 45 is connected with the metal gate, and the semiconductor mesa region 12 of the dielectric trench 33 is connected with the metal source, so that the first dielectric 4 and the dielectric trench 33 cannot be conducted, and a gap is provided to prevent the first dielectric 4 from conducting in contact with the dielectric trench 33.
As a preferred embodiment, the device body 1 is divided into a semiconductor mesa region 12, a first conductivity type channel region 13, a second conductivity type drift region 14, and a semiconductor substrate 15 in this order from top to bottom. The semiconductor substrate 15 is connected to the drain. To reduce back-expansion of the semiconductor substrate 15, the substrate is typically fabricated with heavy doping of the arsenic element. However, since the lowest resistivity of the phosphorus element heavily doped substrate achieved in the prior art is lower than that of the arsenic element heavily doped substrate, the phosphorus element heavily doped substrate is also frequently used in the case of a relatively high substrate resistance ratio, such as a low voltage device below 40V. The thinner the substrate, the better the heat dissipation to the device, and the more significant the reduction of the substrate resistance. The choice of the second conductivity type drift region 14 determines the breakdown voltage of the device. In general, the higher the breakdown voltage of the device, the thicker the thickness of the second conductivity type drift region 14, and the lower the doping concentration of the second conductivity type drift region 14.
The first conductivity type channel region 13 is formed by channel ion implantation, and it is generally necessary to pass through a shielding oxide layer, so that occurrence of tunneling effect of ion implantation can be prevented, thereby preventing the depth of implanted ions from being too deep. The shielding oxide layer can be deposited or grown by thermal oxygen. The channel ions of the first conductivity type channel region 13 are implanted at a voltage of typically 60 to 150keV at a dose of between 5e12cm-2 and 2e13cm-2 with boron as an implanted impurity.
Preferably, for a trench gate 3MOSFET device of 20V, a semiconductor substrate 15 of highly doped phosphorus is generally used, the resistivity of the semiconductor substrate 15 is 0.0011 Ω×cm, the thickness of the semiconductor substrate 15 after thinning is 150 μm, the semiconductor substrate 15 is an N-type highly doped substrate with a bulk concentration of 1e19/cm3 or more, the high doping concentration is to reduce the resistance of the semiconductor substrate 15, and the drain region is composed of the N-type highly doped semiconductor substrate 15, and the drain composed of the back metal layer is formed on the back surface of the semiconductor substrate 15. And for the second conductivity type drift region 14, the trench gate 3 is formed in the second conductivity type drift region 14. The second conductivity type drift region 14 is a single layer drift region, the resistivity of the second conductivity type drift region 14 is 0.15 Ω×cm, and the thickness of the second conductivity type drift region 14 is 4 μm. The width of the gate trench 11 of the trench gate MOSFET device is 0.2 μm.
It should be noted that a buffer layer is further disposed between the second conductivity type drift region 14 and the semiconductor substrate 15, and the main purpose of the buffer layer is to prevent impurity atoms of the highly doped semiconductor substrate 9 from diffusing into the second conductivity type drift region 14 due to thermal processes of the process, so that the doping concentration of the drift region is increased, thereby reducing the breakdown voltage of the device. The doping concentration of the buffer layer generally remains substantially the same as the doping concentration of the second conductivity type drift region 14.
Further preferably, the semiconductor mesa region 12 includes a plurality of first heavily doped half regions 121 and a plurality of second heavily doped half regions 122, where one first heavily doped half region 121 is disposed on each side of the gate trench 11, and each second heavily doped half region 122 is located between two adjacent corresponding first heavily doped half regions 121. Wherein the first heavily doped half region is doped with a first conductivity type and the second heavily doped half region 122 is doped with a second conductivity type.
When the trench gate device is of a P-channel type, the first conductivity type is P-type and the second conductivity type is N-type. When the trench gate device is of an N-channel type, the first conductivity type is N-type and the second conductivity type is P-type. As a preferred embodiment, the first medium 4 also covers the semiconductor mesa region 12. For a silicon substrate device, the first dielectric 4 is covered on the semiconductor platform region 12, and a metal silicide layer is also formed, so that the on-resistance of the source electrode can be reduced. For IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor device), forming a metal silicide layer in the semiconductor mesa region 12 may reduce the breakdown voltage of the device, and the metal silicide layer may be removed by photolithography, and for devices with other silicon-like element substrates, the above process may also be implemented, which will not be described herein.
As a preferred embodiment, the gate dielectric layer 31 may be a gate nitride layer or a gate oxynitride layer, and in this embodiment, a gate oxide layer is preferred, and is formed by using a thermal oxidation process, where the thickness of the gate oxide layer determines the breakdown voltage that can be borne by the gate of the device. The thickness of the gate oxide layer is also very dependent on the threshold voltage of the device. Generally, the lower the threshold voltage required by the device, the thinner the thickness of the gate oxide layer.
In summary, in the trench gate power device provided by the invention, the top end of the device main body is concavely provided with a plurality of gate trenches, a semiconductor platform region is arranged between adjacent gate trenches, a gate dielectric layer and a gate conductive layer are formed in the gate trenches, and the top of the gate conductive layer is lower than the semiconductor platform region, so that the top of the gate conductive layer and the side wall of the semiconductor platform region form a dielectric groove, the subsequent self-alignment back etching is convenient, the top of the gate conductive layer is covered with a first medium, a diffusion layer is formed at the joint of the first medium and the gate conductive layer, the device main body is covered with a front metal layer to form a metal gate and a metal source, the first medium is connected with the metal gate, and the resistivity of the diffusion layer is between the polysilicon gate and the metal gate.
The invention also provides a method for manufacturing the silicide grid of the trench gate power device, which comprises the following steps:
s1, carrying out self-aligned back etching on a gate conducting layer, back etching the top surface of the gate conducting layer in a gate groove to be lower than a first surface and forming a dielectric groove, wherein the dielectric groove has a first depth;
s2, referring to FIG. 3, depositing an intermediate medium in the medium groove, and carrying out back etching to enable the side wall of the medium groove to form a side wall composed of the intermediate medium, wherein the side wall has a first thickness;
s3, referring to FIG. 4, depositing a first medium on the first surface side, wherein the first medium has a second thickness, so that the first medium is combined with the gate conductive layer at the bottom of the side wall and forms a diffusion layer at the combination position;
s4, removing the side wall through etching to form a partition gap.
As a preferred embodiment, the semiconductor platform region of the trench gate power device is a silicon substrate, and step S3 further includes: the first dielectric is also deposited on the semiconductor mesa region, so that for a silicon device, a metal silicide layer is also formed overlying the first dielectric in the semiconductor mesa region, which may reduce the on-resistance of the source.
Referring to fig. 5, as a preferred embodiment, the trench gate power device is an IGBT device, and the method for manufacturing a silicide gate of the trench gate power device further includes the steps of:
s5, removing the first medium deposited on the surface of the semiconductor platform region through photoetching.
As a preferred embodiment, the first depth is 0.20-0.30 μm, and since it is necessary to deposit the first dielectric in the dielectric trench later, it is necessary to make the dielectric trench depth deeper than normal, the depth of the normal trench MOSFET being around 0.1 μm.
As a preferred embodiment, the intermediate medium may be nitride, oxide or oxynitride, and in this embodiment is preferably silicon nitride or silicon dioxide, and the first thickness of the sidewall is
Figure BDA0003397545980000081
(/>
Figure BDA0003397545980000082
In units of length (in units of length),
Figure BDA0003397545980000083
)。
further preferably, the first thickness is
Figure BDA0003397545980000084
In a preferred embodiment, the first dielectric is made of a metal material, such as titanium, nickel, cobalt, etc., and the gate conductive layer is typically a silicon substrate, so that a diffusion layer of metal silicide can be formed by combining with the gate conductive layer, and it should be noted that when a substrate of another silicon-like element is used, the gate conductive layer can also be combined with the first dielectric to form a corresponding diffusion layer of metal compound, the second thickness being
Figure BDA0003397545980000085
Further preferably, the second thickness is
Figure BDA0003397545980000086
As a preferred embodiment, the bonding reaction temperature of the first medium and the gate conductive layer is 800-1000 ℃ and the reaction time is 25-35 minutes.
As a preferred embodiment, the first medium and the gate conductive layer are combined by adopting a rapid thermal annealing process, wherein the annealing temperature is 700-950 ℃ and the duration is 25-35 seconds.
In summary, according to the method for manufacturing the silicide gate provided by the invention, after the gate etching and the source drain injection are completed, an intermediate medium is deposited in the medium groove and etched back to form the side wall, then a first medium is deposited in the medium groove, the intermediate medium and the first medium cannot react, the first medium reacts with the surface of the gate conducting layer and is combined to form a diffusion layer, the first medium is connected with the gate of the front metal layer, and the resistance of the diffusion layer is between that of metal and monocrystalline silicon.
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to cover all such modifications and variations, and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, such as combining technical features of the embodiments, or directly or indirectly using the embodiments in other related technical fields, are included in the scope of the patent protection of the present application.
In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. In addition, the present application may use the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. In this application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims (15)

1. A trench gate power device, comprising: device body, front side metal layer, metalized drain and a plurality of trench gates, wherein:
the top end of the device main body covers the front metal layer, the front metal layer comprises a metal grid electrode and a metal source electrode, the bottom end of the device main body is connected with the metallized drain electrode, a plurality of grid grooves are concavely arranged at the top end of the device main body, a semiconductor platform area is arranged in an area between every two adjacent grid grooves, and the semiconductor platform area is connected with the metal source electrode;
each trench gate comprises a gate dielectric layer and a gate conducting layer, the gate conducting layer is positioned in the gate trench, the top of the gate conducting layer is lower than the upper surface of the semiconductor platform region, a dielectric groove is formed in the portion, higher than the gate conducting layer, of the gate trench, and the gate dielectric layer is filled in a gap between the gate trench and the gate conducting layer;
the top of the gate conducting layer is covered with a first medium, the first medium is connected with the metal gate, and a diffusion layer is formed at the joint of the first medium and the gate conducting layer.
2. The trench-gate power device of claim 1 wherein a blocking void is formed between the first dielectric and the dielectric trench sidewalls.
3. The trench-gate power device of claim 1 wherein the device body is divided into the semiconductor mesa region, the first conductivity type channel region, the second conductivity type drift region, and the semiconductor substrate in that order from top to bottom.
4. The trench-gate power device of claim 3, wherein the semiconductor mesa region comprises a plurality of first heavily doped half regions and a plurality of second heavily doped half regions, one of the first heavily doped half regions is disposed on each side of the gate trench, and each of the second heavily doped half regions is located between two corresponding adjacent first heavily doped half regions.
5. The trench-gate power device of claim 3 wherein said first conductivity type is P-type and said second conductivity type is N-type; or, the first conductivity type is N type, and the second conductivity type is P type.
6. The trench-gate power device of claim 1 wherein said first dielectric further covers said semiconductor mesa region.
7. The trench-gate power device of claim 1 wherein the gate dielectric layer is a gate oxide layer and the gate conductive layer is a polysilicon gate.
8. The method for manufacturing the silicide gate of the trench gate power device is characterized by comprising the following steps of:
s1, carrying out self-aligned back etching on a gate conducting layer, back etching the top surface of the gate conducting layer in a gate groove to be lower than a first surface and forming a medium groove, wherein the medium groove has a first depth;
s2, depositing an intermediate medium in the medium groove, and carrying out back etching to enable the side wall of the medium groove to form a side wall composed of the intermediate medium, wherein the side wall has a first thickness;
s3, depositing a first medium on the first surface side, enabling the first medium to be combined with the gate conducting layer at the bottom of the side wall, and forming a diffusion layer at the combination position, wherein the first medium has a second thickness;
and S4, removing the side wall through etching to form a partition gap.
9. The method for fabricating a silicide gate of a trench-gate power device of claim 8, wherein the semiconductor mesa region of the trench-gate power device is a silicon substrate, and step S3 further comprises: the first medium is also deposited on the semiconductor platform region.
10. The method of fabricating a silicide gate of a trench gate power device of claim 9, wherein the trench gate power device is an IGBT device, the method of fabricating a silicide gate of a trench gate power device further comprising the steps of:
s5, removing the first medium deposited on the surface of the semiconductor platform region through photoetching.
11. The method of fabricating a silicide gate of a trench-gate power device of claim 8, wherein the first depth is 0.20 μm to 0.30 μm.
12. The method of claim 8, wherein the sidewall is made of silicon nitride or silicon dioxide, and the first thickness is
Figure FDA0003397545970000021
Figure FDA0003397545970000022
13. The method of fabricating a silicide gate of a trench-gate power device of claim 8, wherein said first dielectric is metal and said second thickness is
Figure FDA0003397545970000023
14. The method of fabricating a silicide gate of a trench-gate power device of claim 8, wherein the first medium and the gate conductive layer are combined at a reaction temperature of 800 ℃ to 1000 ℃ for a reaction time period of 25 to 35 minutes.
15. The method of claim 8, wherein the first medium and the gate conductive layer are combined by rapid thermal annealing at 700-950 ℃ for 25-35 seconds.
CN202111485978.8A 2021-12-07 2021-12-07 Trench gate power device and silicide gate manufacturing method Pending CN116247084A (en)

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