CN116247071A - Semiconductor device integrating photoelectric device and electronic device and integration method thereof - Google Patents

Semiconductor device integrating photoelectric device and electronic device and integration method thereof Download PDF

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CN116247071A
CN116247071A CN202310354997.XA CN202310354997A CN116247071A CN 116247071 A CN116247071 A CN 116247071A CN 202310354997 A CN202310354997 A CN 202310354997A CN 116247071 A CN116247071 A CN 116247071A
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electrode
device structure
semiconductor layer
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layer
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王国斌
王阳
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Jiangsu Third Generation Semiconductor Research Institute Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract

The invention discloses a semiconductor device integrating a photoelectric device and an electronic device and an integration method thereof. The integration method comprises the following steps: manufacturing a photoelectric device structure on a first polar surface of the GaN single crystal substrate, manufacturing an electronic device structure on a second polar surface of the GaN single crystal substrate, and electrically connecting the electronic device structure with at least one electrode of the photoelectric device structure, or wherein at least one electrode of the photoelectric device structure comprises the electronic device structure; one of the first polar surface and the second polar surface is a Ga polar surface, and the other is an N polar surface. The photoelectric device structure and the electronic device structure are integrated on different polar surfaces of the GaN single crystal substrate, the side wall damage of the photoelectric device structure can be overcome, the efficiency is improved, the integrated control is directly carried out without huge transfer, and the whole volume is smaller.

Description

Semiconductor device integrating photoelectric device and electronic device and integration method thereof
Technical Field
The invention particularly relates to a semiconductor device integrating a photoelectric device and an electronic device and an integration method thereof, belonging to the technical field of semiconductor devices.
Background
The third generation semiconductor represented by GaN has a large forbidden bandwidth and breakdown voltage, and has the advantages of high chemical stability, high temperature resistance, corrosion resistance and the like, and is expected to be a key strategic material for the development of the next generation semiconductor industry in photoelectric devices and high-frequency high-power electronic devices.
Homogeneous epitaxial Light Emitting Diodes (LEDs) are considered as next generation LED technology because their ultra-high crystal quality can maximally suppress the occurrence of non-radiative recombination. However, since homoepitaxy is mostly planar, the brightness of the emitted light is sometimes even inferior to that of a patterned heteroepitaxial LED. Secondly, homoepitaxy has the characteristics of double-sided GaN, which is commonly used to develop chip structures of vertical structure.
The currently viewed GaN-based Micro-LEDs have not been industrialized yet due to two major problems. Firstly, the miniaturization of the size causes the rapid reduction of efficiency, and secondly, the huge amount of chips are difficult to transfer and the integrated control of forming an array. The two problems cannot be avoided in the conventional method generally, because most of epitaxial structures of GaN-based Micro-LEDs are in a two-dimensional planar laminated growth mode, and the etching process of small-size chips can cause side wall damage of an active area, and the Micro-LEDs are very sensitive to the side wall damage, so that efficiency is reduced. And because the chip size is smaller, the chip is limited by the size of an electrode and the like during integration, and meanwhile, the Micro-LED array system driven by the traditional Si-based complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) is complicated in+ division, and parasitic resistance, capacitance and inductance caused by interconnection of components reduce the performance of the device.
Disclosure of Invention
The invention mainly aims to provide a semiconductor device for integrating an optoelectronic device and an electronic device and an integration method thereof, thereby overcoming the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
in one aspect, the present invention provides a method for integrating an optoelectronic device and an electronic device, including:
manufacturing an optoelectronic device structure on a first polar surface of a GaN single crystal substrate, manufacturing an electronic device structure on a second polar surface of the GaN single crystal substrate, and electrically connecting the electronic device structure with at least one electrode of the optoelectronic device structure, or wherein at least one electrode of the optoelectronic device structure comprises the electronic device structure; wherein one of the first polar surface and the second polar surface is a Ga polar surface, and the other is an N polar surface.
Further, the GaN single crystal substrate is an N-type GaN single crystal substrate.
Further, the optoelectronic device structure includes an LED device structure, and the integration method specifically includes:
manufacturing at least one micro-nano scale column on the first polar surface to form a first semiconductor layer;
manufacturing a wrapping layer wrapping the column body on the column body, wherein the wrapping layer comprises an active layer and a second semiconductor layer which are sequentially stacked, so that a first epitaxial structure is formed;
and manufacturing a first electrode and a second electrode matched with the first epitaxial structure, and enabling the first electrode to be electrically connected with the first semiconductor layer, and enabling the second electrode to be electrically connected with the second semiconductor layer, so that the LED device structure is formed, wherein one of the first electrode and the second electrode is electrically connected with the electronic device structure, or one of the first electrode and the second electrode comprises the electronic device structure.
Further, the LED device structure can be a Micro-LED, mini-LED or a conventional sized LED chip structure.
Further, the integration method specifically includes: and manufacturing a plurality of columns on the first polar surface of the GaN single crystal substrate, manufacturing a wrapping layer wrapping the columns on each column, and arranging two adjacent wrapping layers at intervals so as to form a plurality of first epitaxial structures.
Further, one of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer, and the other is an n-type semiconductor layer; one of the first electrode and the second electrode is a p electrode, and the other electrode is an n electrode; the electronic device structure is electrically connected with at least one n-electrode of the LED device structure, or the at least one n-electrode of the LED device structure comprises the electronic device structure.
Further, the GaN single crystal substrate includes a first polar portion having a first polar face, and the integration method specifically includes: and etching the first polar part to form the column body integrated with the GaN single crystal substrate, wherein the first semiconductor layer is an n-type semiconductor layer.
Further, the column extends in a direction forming an angle of 0to 180 ° with the first polar surface.
Further, the radial dimension of the cylinder is 0.1-50 μm.
Further, the axial dimension of the column is 1-10 μm.
Further, the distance between two adjacent columns is 10-100 μm.
Further, the integration method specifically includes: and growing a III-nitride material on the pillars, thereby forming the cladding layer.
Further, the integration method specifically includes: and placing the GaN single crystal substrate forming the column in a reaction cavity, growing the active layer on the column under a first growth condition and growing the second semiconductor layer on the active layer under a second growth condition, wherein the first growth condition comprises that the growth pressure in the reaction cavity is 50-200torr, the growth temperature is 700-800 ℃, the V/III ratio of the growth raw materials is 1000-10000, and the second growth condition comprises that the growth pressure in the reaction cavity is 50-200torr, the growth temperature is 900-1050 ℃, and the V/III ratio of the growth raw materials is 1000-10000.
Further, the integration method further comprises: forming at least one isolation layer on the GaN single crystal substrate, and forming the wrapping layer on the column body; each isolation layer is arranged around one column body, the height of each isolation layer is smaller than that of each column body, and the second electrode and the GaN single crystal substrate are electrically isolated by the isolation layers.
Further, the isolation layer comprises SiO 2 /Si 3 N 4 The height of the isolation layer is 0.1-1 μm.
Further, the GaN single crystal substrate includes a second polar portion having a second polar face, and the integration method specifically includes: and etching the second polar part to form a groove-shaped structure, and manufacturing the electronic device structure in the groove-shaped structure.
Further, the second polar part includes a first region and a second region disposed around the first region, and the integration method specifically includes: the groove-shaped structure is formed in the first area.
Further, the depth of the groove-like structure is 0.1-5 μm.
Further, the electronic device structure includes a transistor device structure, such as: HEMT device structure, MOS device structure, or field effect transistor (Field Effect Transistor, FET) device structure.
Further, the transistor device structure is a HEMT device structure, and the integration method specifically includes:
sequentially manufacturing a third semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer which are stacked on the bottom of the groove-shaped structure, wherein a carrier channel is formed between the third semiconductor layer and the fourth semiconductor layer, so that a second epitaxial structure is formed;
and manufacturing a source electrode, a drain electrode and a grid electrode matched with the second epitaxial structure, so as to form the HEMT device structure.
Further, a carrier channel in the HEMT device structure is located in the groove-shaped structure.
Further, the integration method further comprises: and forming a passivation layer on the second epitaxial structure, wherein the passivation layer is disposed between any two of the source electrode, the drain electrode and the gate electrode.
In another aspect, the present invention provides a semiconductor device integrating an optoelectronic device and an electronic device, including:
a GaN single crystal substrate having a first polar face and a second polar face, one of the first polar face and the second polar face being a Ga polar face and the other being an N polar face;
the photoelectric device structure is arranged on the first polar surface;
and the electronic device structure is arranged on the second polar surface and is electrically connected with at least one electrode of the photoelectric device structure, or the at least one electrode of the photoelectric device structure comprises the electronic device structure.
Further, the optoelectronic device structure includes an LED device structure, which may be a Micro-LED, mini-LED, or a conventional sized LED chip structure.
Further, the LED device structure comprises a first epitaxial structure, a first electrode and a second electrode matched with the first epitaxial structure, the first epitaxial structure comprises a first semiconductor layer and a wrapping layer, the first semiconductor layer comprises at least one micro-nano cylinder, the wrapping layer wraps the cylinder, the first semiconductor layer comprises a micro-nano cylinder arranged on the first polar surface, the wrapping layer comprises an active layer and a second semiconductor layer which are sequentially stacked, the first electrode is electrically connected with the first semiconductor layer, the second electrode is electrically connected with the second semiconductor layer,
wherein one of the first and second electrodes is electrically connected with the electronic device structure, or one of the first and second electrodes comprises the electronic device structure.
Further, the LED device structure comprises a plurality of first epitaxial structures, and the first epitaxial structures are arranged at intervals.
Further, an isolation layer is further arranged on the GaN single crystal substrate, the isolation layer is arranged between the second electrode and the GaN single crystal substrate, the isolation layer surrounds the first semiconductor layer and the active layer, and the height of the isolation layer is smaller than that of the column body.
Further, the isolation layer comprises SiO 2 /Si 3 N 4 The height of the isolation layer is 0.1-1 μm.
Further, the column extends in a direction forming an angle of 0to 180 ° with the first polar surface.
Further, the radial dimension of the cylinder is 0.1-50 μm.
Further, the axial dimension of the column is 1-10 μm.
Further, the distance between two adjacent columns is 10-100 μm.
Further, one of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer, and the other is an n-type semiconductor layer; one of the first electrode and the second electrode is a p electrode, and the other electrode is an n electrode; the electronic device structure is electrically connected to at least one n-electrode of the optoelectronic device structure, or the at least one n-electrode of the optoelectronic device structure comprises the electronic device structure.
Further, the column is integrally provided with the GaN single crystal substrate.
Further, the GaN single crystal substrate comprises a first polar part, the first polar part is provided with the first polar surface, and the column body and the first polar part are integrally arranged.
Further, the material of the wrapping layer comprises a III-nitride material.
Further, the second polar surface of the GaN single crystal substrate is provided with a groove-like structure, and at least a part of the electronic device structure is disposed in the groove-like structure.
Further, the GaN single crystal substrate includes a second polarity portion having a second polarity face, and the trench structure is disposed within the second polarity portion.
Further, the second polar portion includes a first region and a second region disposed around the first region, and the groove-like structure is disposed in the first region.
Further, the depth of the groove-like structure is 0.1-5 μm.
Further, the electronic device structure includes a transistor device structure, such as a HEMT device structure, a MOS device structure, or a FET device structure.
Further, the electronic device structure includes a HEMT device structure.
Further, the HEMT device structure comprises a second epitaxial structure, and a source electrode, a drain electrode and a gate electrode which are matched with the second epitaxial structure, wherein the second epitaxial structure comprises a third semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer which are sequentially stacked on the GaN single crystal substrate, a carrier channel is formed between the third semiconductor layer and the fourth semiconductor layer, and the source electrode and the drain electrode are electrically connected through the carrier channel.
Further, a carrier channel in the HEMT device structure is located in the groove-shaped structure.
Further, a passivation layer is further disposed between any two of the source electrode, the drain electrode and the gate electrode.
Compared with the prior art, the invention has the advantages that:
the invention provides a manufacturing method of a semiconductor device integrating a photoelectric device and an electronic device, which comprises the steps of manufacturing a photoelectric device structure on a first polar surface (one of a Ga polar surface and an N polar surface) of a GaN single crystal substrate, manufacturing an electronic device structure on a second polar surface (the other of the Ga polar surface and the N polar surface) of the GaN single crystal substrate, and electrically connecting the electronic device structure with at least one electrode of the photoelectric device structure, or wherein at least one electrode of the photoelectric device structure comprises the electronic device structure; by integrating the photoelectric device structure and the electronic device structure on different polar surfaces of the front surface and the back surface of the GaN monocrystal substrate and utilizing the advantages of the photoelectric device structure and the electronic device structure, the side wall damage of the photoelectric device structure is avoided, and therefore the efficiency of the photoelectric device is improved; and the photoelectric device is directly integrated and controlled by utilizing the electronic device without carrying out mass transfer treatment on the photoelectric device, so that the whole volume is reduced, and the miniaturization design is facilitated.
Drawings
Fig. 1 is a schematic structural view of a semiconductor device integrating Micro-LEDs and HEMTs provided in an exemplary embodiment of the present invention;
FIG. 2 is a schematic view of a GaN single crystal substrate according to the present invention;
FIG. 3 is a schematic view of the structure after processing to form a plurality of pillars on the first polar surface of the GaN single crystal substrate;
FIG. 4 is a schematic diagram of the structure after formation of the active region and isolation layer;
FIG. 5 is a schematic diagram of the structure after formation of a p-type layer;
fig. 6 is a schematic view of the structure after formation of the p-electrode;
FIG. 7 is a schematic diagram of the structure after processing the second polar surface of the GaN single crystal substrate to form a trench structure and a tunnel layer;
FIG. 8 is a schematic diagram of the structure after formation of a barrier layer;
FIG. 9 is a schematic diagram of the structure after formation of the cap layer;
fig. 10 is a schematic diagram of the structure after forming the source, drain and gate electrodes.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical solution, implementation process and principle thereof will be further explained with reference to the drawings and specific embodiments, and unless otherwise indicated, semiconductor epitaxial growth apparatuses, etching apparatuses, metal vapor deposition apparatuses and the like used in the embodiments of the present invention may be known to those skilled in the art, and are not specifically limited herein.
Aiming at the problems in the prior art, the invention provides an integrated device based on a GaN single crystal substrate and considering both a Ga-face photoelectric device structure and an N-face electronic device structure and a monolithic integration method thereof from a general material platform. The gallium nitride homogeneous photoelectric integrated control system is formed by carrying out epitaxial structure growth of a wrapped three-dimensional photoelectric device and evaporation of a transparent electrode on the Ga surface of a GaN single crystal substrate to form a photoelectric device structure, and carrying out growth of an electronic device epitaxial structure and gate, drain and source electrode manufacture on the N surface of the GaN single crystal substrate to obtain an electronic device structure, and electrically connecting the electronic device structure with at least one electrode of the photoelectric device, or using the electronic device structure as at least one electrode of the photoelectric device.
The implementation process, principle and the like of the technical scheme of the invention will be further explained by taking a semiconductor device integrating Micro-LEDs and HEMTs as an example and an integration method thereof.
In a more typical embodiment, referring to fig. 1, a semiconductor device (or may be referred to as a Micro-LED array chip) monolithically integrating Micro-LEDs and HEMTs includes an n-type GaN single crystal substrate 100, and a HEMT device structure and a plurality of Micro-LED device structures disposed on the n-type GaN single crystal substrate 100, the HEMT device structure serving as a common electrode for the plurality of Micro-LED device structures.
The plurality of Micro-LED device structures are grown in situ on a first polarity side of the n-type GaN single crystal substrate 100, and the HEMT device structures are grown in situ on a second polarity side of the n-type GaN single crystal substrate 100. Specifically, one of the first polar surface and the second polar surface is a Ga polar surface (may be simply referred to as a Ga surface), and the other is an N polar surface (may be simply referred to as an N surface); namely, a plurality of Micro-LED device structures are grown on the Ga surface of the N-type GaN single crystal substrate 100 in situ, and HEMT device structures are grown on the N surface of the N-type GaN single crystal substrate 100 in situ; alternatively, a plurality of Micro-LED device structures are grown in-situ on the N-face of the N-type GaN single crystal substrate 100, and HEMT device structures are grown in-situ on the Ga-face of the N-type GaN single crystal substrate 100.
In a specific embodiment, each Micro-LED device structure includes a Micro-LED epitaxial structure (i.e., the aforementioned first epitaxial structure) 210 and a p-electrode 220 that mates with the Micro-LED epitaxial structure 210, with the hemt device structure acting as an n-electrode that mates with the Micro-LED epitaxial structure 210.
The Micro-LED epitaxial structure 210 includes an n-type semiconductor layer 211, an active layer 212 and a p-type semiconductor layer 213 sequentially disposed, the active layer 212 wraps the n-type semiconductor layer 211, the p-type semiconductor layer 213 wraps the active layer 212, the p-electrode 220 is electrically connected with the p-type semiconductor layer 213, and the n-electrode is electrically connected with the n-type semiconductor layer 211.
Specifically, the n-type semiconductor layer 211 is a micro-nano-scale pillar provided on the first polar surface of the n-type GaN single crystal substrate 100 and integrally provided with the n-type GaN single crystal substrate 100, and the active layer 212 and the p-type semiconductor layer 213 are sequentially stacked on the pillar in a three-dimensional package.
Specifically, the GaN single crystal substrate 100 includes a first polar portion having a first polar surface and a second polar portion having a second polar surface, which are sequentially arranged, and the pillars are formed by etching the first polar portion.
Specifically, the columns extend in a direction forming an angle of 0to 180 ° with the first polar plane, for example, the columns may extend in a direction forming an angle of 90 ° with the first polar plane, i.e., the columns are perpendicular to the first polar plane, wherein a radial dimension (the radial dimension may be a diameter, a width or a length of a radial section of the columns) a of the columns is 0.1 to 50 μm, an axial dimension (the axial dimension may be a height of the columns or a length of the columns in an axial direction) d of the columns is 1 to 10 μm, and a distance b between two adjacent columns is 10 to 100 μm.
Specifically, the active layer 212 may be an InGaN/GaN quantum well structure, and the p-type semiconductor layer 213 may be p-type GaN.
Specifically, the n-type GaN single crystal substrate 100 is further provided with a plurality of spacers 400, each spacer 400 is disposed around a column, the p-type semiconductor layer 213 is electrically isolated from the n-type GaN single crystal substrate 100 by the spacers 400, and exemplary materials of the spacers 400 include SiO 2 Or Si (or) 3 N 4 The thickness of the spacer 400 is 0.1-1 μm.
Specifically, the p-electrode 220 may be an Indium Tin Oxide (ITO) transparent electrode.
Specifically, the HEMT device structure includes a HEMT epitaxial structure (i.e., the aforementioned second epitaxial structure) 310, and a source 320, a drain 330, and a gate 340 that are mated to the HEMT epitaxial structure 310, the HEMT epitaxial structure 310 being disposed on the second polarity side of the n-type GaN single crystal substrate 100.
Specifically, the HEMT epitaxial structure 310 includes a tunnel layer (i.e., the aforementioned third semiconductor layer) 311, a barrier layer (i.e., the aforementioned fourth semiconductor layer) 312, and a cap layer (i.e., the aforementioned fifth semiconductor layer) 313, which are sequentially stacked on the n-type GaN single crystal substrate 100, a source electrode 320 and a drain electrode 330 are disposed on the cap layer 313, and a gate electrode 340 is disposed on the barrier layer 312.
Specifically, the cap layer 313 is further provided with a passivation layer 600, and the passivation layer 600 is disposed between the source electrode 320, the drain electrode 330 and the gate electrode 340; illustratively, the passivation layer 600 may be made of silicon oxide or the like.
Specifically, the second polar surface of the n-type GaN single crystal substrate 100 is further provided with a trench structure, the HEMT epitaxial structure 310 is disposed in the trench structure, and the carrier channel in the HEMT epitaxial structure 310 is disposed in the trench structure.
Specifically, the groove-like structure is provided at the second polar portion of the n-type GaN single crystal substrate 100, and the depth of the groove-like structure is 0.1-5 μm.
In a more typical embodiment, referring to fig. 2-10, a method for monolithically integrating Micro-LEDs and HEMTs based on GaN single crystal substrates is provided in this example, which may include the following steps:
1) An n-type GaN single crystal substrate 100 is provided.
As shown in fig. 2, the N-type GaN single crystal substrate 100 includes a first polar portion and a second polar portion arranged in this order, the first polar portion having a first polar surface and the second polar portion having a second polar surface, one of the first polar surface and the second polar surface being a Ga polar surface and the other being an N polar surface; it will be appreciated that the Ga-polar and N-polar faces are disposed opposite.
2) The first polar portion is etched from the first polar surface of the n-type GaN single crystal substrate 100to form a plurality of Micro-nano scale pillars distributed at intervals, and the pillars are used as the n-type semiconductor layer 211 of the Micro-LED device structure, as shown in fig. 3.
The pillars extend in a direction at an angle of 0to 180 ° to the first polar plane, for example, the pillars may extend in a direction at an angle of 90 ° to the first polar plane, i.e., the pillars are perpendicular to the first polar plane, wherein a radial dimension (the radial dimension may be a diameter, a width or a length of a radial cross section of the pillars) a of the pillars is 0.1 to 50 μm, an axial dimension (the axial dimension may be a height of the pillars or a length of the pillars in the axial direction) d of the pillars is 1 to 10 μm, and a spacing b between adjacent pillars is 10 to 100 μm.
3) An isolation layer 400 is formed on the first polar surface of the n-type GaN single crystal substrate 100 such that the isolation layer 400 is distributed around the plurality of pillars as shown in fig. 4.
The material of the isolation layer 400 includes SiO 2 Or Si (or) 3 N 4 The thickness of the spacer 400 is 0.1-1 μm.
4) Placing an n-type GaN single crystal substrate 100 having a plurality of columns in a reaction chamber (which may be a reaction chamber of a chemical vapor deposition apparatus), setting a growth pressure in the reaction chamber to 50-200torr, a growth temperature to 700-800 ℃, and setting a V/III ratio (V-III ratio is a molar ratio of a V group element to a III group element) of a growth raw material to 1000-10000 to grow an active layer 212 forming a three-dimensional packed column on the columns, as shown in FIG. 4; the growth pressure in the reaction chamber is set to 50-200torr, the growth temperature is set to 900-1050 deg.c, and the V/III ratio of the growth raw material is set to 1000-10000 to form p-type semiconductor layers 213 by layer-by-layer growth on the active layer 212, thereby forming a plurality of Micro-LED epitaxial structures 210, as shown in fig. 5.
The active layer 212 and the p-type semiconductor layer 213 have a three-dimensional wrapping shape, the active layer 212 wraps the n-type semiconductor layer 211, the p-type semiconductor layer 213 wraps the active layer 212, and the p-type semiconductor layer 213 and the n-type GaN single crystal substrate 100 are electrically isolated by the isolation layer 400.
Specifically, the active layer 212 may be an InGaN/GaN quantum well structure, and the p-type semiconductor layer 213 may be p-type GaN.
5) P-electrodes 220 are formed on the surfaces of the Micro-LED epitaxial structures 210, the p-electrodes 220 are electrically connected with the p-type semiconductor layers 213, and the p-electrodes 220 are electrically isolated from the n-type GaN single crystal substrate 100 by isolation layers, so that a Micro-LED array is formed, as shown in fig. 6.
The p-electrode 220 may be an ITO transparent electrode.
6) The grown epitaxial wafer is inverted and etched on the second polar surface of the n-type GaN single crystal substrate 100to form a trench structure 110, as shown in fig. 7.
A silicon oxide or silicon nitride mask 500 may be first provided on a second region of the second polar surface of the n-type GaN single crystal substrate 100 and the first region of the second polar surface may be etched to form the trench structure 110.
In particular, the second region is arranged around the first region, i.e. the second region can be understood as an edge region, the groove-like structure 110 having a depth of 0.1-5 μm.
7) A tunnel layer 311, a barrier layer 312, and a cap layer 313 are sequentially formed on the bottom of the trench 110, thereby forming a HEMT epitaxial structure 310, as shown in fig. 7, 8, and 9.
The tunnel layer 311 may be a GaN layer, the barrier layer 312 may be an AlGaN layer, and the cap layer 313 may be a GaN layer.
8) The source 320, drain 330, and gate 340 are fabricated in cooperation with the HEMT epitaxial structure 310 to form a HEMT device structure, as shown in fig. 10.
It will be appreciated that in other embodiments, the passivation layer 600 may also be formed on the cap layer 313 with the passivation layer 600 disposed between any two of the drain electrode 330, the gate electrode 340, and the source electrode 320; in addition, the silicon oxide or silicon nitride mask 500 may also be removed.
The invention utilizes the switching performance of the HEMT to realize the control of the quick on-off response of the Micro-LED above the HEMT, and satisfies the display application, specifically, the two-dimensional electron gas positioned on the barrier layer can be formed through the control of the grid electrode, the drain electrode and the source electrode, whether the two-dimensional electron gas is generated or not can be directly controlled through the n-type GaN monocrystal substrate to realize the quick on-off control of electrons, thereby realizing the effective control of the on-off of the whole Micro-LED array; in addition, the contact resistance between the GaN cap layer growing on the N surface and the source electrode, the drain electrode and the grid electrode is lower, and the surface state between the GaN cap layer and the passivation layer can be improved, so that the occurrence probability of the leakage problem is reduced; in addition, compared with a heterogeneous growth scheme, the homoepitaxy adopted by the invention can obtain a high-quality single-polarity N-face GaN material, and the N-face GaN material also has higher transconductance and can support better high-frequency characteristics.
Example 1
The Micro-LED and HEMT monolithic integration method based on the GaN single crystal substrate provided by the embodiment comprises the following steps:
1) And (3) performing in-situ etching on the Ga surface of the Si-doped n-type GaN single crystal substrate by adopting an ICP (Inductive Coupled Plasma) etching process, so that a plurality of micro-nano scale columns are formed on the Ga surface at intervals, and the columns are used as an n-type semiconductor layer.
Each pillar has a diameter a=2 μm, a pillar height d=5 μm, and a pitch b=10 μm between adjacent pillars.
2) Protecting the column with mask, placing the n-type GaN monocrystal substrate covered by the mask in the reaction chamber of plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) equipment, and depositing SiO with thickness of 200nm on the etched surface of the n-type GaN monocrystal substrate 2 As an isolation layer, and the isolation layer is disposed around the column.
3) Removing the mask, setting the growth pressure In the reaction cavity to 100torr, setting the growth temperature to 750 ℃, introducing the growth raw material into the reaction cavity, setting the V/III ratio In the growth raw material to 5000, and thereby growing In which wraps the column on the surface of each column 0.15 A GaN/GaN quantum well structure; setting the growth pressure In the reaction cavity to be 100torr, setting the growth temperature to be 1000 ℃, introducing the growth raw material into the reaction cavity, and setting the V/III ratio In the growth raw material to be 5000, thereby obtaining the growth target material with the following characteristics of In 0.15 The GaN/GaN quantum well structure surface grows to form a p-type GaN layer, in 0.15 The GaN/GaN quantum well structure has a thickness of 75nm and 5 pairs, and the p-type GaN layer has a thickness of 100nm, so that a plurality of Micro-LED epitaxial structures are obtained.
4) And forming an ITO electrode on the surface of the Micro-LED epitaxial structure by vapor deposition, wherein the ITO electrode is electrically connected with the p-type GaN layer, so that the Micro-LED array is obtained.
5) Inverting the obtained epitaxial wafer, and depositing SiO in the edge area of the N face of the N-type GaN single crystal substrate 2 And protecting the mask, and then carrying out in-situ etching on the area which is not covered by the mask, wherein the etching depth is 1 mu m, so that a groove-shaped structure is formed.
6) C-doped GaN tunnel layer growth is carried out at the bottom of the groove-shaped structure, and the thickness of the GaN tunnel layer is controlled to be 300nm; then growing an AlGaN barrier layer with the thickness of 20nm on the GaN tunnel layer, wherein the Al component content is 25 at%; and finally, growing a GaN cap layer with the thickness of 2nm on the AlGaN barrier layer, thereby obtaining the HEMT epitaxial structure.
7) Manufacturing a source electrode, a drain electrode and a grid electrode which are matched with the HEMT epitaxial structure; and manufacturing a passivation layer among the source electrode, the drain electrode and the grid electrode, so as to form a HEMT device structure, and finally obtaining the semiconductor device of the monolithically integrated Micro-LED and HEMT.
According to the embodiment, the GaN-based LED and the HEMT are integrated on the two polarized surfaces of the same GaN single crystal substrate, the advantage of controllable three-dimensional growth of the Ga surface is utilized to carry out wrapped LED patterning and in-situ growth of the array chip, the side wall damage caused by later etching is avoided, and the efficiency of the Micro-LED is improved; in addition, the structure of the HEMT device is grown on the N surface of the GaN single crystal substrate, so that the contact resistance between the GaN cap layer and the source electrode, the drain electrode and the grid electrode is reduced, the surface state between the GaN cap layer and the passivation layer is improved, the generation of electric leakage is avoided, the surface property of the N-surface GaN material is more active, the response is faster, the N-surface GaN material also has higher transconductance, better high-frequency characteristics can be supported, the advantages of long service life, low electric leakage, high controlled responsiveness and the like of the GaN-based LED and the Micro-LED array chip are fully exerted, and the GaN-based LED can be applied to the fields of Micro display, visible light communication and the like.
The monolithically integrated semiconductor device array chip of Micro-LED and HEMT obtained in example 1 was named sample a.
Comparative example 1
The array chip obtained by the general method of growing etching on the sapphire Ga plane as an electrode by the method disclosed in CN109841710a was designated as sample B.
The monolithically integrated Micro-LED and HEMT semiconductor device obtained in example 1 was tested with the Micro-LED array chip in comparative example 1, and the test results are shown in table 1.
Table 1 shows the results of the test characterization of the devices of example 1 and comparative example 1
Figure BDA0004163085680000121
Where PPI is the number of Pixels Per Inch (Pixels Per Inch).
As can be seen from table 1, the sample a obtained in the embodiment 1 of the present invention has higher light-emitting brightness, and a very high chip lighting rate, so that higher pixel resolution is achieved, and because the HEMT fabricated on the N-polar surface performs overall high-speed switching control on the N-electrode, the response speed of ns level is achieved. The chip size of the sample wafer B obtained in comparative example 1 is smaller, the etching process of the small-size chip causes damage to the side wall of the active region, the Micro-LED is very sensitive to the damage, the damage to the side wall of the Micro-LED easily causes rapid reduction of brightness, and the N electrode and the P electrode are arranged on the same side, so that the lighting rate of the whole array chip is less than half due to the limitation of the electrode size and the like during integration, the low pixel resolution is directly caused, and the response speed is two orders of magnitude higher than that of the sample a due to the integration without the high mobility field effect transistor.
Example 2
Example 2 is substantially the same as example 1 except that: embodiment 2 is a Micro-LED array formed on the N-side of an N-type GaN single crystal substrate, while a HEMT device structure is formed on the Ga-side of the N-type GaN single crystal substrate. The monolithically integrated Micro-LED and HEMT semiconductor device obtained in example 2 was designated as sample C.
The monolithically integrated Micro-LED and HEMT semiconductor devices obtained in example 1 and example 2 were tested, and the test results are shown in table 2.
Table 2 shows the test characterization results for the devices of example 1 and example 2
Figure BDA0004163085680000131
As can be seen from table 2, the brightness and resolution of sample a obtained in example 1 are higher; while sample C obtained in example 2 was an N-sided grown Micro-LED light emitting structure with a light emitting luminance slightly lower than the lighting rate of the chip array, but could be made in a long wavelength band.
The photoelectric device structure and the electronic device structure are integrated on different polar surfaces of the GaN single crystal substrate, the side wall damage of the photoelectric device structure can be overcome, the efficiency is improved, the integrated control is directly carried out without huge transfer, and the whole volume is smaller.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.

Claims (10)

1. A method of integrating an optoelectronic device and an electronic device, comprising:
manufacturing an optoelectronic device structure on a first polar surface of a GaN single crystal substrate, manufacturing an electronic device structure on a second polar surface of the GaN single crystal substrate, and electrically connecting the electronic device structure with at least one electrode of the optoelectronic device structure, or wherein at least one electrode of the optoelectronic device structure comprises the electronic device structure;
wherein one of the first polar surface and the second polar surface is a Ga polar surface, and the other is an N polar surface.
2. The method of integrating an optoelectronic device and an electronic device according to claim 1, wherein the optoelectronic device structure comprises an LED device structure, the method of integrating comprising:
manufacturing at least one micro-nano scale column on the first polar surface to form a first semiconductor layer;
manufacturing a wrapping layer wrapping the column body on the column body, wherein the wrapping layer comprises an active layer and a second semiconductor layer which are sequentially stacked, so that a first epitaxial structure is formed;
manufacturing a first electrode and a second electrode which are matched with the first epitaxial structure, and enabling the first electrode to be electrically connected with the first semiconductor layer, and enabling the second electrode to be electrically connected with the second semiconductor layer, so that the LED device structure is formed; wherein one of the first and second electrodes is electrically connected with the electronic device structure, or one of the first and second electrodes comprises the electronic device structure;
preferably, the integration method specifically includes:
forming a plurality of columns on a first polar surface of the GaN monocrystal substrate, forming a wrapping layer wrapping the columns on each column, and arranging two adjacent wrapping layers at intervals to form a plurality of first epitaxial structures;
preferably, one of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer, and the other is an n-type semiconductor layer; one of the first electrode and the second electrode is a p electrode, and the other electrode is an n electrode; the electronic device structure is electrically connected with at least one n-electrode of the LED device structure, or the at least one n-electrode of the LED device structure comprises the electronic device structure.
3. The method of integrating an optoelectronic device and an electronic device according to claim 2, wherein the GaN single crystal substrate comprises a first polar portion having a first polar face, the method comprising:
etching the first polar part to form the column body integrated with the GaN single crystal substrate, wherein the first semiconductor layer is an n-type semiconductor layer;
preferably, the column extends in a direction forming an angle of 0to 180 ° with the first polar plane;
preferably, the radial dimension of the cylinder is 0.1-50 μm;
preferably, the axial dimension of the column is 1-10 μm;
preferably, the spacing between two adjacent columns is 10-100 μm.
4. A method of integrating an optoelectronic device and an electronic device according to claim 2 or 3, characterized in that it comprises in particular: growing a group III nitride material on the pillars, thereby forming the cladding layer;
preferably, the integration method specifically includes:
and placing the GaN single crystal substrate forming the column in a reaction cavity, growing the active layer on the column under a first growth condition and growing the second semiconductor layer on the active layer under a second growth condition, wherein the first growth condition comprises that the growth pressure in the reaction cavity is 50-200torr, the growth temperature is 700-800 ℃, the V/III ratio of the growth raw materials is 1000-10000, and the second growth condition comprises that the growth pressure in the reaction cavity is 50-200torr, the growth temperature is 900-1050 ℃, and the V/III ratio of the growth raw materials is 1000-10000.
5. A method of integrating an optoelectronic device and an electronic device according to claim 2 or 3, wherein the method of integrating further comprises:
forming at least one isolation layer on the GaN single crystal substrate, and forming the wrapping layer on the column body; wherein each isolation layer is arranged around one column body, the height of each isolation layer is smaller than that of the column body, and the second electrode and the GaN single crystal substrate are electrically isolated by the isolation layers;
preferably, the material of the isolation layer comprises SiO 2 /Si 3 N 4 The height of the isolation layer is 0.1-1 μm.
6. The method of integrating an optoelectronic device and an electronic device according to claim 1, wherein the GaN single crystal substrate comprises a second polar portion having a second polar face, the method comprising:
etching the second polar part to form a groove-shaped structure, and manufacturing the electronic device structure in the groove-shaped structure;
preferably, the second polar part includes a first region and a second region disposed around the first region, and the integration method specifically includes: forming the groove-shaped structure in the first area;
preferably, the depth of the groove-like structure is 0.1-5 μm.
7. The method of integrating an optoelectronic device and an electronic device of claim 6, wherein the electronic device structure comprises a transistor device structure;
preferably, the transistor device structure is a HEMT device structure, and the integration method specifically includes:
sequentially manufacturing a third semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer which are stacked on the bottom of the groove-shaped structure, wherein a carrier channel is formed between the third semiconductor layer and the fourth semiconductor layer, so that a second epitaxial structure is formed;
manufacturing a source electrode, a drain electrode and a grid electrode which are matched with the second epitaxial structure, so as to form the HEMT device structure;
preferably, the integration method further comprises: and forming a passivation layer on the second epitaxial structure, wherein the passivation layer is disposed between any two of the source electrode, the drain electrode and the gate electrode.
8. A semiconductor device integrating an optoelectronic device and an electronic device, comprising:
a GaN single crystal substrate having a first polar face and a second polar face, one of the first polar face and the second polar face being a Ga polar face and the other being an N polar face;
the photoelectric device structure is arranged on the first polar surface;
and the electronic device structure is arranged on the second polar surface and is electrically connected with at least one electrode of the photoelectric device structure, or the at least one electrode of the photoelectric device structure comprises the electronic device structure.
9. The semiconductor device according to claim 8, wherein: the optoelectronic device structure comprises an LED device structure;
preferably, the LED device structure includes a first epitaxial structure, and a first electrode and a second electrode that are matched with the first epitaxial structure, where the first epitaxial structure includes a first semiconductor layer and a wrapping layer, the first semiconductor layer includes at least one micro-nano scale pillar, the wrapping layer wraps the pillar, the first semiconductor layer includes a micro-nano scale pillar disposed on the first polar plane, the wrapping layer includes an active layer and a second semiconductor layer that are sequentially stacked, the first electrode is electrically connected with the first semiconductor layer, and the second electrode is electrically connected with the second semiconductor layer, where one of the first electrode and the second electrode is electrically connected with the electronic device structure, or one of the first electrode and the second electrode includes the electronic device structure;
preferably, the LED device structure includes a plurality of first epitaxial structures, and the plurality of first epitaxial structures are arranged at intervals;
preferably, an isolation layer is further disposed on the GaN single crystal substrate, the isolation layer is disposed between the second electrode and the GaN single crystal substrate, the isolation layer is disposed around the first semiconductor layer and the active layer, and the height of the isolation layer is smaller than the height of the column;
preferably, the material of the isolation layer comprises SiO 2 /Si 3 N 4 The height of the isolation layer is 0.1-1 mu m;
preferably, the column extends in a direction forming an angle of 0to 180 ° with the first polar plane;
preferably, the radial dimension of the cylinder is 0.1-50 μm; preferably, the axial dimension of the column is 1-10 μm; preferably, the distance between two adjacent columns is 10-100 μm;
preferably, one of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer, and the other is an n-type semiconductor layer; one of the first electrode and the second electrode is a p electrode, and the other electrode is an n electrode; the electronic device structure is electrically connected with at least one n-electrode of the optoelectronic device structure, or the at least one n-electrode of the optoelectronic device structure comprises the electronic device structure;
preferably, the columns are integrally provided with the GaN single crystal substrate;
preferably, the GaN single crystal substrate includes a first polar portion having the first polar surface, the pillar being integrally provided with the first polar portion;
preferably, the material of the wrapping layer includes a group III nitride material.
10. The semiconductor device according to claim 8, wherein: the second polar surface of the GaN single crystal substrate is provided with a groove-shaped structure, and at least one part of the electronic device structure is arranged in the groove-shaped structure;
preferably, the GaN single crystal substrate includes a second polar portion having a second polar face, the groove-like structure being disposed within the second polar portion;
preferably, the second polar portion includes a first region and a second region disposed around the first region, the groove-like structure being disposed within the first region;
preferably, the depth of the groove-like structure is 0.1-5 μm;
preferably, the electronic device structure comprises a transistor device structure;
preferably, the electronic device structure includes a HEMT device structure;
preferably, the HEMT device structure comprises a second epitaxial structure, and a source electrode, a drain electrode and a gate electrode which are matched with the second epitaxial structure, wherein the second epitaxial structure comprises a third semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer which are sequentially stacked on the GaN single crystal substrate, a carrier channel is formed between the third semiconductor layer and the fourth semiconductor layer, and the source electrode and the drain electrode are electrically connected through the carrier channel;
preferably, a passivation layer is further disposed between any two of the source electrode, the drain electrode and the gate electrode.
CN202310354997.XA 2023-04-04 2023-04-04 Semiconductor device integrating photoelectric device and electronic device and integration method thereof Pending CN116247071A (en)

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