CN116247034A - Copper interconnection structure system, preparation method thereof and electronic component - Google Patents

Copper interconnection structure system, preparation method thereof and electronic component Download PDF

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Publication number
CN116247034A
CN116247034A CN202310358315.2A CN202310358315A CN116247034A CN 116247034 A CN116247034 A CN 116247034A CN 202310358315 A CN202310358315 A CN 202310358315A CN 116247034 A CN116247034 A CN 116247034A
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copper
alloy film
dielectric layer
based alloy
magnetron sputtering
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Inventor
林松盛
尹振东
唐鹏
苏一凡
张程
石倩
韦春贝
黄力为
代明江
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Institute of New Materials of Guangdong Academy of Sciences
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Institute of New Materials of Guangdong Academy of Sciences
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention discloses a copper interconnection structure system, a preparation method thereof and an electronic component, and belongs to the technical field of integrated circuit manufacturing and advanced packaging. The copper interconnection structure system comprises a dielectric layer arranged on the surface of a substrate and a copper-based alloy film arranged on the surface of the dielectric layer, wherein a diffusion barrier interconnection structure is formed between the copper-based alloy film and the dielectric layer; doping elements are doped in the copper-based alloy film; the doping element comprises metal and refractory metal which are easy to form an oxide self-passivation layer, and no intermetallic compound is formed between the doping element and copper; the doping amount of the doping element in the copper-based alloy film is 0.1-3 at%. The copper interconnection structure system has higher thermal stability and reliability, can keep lower film resistivity, is beneficial to reducing circuit power consumption, is beneficial to prolonging the service life of a circuit, and has important guiding significance for improving the performance of an integrated circuit.

Description

Copper interconnection structure system, preparation method thereof and electronic component
Technical Field
The invention relates to the technical field of integrated circuit manufacture and advanced packaging, in particular to a copper interconnection structure system, a preparation method thereof and an electronic component.
Background
At present, cu interconnect metal wires are widely used in the field of large-scale integrated circuit fabrication and advanced packaging technology because of their advantages of low resistivity, high thermal stability and high electromigration resistance, but have the problems of "three high and one low", i.e., high diffusivity, high reactivity, high corrosiveness and low adhesion, wherein the problem of high diffusivity affects the most.
Copper is extremely easy to be rapidly diffused into SiO in an ionic state at high temperature 2 Or Si inside, and react with the silicon substrate to form a high-resistance copper silicon compound (Cu 3 Si), which is liable to cause short circuit of the circuit, resulting in degradation of electronic components and reduction of the service life of the circuit. It is desirable to provide a diffusion barrier between copper and silicon substrates to block diffusion between copper and silicon.
As the technology nodes in the semiconductor industry shrink to the nanometer stage, moore's law goes to the limit, a thin barrier layer needs to be added to the copper thin film, namely the lower surface of the copper seed crystal layer, and the existence of the barrier layer not only increases the process steps, but also occupies the space of the copper interconnection, and increases the overall resistance of the copper interconnection.
In view of this, the present invention has been made.
Disclosure of Invention
It is an object of the present invention to provide a copper interconnect structure system that not only has high thermal stability and reliability, but also maintains low sheet resistivity.
The second objective of the present invention is to provide a method for preparing the copper interconnect structure system.
It is a further object of the present invention to provide an electronic component comprising the copper interconnect structure system.
The application can be realized as follows:
in a first aspect, the present application provides a copper interconnect structure comprising a dielectric layer disposed on a surface of a substrate and a copper-based alloy film disposed on a surface of the dielectric layer, wherein a diffusion barrier interconnect structure is formed between the copper-based alloy film and the dielectric layer;
doping elements are doped in the copper-based alloy film; the doping element comprises metal and refractory metal which are easy to form an oxide self-passivation layer, and no intermetallic compound is formed between the doping element and copper; the doping amount of the doping element in the copper-based alloy film is 0.1-3 at%.
In an alternative embodiment, the atomic ratio between the metal from which the oxide self-passivation layer is readily formed and the refractory metal is in the range of 1:1 to 1:2.
In an alternative embodiment, the metal susceptible to forming the oxide self-passivation layer includes at least one of Zr, ti, and V; and/or the refractory metal comprises at least one of Cr, mo, and W.
In an alternative embodiment, the copper-based alloy thin film has a thickness of 50-500nm.
In an alternative embodiment, the substrate comprises a single crystal Si substrate.
In an alternative embodiment, the dielectric layer comprises SiO 2 A dielectric layer.
In an alternative embodiment, the dielectric layer has a thickness of 10-200nm.
In a second aspect, the present application provides a method for preparing a copper interconnect structure system according to any one of the preceding embodiments, comprising the steps of: and arranging a copper-based alloy film on the surface of the dielectric layer.
In an alternative embodiment, a copper-based alloy film is prepared by magnetron sputtering.
In an alternative embodiment, the target used in the magnetron sputtering process is a composite target or alloy target composed of a pure copper target inlaid with a doped metal.
In an alternative embodiment, the background vacuum level during magnetron sputtering is better than 1×10 -3 Pa。
In alternative embodiments, the process conditions of magnetron sputtering include at least one of the following features:
characteristic one: the power of the magnetron sputtering is 30-500W;
and the second characteristic is: the working air pressure is 0.1-1.0Pa;
and (3) the following characteristics: the bias voltage is-50V to-150V;
and four characteristics: the deposition time is 300-3600s.
In an alternative embodiment, the method further comprises pre-treating the substrate with the dielectric layer prior to the magnetron sputtering.
In an alternative embodiment, the pretreatment includes cleaning and ion etching.
In an alternative embodiment, the ion etching is performed by glow discharge.
In an alternative embodiment, the process conditions of the ion etching include at least one of the following features:
characteristic one: the working air pressure is 0.3-0.5Pa;
and the second characteristic is: the bias voltage is-400V to-800V;
and (3) the following characteristics: the cleaning time is 2-5min.
In an alternative embodiment, the magnetron sputtering is followed by a vacuum annealing process.
In an alternative embodiment, the process conditions of the vacuum anneal include at least one of the following features:
characteristic one: background vacuum degree is better than 2 multiplied by 10 -4 Pa；
And the second characteristic is: the annealing temperature is 400-800 ℃;
and (3) the following characteristics: the temperature rising rate is 5-10 ℃/min;
and four characteristics: the heat preservation time is 30-60min.
In a third aspect, the present application provides an electronic component comprising the copper interconnect architecture of any of the preceding embodiments.
The beneficial effects of this application include:
according to the method, the specific metal is doped in the copper-based alloy film, so that the thermal stability of the copper interconnection structure system can be effectively improved, and the film resistivity of the copper interconnection structure system can be reduced. Specifically, by co-doping a metal element (including at least one of Zr, ti, and V) and a refractory metal element (including at least one of Cr, mo, and W) which are liable to form an oxide passivation layer in the copper-based alloy thin film, zr, ti, or V atoms can generate stable ZrO at interfaces (between the thin film and the dielectric layer), respectively, by interaction between the co-doping elements 2 、TiO 2 Or V 2 O 5 Can be used as a barrier layer and can effectively improve the copper-based alloy film and a dielectric layer (such as SiO) 2 Dielectric layer). Cr, mo or W exists in the form of a refractory metal simple substance layer, so that the high-temperature thermal stability of the diffusion barrier layer can be further improved, and meanwhile, the better conductivity can be maintained. The two are combined, so that the diffusion barrier performance of the copper interconnection structure system is improved, and meanwhile, the influence on the conductivity of the copper interconnection structure system is small, and the reliability of the Cu interconnection line is improved.
That is, the copper interconnection structure system provided by the application has the advantages that the copper interconnection structure system has lower resistivity, higher thermal stability and good diffusion barrier property by arranging the copper base alloy film, so that the problems of performance degradation and failure of electronic components caused by severe copper-silicon interdiffusion at high temperature are avoided, the circuit power consumption is reduced, and the service life of the circuit is prolonged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic structural diagram of a copper interconnect architecture provided herein;
FIG. 2 is a graph showing the change of the film resistivity of the Zr and Cr element doped copper-based alloy film interconnect structure system in comparative example 2 and comparative example 3 and the Zr and Cr element co-doped copper-based alloy film interconnect structure system in example 1 with the annealing temperature;
FIG. 3 is an XRD spectrum of a Zr and Cr element doped copper-based alloy thin film interconnect structure system in comparative example 2 and comparative example 3 and a Zr and Cr element co-doped copper-based alloy thin film interconnect structure system in example 1 after vacuum annealing at 800 ℃.
Icon: 1-a substrate; a 2-dielectric layer; 3-copper base alloy film.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
The copper interconnection structure system, the preparation method thereof and the electronic component provided by the application are specifically described below.
Aiming at the problems that the existing copper interconnection diffusion barrier layer needs to be prepared independently, has poor thermal stability and high resistivity, the diffusion barrier performance needs to be further improved, and the like, the inventor creatively provides a copper interconnection structure system which has high thermal stability and reliability, can keep low film resistivity, is beneficial to reducing circuit power consumption and prolonging the service life of a circuit.
Specifically, referring to fig. 1, the copper interconnect structure system includes a dielectric layer 2 disposed on a surface of a substrate 1, and a copper-based alloy film 3 disposed on a surface of the dielectric layer 2, wherein a diffusion barrier interconnect structure is formed between the copper-based alloy film 3 and the dielectric layer 2.
The substrate 1 described above may illustratively comprise a monocrystalline Si substrate, and furthermore, it is not excluded that other substrates 1 may be employed.
The dielectric layer 2 may illustratively comprise SiO 2 Dielectric layers, in addition, are not excluded as being other inorganic insulating dielectric layers. The thickness of the dielectric layer 2 may be 10 to 200nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 120nm, 150nm, 180nm or 200nm, etc., and may be any other value within the range of 10 to 200nm.
If the thickness of the dielectric layer 2 is less than 10nm, the oxide passivation layer is not easy to form, so that the adhesion capability between the copper interconnection line and the dielectric layer is reduced, or the passivation layer thickness is too thin, and the diffusion barrier capability is reduced; if the thickness of the dielectric layer 2 exceeds 200nm, the reduction of the feature size of the integrated circuit is not favored.
In the application, the copper-based alloy film 3 is doped with doping elements; the doping element includes a metal that is susceptible to forming an oxide self-passivation layer and a refractory metal.
Illustratively, the metal susceptible to forming the oxide self-passivation layer includes at least one of Zr, ti, and V. The refractory metal comprises at least one of Cr, mo, and W.
It should be noted that, as used herein, no intermetallic compound is formed between the doping element and copper.
According to the method, the specific metal is doped in the copper-based alloy film 3, so that the thermal stability of the copper interconnection structure system can be effectively improved, and the film resistivity of the copper interconnection structure system can be reduced. Specifically, by co-doping a metal element (including at least one of Zr, ti and V) and a refractory metal element (including at least one of Cr, mo and W) which are liable to form an oxide passivation layer in the copper-based alloy thin film 3, zr, ti and/or V atoms can form stable ZrO at the interface (between the thin film and the dielectric layer 2) respectively by interaction between the co-doping elements after vacuum annealing treatment 2 、TiO 2 And/or V 2 O 5 Can be used as a barrier layer and can effectively improve the copper-based alloy film 3 and the dielectric layer 2 (such as SiO 2 Dielectric layer). Cr, mo and/or W exist in the form of refractory metal simple substance layer, and can be further improvedThe diffusion barrier layer has high thermal stability and good conductivity. The two are combined, so that the diffusion barrier performance of the copper interconnection structure system is improved, and meanwhile, the influence on the conductivity of the copper interconnection structure system is small, and the reliability of the Cu interconnection line is improved.
For reference, the total doping amount of the above doping elements in the copper-based alloy thin film 3 may be 0.1 to 3at.%, such as 0.1at.%, 0.2at.%, 0.5at.%, 0.8at.%, 1.0at.%, 1.2at.%, 1.5at.%, 1.8at.%, 2.0at.%, 2.2at.%, 2.5at.%, 2.8at.%, or 3.0at.%, etc., and may be any other value in the range of 0.1 to 3at.%.
In some preferred embodiments, the total doping amount of the doping element in the copper-based alloy thin film 3 may be 1 to 2at.%; in some more preferred embodiments, the total doping amount of the doping element in the copper-based alloy thin film 3 may be 1.5at.%. In the above preferred or more preferable range, the copper interconnect structure system has more excellent conductive properties and thermal stability.
If the total doping amount of the doping elements in the copper-based alloy film 3 is lower than 0.1at%, an effective diffusion barrier layer is not formed, and the thermal stability of the copper interconnection structure is reduced; if the total doping amount of the doping elements in the copper-based alloy film 3 is higher than 3at%, the resistivity of the copper interconnection structure is not reduced, and the requirement of low resistivity of the copper interconnection line is not met.
For reference, the atomic ratio between the metal capable of forming the oxide self-passivation layer and the refractory metal may be 1:1-1:2, such as 1:1, 1:1.1, 1:1.2, 1:1.3, 1:1.4, 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9, or 1:2, and may be any other value within the range of 1:1-1:2.
If the doping amount of the refractory metal is less than the doping amount of the metal which is easy to form the oxide self-passivation layer, the film resistivity is not reduced by virtue of the good conductivity of the Cr metal simple substance layer; if the doping amount of the refractory metal is 2 times higher than that of the metal which is easy to form the oxide self-passivation layer, the adhesion capability of the copper interconnection line and the dielectric layer is not enhanced.
For reference, the thickness of the copper-based alloy thin film 3 may be 50 to 500nm, such as 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm, or any other value within the range of 50 to 500nm.
If the thickness of the copper-based alloy film 3 is less than 50nm, the diffusion barrier performance of the copper interconnection structure system is poor; if the thickness of the copper-based alloy film 3 exceeds 500nm, the requirement of the feature size of the copper interconnection line of the integrated circuit which is continuously reduced is not satisfied.
In some embodiments, the copper interconnect structure system can withstand high temperatures of 800 ℃ and can have a resistivity as low as 2.93 μΩ·cm.
On the other hand, the copper interconnection structure system provided by the application has the advantages that the copper interconnection structure system has lower resistivity, higher thermal stability and good diffusion barrier property by depositing the copper base alloy film 3, so that the problems of performance degradation and failure of electronic components caused by severe copper-silicon interdiffusion at high temperature are avoided, the circuit power consumption is reduced, and the service life of the circuit is prolonged.
Correspondingly, the application also provides a preparation method of the copper interconnection structure system, which comprises the following steps: a copper-based alloy film 3 is provided on the surface of the dielectric layer 2.
In some embodiments, prior to preparing the copper-based alloy film 3, further comprising pre-treating the substrate 1 with the dielectric layer 2.
For example, the pretreatment may include cleaning and ion etching.
The cleaning may be sequentially performing acetone cleaning, absolute ethyl alcohol cleaning and deionized water cleaning on the substrate 1 with the dielectric layer 2, and drying after cleaning.
Ion etching can be performed by glow discharge.
The working pressure of the ion etching may be 0.3-0.5Pa, such as 0.3Pa, 0.35Pa, 0.4Pa, 0.45Pa, or 0.5Pa, or any other value within the range of 0.3-0.5 Pa.
The bias voltage for ion etching may be-400V to-800V, such as-400V, -450V, -500V, -550V, -600V, -650V, -700V, -750V or-800V, etc., or may be any other value in the range of-400V to-800V.
The ion etching cleaning time can be 2-5min, such as 2min, 2.5min, 3min, 3.5min, 4min, 4.5min or 5min, or any other value within 2-5min.
In some embodiments, the copper-based alloy film 3 may be prepared by magnetron sputtering. In other embodiments, it is not excluded that the copper-based alloy film 3 may be produced in other ways.
The copper-based alloy film 3 prepared by the magnetron sputtering process has at least the following advantages: the deposition efficiency is high, the film base binding force is good, and the obtained film has high purity, good compactness and good film forming uniformity.
Taking the preparation method as an example of magnetron sputtering, the target material used in the magnetron sputtering process can be a composite target or an alloy target formed by embedding doped metal into a pure copper target.
Background vacuum degree in the magnetron sputtering process is better than 1 multiplied by 10 -3 Pa, e.g. 0.9X10 -3 Pa、0.8×10 -3 Pa or 0.7X10 -3 Pa, and the like.
If the background vacuum degree in the magnetron sputtering process is insufficient, the residual elements (such as O and/or N) in the furnace chamber easily pollute the interface due to the slow magnetron sputtering deposition rate, and the film performance is affected.
For reference, the power of the magnetron sputtering may be 30 to 500W, such as 30W, 50W, 100W, 120W, 150W, 200W, 250W, 300W, 350W, 400W, 450W, or 500W, or any other value in the range of 30 to 500W.
If the power in the magnetron sputtering process is lower than 30W, the deposition rate is easy to be too slow and the glow is not easy to start; above 500W, the structure of the film is easily damaged, the secondary sputtering of high-energy particles is easy, the prepared film is rough, and the defects of the film are increased.
The working pressure of the magnetron sputtering may be 0.1 to 1.0Pa, such as 0.1Pa, 0.2Pa, 0.3Pa, 0.4Pa, 0.5Pa, 0.6Pa, 0.7Pa, 0.8Pa, 0.9Pa, or 1.0Pa, or any other value within the range of 0.1 to 1.0 Pa.
If the working air pressure in the magnetron sputtering process is lower than 0.1Pa, the deposition rate is easy to be low, the film is very thin, and high-energy particles reach the surface of the substrate to cause secondary sputtering, so that the surface of the film is rough; above 1.0Pa, holes are formed on the surface of the film, and the continuity is poor.
The bias voltage of the magnetron sputtering can be-50V to-150V, such as-50V, -60V, -70V, -80V, -90V, -100V, -110V, -120V, -130V, -140V or-150V, and the like, and can be any other value in the range of-50V to-150V.
If the bias voltage in the magnetron sputtering process is lower than-50V (such as-40V, etc.), the compactness of the film is easy to be reduced, and the resistivity is increased; above-150V (such as-160V, etc.), the phenomenon of self-sputtering is serious and the residual stress is too high, so that the binding force of the film is reduced.
The deposition time of the magnetron sputtering may be 300-3600s, such as 300s, 500s, 800s, 1000s, 1500s, 2000s, 2500s, 3000s, 3200s or 3600s, and may be any other value within the range of 300-3600s.
If the deposition time in the magnetron sputtering process is shorter than 300s, the prepared film is thinner, so that the thickness of the annealed self-formed diffusion barrier layer is thinner, and the requirement of diffusion barrier cannot be met; longer than 3600s, the ever-decreasing copper interconnect feature size requirements of integrated circuits are not met.
Further, after magnetron sputtering, a vacuum annealing treatment process is also provided.
As reference ground, the background vacuum degree of vacuum annealing is better than 2×10 -4 Pa, e.g. 1.8X10 -4 Pa、1.5×10 - 4 Pa、1×10 -4 Pa or 0.8X10 -4 Pa, and the like.
If the background vacuum degree in the vacuum annealing process is not proper, copper atoms in the film are easily oxidized in the annealing process, so that the film resistivity is increased.
The annealing temperature may be 400-800 ℃, such as 400 ℃, 450 ℃, 500 ℃, 550 ℃, 600 ℃, 650 ℃,700 ℃, 750 ℃, 800 ℃, etc., or any other value in the range of 400-800 ℃.
If the annealing temperature is lower than 400 ℃, the annealing driving force for providing enough doping elements is not favorable, and the film resistivity is reduced; above 800 ℃, the high temperature thermal stability of the copper interconnect structure cannot be verified.
The heating rate in the vacuum annealing treatment process can be 5-10 ℃ per minute, such as 5 ℃ per minute, 5.5 ℃ per minute, 6 ℃ per minute, 6.5 ℃ per minute, 7 ℃ per minute, 7.5 ℃ per minute, 8 ℃ per minute, 8.5 ℃ per minute, 9 ℃ per minute, 9.5 ℃ per minute or 10 ℃ per minute, and the like, and can also be any other value within the range of 5-10 ℃ per minute.
If the heating rate is less than 5 ℃/min, the precipitation of doping elements is not facilitated, and an effective diffusion barrier layer is formed; is more than 10 ℃/min, is unfavorable for the growth of crystal grains and has poorer film compactness.
The vacuum annealing process can be performed for 30-60min, such as 30min, 35min, 40min, 45min, 50min, 55min or 60min, or any other value within 30-60min.
If the heat preservation time is shorter than 30min, the annealing driving force which is not enough for the doping element is not favorable, the film resistivity is reduced, and an effective diffusion barrier layer is formed; after the time of longer than 60 minutes, crystal grains are easily grown, aggregated and pilled due to annealing of the film, and the surface quality of the film is reduced.
It is emphasized that the doping elements are doped in copper before vacuum annealing treatment, and the conductivity of the doping elements is inferior to that of pure copper, so that the corresponding film can not meet the requirements of industry on resistivity; after the vacuum annealing treatment, the doping element can spontaneously diffuse, so that the doping element is concentrated at the interface, and the resistivity of the film is reduced.
On the contrary, the conventional copper interconnection diffusion barrier layer in the prior art is prepared by a two-step method, namely, a copper film, namely, a copper seed layer is deposited on the surface of the substrate 1 with the dielectric layer 2 after the diffusion barrier layer is deposited. However, the method has the problems of complex preparation process, larger overall size of the device, higher overall resistance of an interconnection system and the like. The method provided by the application is simple in process, does not need to prepare the diffusion barrier layer independently, and only needs to prepare the diffusion barrier layer by a one-step method, so that the process flow is simplified, and the process efficiency is improved. Compared with the prior art, the method not only reduces the overall size of the device and the overall resistance of an interconnection system, but also effectively solves the problem of insufficient thermal stability of the conventional single element doped copper alloy film.
In addition, the application also provides an electronic component, which comprises the copper interconnection structure system, is not easy to cause short circuit and degradation of the device, and has long service life.
The features and capabilities of the present invention are described in further detail below in connection with the examples.
Example 1
The embodiment provides a copper interconnection structure system, which is prepared by the following steps:
(1) Will have a dielectric layer 2 (SiO) of 10nm 2 Placing substrate 1 (Si substrate) of dielectric layer) into acetone, absolute ethanol, deionized water, cleaning for 15min, oven drying, placing on rotary sample stage at the center of chamber, closing vacuum chamber door, and sequentially vacuumizing to 0.8X10 by using mechanical pump and molecular pump -3 Pa；
(2) Performing ion etching treatment on the substrate 1 by glow discharge, and introducing argon to a working pressure of 0.3Pa, a bias voltage of-400V and a cleaning time of 5min in the ion etching process;
(3) After ion etching is finished, starting a Cu-Zr-Cr embedded composite target, and preparing a ZrCr multi-doped copper alloy film by magnetron sputtering, wherein the technological parameters are as follows: target power 30W, bias voltage-50V, working air pressure 0.1Pa, deposition time 300s;
(4) After coating, the furnace is opened to take out the sample, and the sample is divided into a deposition state (not annealed) and an annealing state. The annealed sample is prepared by putting the obtained ZrCr multi-doped copper alloy film into a vacuum annealing furnace, wherein the background vacuum degree of the annealing furnace is 1 multiplied by 10 -4 Pa, performing high vacuum annealing at different temperatures, wherein the annealing temperature is 400 ℃, 500 ℃, 600 ℃,700 ℃, 800 ℃, and the heat preservation time is 30min, and the heating rate is 5 ℃/min;
in the prepared Zr and Cr multi-doped copper alloy film, the thickness of the film layer is 50nm, the co-doping amount of Zr and Cr metals is 0.1at%, and the atomic ratio of Zr to Cr is 1:1.
Cu (ZrCr) 1 /SiO 2 Si co-doped alloy thin film interconnection structure systemThe change in film resistivity with annealing temperature is shown in fig. 2. As can be seen from fig. 2: the resistivity of the ZrCr multi-doped copper alloy film after 800 ℃ annealing is about 3.23 mu omega cm, meets the requirement of the copper interconnection line on the resistivity, and has practical significance.
Example 2
The embodiment provides a copper interconnection structure system, which is prepared by the following steps:
(1) Will have a dielectric layer 2 (SiO) of 100nm 2 Placing substrate 1 (Si substrate) of dielectric layer) into acetone, absolute ethanol, deionized water, cleaning for 20min, oven drying, placing on rotary sample stage at the center of chamber, closing vacuum chamber door, and sequentially vacuumizing to 1.0X10 by using mechanical pump and molecular pump -3 Pa；
(2) Performing ion etching treatment on the substrate 1 by glow discharge, and introducing argon to a working pressure of 0.4Pa, a bias voltage of-600V and a cleaning time of 3min in the ion etching process;
(3) After ion etching is finished, starting a Cu-Ti-Mo embedded composite target, and preparing the TiMo multi-doped copper alloy film by magnetron sputtering, wherein the technological parameters are as follows: target power 300W, bias voltage-110V, working air pressure 0.5Pa, deposition time 1800s;
(4) After coating, the furnace is opened to take out the sample, and the sample is divided into two main types of a deposition state (not annealed) and an annealing state. The annealed sample is prepared by putting the obtained TiMo multi-doped copper alloy film into a vacuum annealing furnace, wherein the background vacuum degree of the annealing furnace is better than 1.8X10 -4 Pa, performing high vacuum annealing at different temperatures, wherein the annealing temperature is 400 ℃, 500 ℃, 600 ℃,700 ℃, 800 ℃, the heat preservation time is 45min, and the heating rate is 7 ℃/min;
in the TiMo multi-doped copper alloy film prepared by the method, the thickness of a film layer is 300nm, the co-doping amount of Ti and Mo metals is 1.5at%, and the atomic ratio of Ti to Mo is 1:1.5.
The Cu (TiMo)/SiO 2 The resistivity of the Si co-doped alloy film interconnection structure system after being annealed at 800 ℃ is about 3.05 mu omega cm, meets the requirement of copper interconnection wires on the resistivity, and has practical significance.
Example 3
The embodiment provides a copper interconnection structure system, which is prepared by the following steps:
(1) Will have a dielectric layer 2 (SiO) of 200nm 2 Placing substrate 1 (Si substrate) of dielectric layer) into acetone, absolute ethanol, and deionized water, cleaning for 30min, oven drying, placing on a rotary sample stage at the center of the chamber, closing vacuum chamber door, and sequentially vacuumizing to 0.9X10 with mechanical pump and molecular pump -3 Pa；
(2) Performing ion etching treatment on the substrate 1 by glow discharge, and introducing argon to a working pressure of 0.5Pa, a bias voltage of-800V and a cleaning time of 2min in the ion etching process;
(3) After ion etching is finished, starting a Cu-V-W embedded composite target, and preparing the VW multi-element doped copper alloy film by magnetron sputtering, wherein the technological parameters are as follows: target power 500W, bias-150V, working air pressure 1.0Pa, deposition time 3600s;
(4) After coating, the furnace is opened to take out the sample, and the sample is divided into two main types of a deposition state (not annealed) and an annealing state. The annealed sample is prepared by placing the obtained VW multi-doped copper alloy film into a vacuum annealing furnace, wherein the background vacuum degree of the annealing furnace is better than 1.5 multiplied by 10 -4 Pa, performing high vacuum annealing at different temperatures, wherein the annealing temperature is 400 ℃, 500 ℃, 600 ℃,700 ℃, 800 ℃, the heat preservation time is 60min, and the heating rate is 10 ℃/min;
in the V and W multi-element doped copper alloy film prepared by the method, the thickness of a film layer is 500nm, the co-doping amount of V and W metals is 3at%, and the atomic ratio of V to W is 1:2.
Cu (VW)/SiO 2 The resistivity of the Si co-doped alloy film interconnection structure system after being annealed at 800 ℃ is about 2.93 mu omega cm, meets the requirement of copper interconnection wires on the resistivity, and has practical significance.
Example 4
This embodiment differs from embodiment 1 in that: the atomic ratio of Zr to Cr is 1:1.5.
Cu (ZrCr) 2 /SiO 2 The film resistivity of the Si co-doped alloy film interconnection structure system after being annealed at 800 ℃ is about 3.16 mu omega cm, and the Si co-doped alloy film interconnection structure system has a certain practical significance of copper interconnection lines.
Example 5
This embodiment differs from embodiment 1 in that: the atomic ratio of Zr to Cr is 1:2.
Cu (ZrCr) 3 /SiO 2 The film resistivity of the Si co-doped alloy film interconnection structure system after 800 ℃ annealing is about 3.47 mu omega cm, and the Si co-doped alloy film interconnection structure system has a certain practical significance of copper interconnection lines.
Comparative example 1
This comparative example is similar to example 1, except that: the copper-based alloy film 3 is not doped with metal elements (neither doped with Zr nor doped with Cr), and the prepared pure Cu film in a deposition state and the annealed pure Cu film have almost no diffusion barrier property, and the resistivity is increased to 74.7 mu omega cm after high-temperature annealing at 700 ℃ to indicate that the phenomenon of severe copper-silicon interdiffusion occurs at the moment.
Comparative example 2
This comparative example is similar to example 1, except that: the Zr metal element doping (undoped Cr) is only carried out in the copper-based alloy film 3, and the deposited Zr-doped copper alloy film and the annealed Zr-doped copper alloy film are prepared. After high-temperature annealing at 700 ℃, the resistivity of the film slightly increases to 3.61 mu omega cm compared with annealing at 600 ℃, which shows the trend of copper-silicon interdiffusion at the moment; after annealing at 800 ℃, the resistivity rises to 7.72 mu. Omega. Cm, indicating that the thermal stability of the Zr-doped copper alloy film is still insufficient.
Comparative example 3
This comparative example is similar to example 1, except that: the copper-based alloy film 3 is only doped with Cr metal element (undoped Zr), and the deposited Cr-doped copper alloy film and the annealed Cr-doped copper alloy film are prepared. After high temperature annealing at 700 ℃, the resistivity of the film is still further reduced to 3.05 mu omega cm, but when the annealing temperature is increased to 800 ℃, the resistivity is increased to 6.79 mu omega cm, which indicates that the high-temperature thermal stability of the Cr-doped copper alloy film is still insufficient, but the resistivity of the film is improved.
Comparative example 4
The difference between this comparative example and example 1 is that: the doping amount of the doping element in the copper-based alloy thin film 3 was 0.05at.%.
Comparative example 5
The difference between this comparative example and example 1 is that: the doping amount of the doping element in the copper-based alloy thin film 3 was 5 at%.
Comparative example 6
The difference between this comparative example and example 1 is that: the atomic ratio of Zr to Cr is 1:0.5.
Comparative example 7
The difference between this comparative example and example 1 is that: the atomic ratio of Zr to Cr is 1:3.
Comparative example 8
The difference between this comparative example and example 1 is that: the thickness of the copper-based alloy film 3 was 20nm.
Comparative example 9
The difference between this comparative example and example 1 is that: the thickness of the dielectric layer 2 is 5nm.
Comparative example 10
The difference between this comparative example and example 1 is that: the thickness of the dielectric layer 2 was 220nm.
Comparative example 11
The difference between this comparative example and example 1 is that: background vacuum degree in the magnetron sputtering process is 1.5X10 -3 Pa。
Comparative example 12
The difference between this comparative example and example 1 is that: the power in the magnetron sputtering process is 20W.
Comparative example 13
The difference between this comparative example and example 1 is that: the power in the magnetron sputtering process is 600W.
Comparative example 14
The difference between this comparative example and example 1 is that: the working air pressure in the magnetron sputtering process is 0.05Pa.
Comparative example 15
The difference between this comparative example and example 1 is that: the working air pressure in the magnetron sputtering process is 1.2Pa.
Comparative example 16
The difference between this comparative example and example 1 is that: the bias voltage during magnetron sputtering was-30V.
Comparative example 17
The difference between this comparative example and example 1 is that: the bias voltage during magnetron sputtering was-200V.
Comparative example 18
The difference between this comparative example and example 1 is that: the deposition time in the magnetron sputtering process is 200s.
Comparative example 19
The difference between this comparative example and example 1 is that: the deposition time in the magnetron sputtering process is 4000s.
Comparative example 20
The difference between this comparative example and example 1 is that: background vacuum degree of vacuum annealing is 2.5X10 -4 Pa。
Comparative example 21
The difference between this comparative example and example 1 is that: the temperature of the vacuum annealing was 300 ℃.
Comparative example 22
The difference between this comparative example and example 1 is that: the temperature of the vacuum annealing was 900 ℃.
Comparative example 23
The difference between this comparative example and example 1 is that: the heating rate in the vacuum annealing process is 2 ℃/min.
Comparative example 24
The difference between this comparative example and example 1 is that: the heating rate in the vacuum annealing process is 12 ℃/min.
Comparative example 25
The difference between this comparative example and example 1 is that: the holding time in the vacuum annealing process was 20min.
Comparative example 26
The difference between this comparative example and example 1 is that: the holding time in the vacuum annealing process was 80min.
Test examples
Performance tests were performed using examples 1 to 5 and comparative examples 1 to 26, and the results are shown in fig. 2, 3 and table 1.
FIG. 2 is a graph showing the change of film resistivity of a Zr or Cr single doped copper alloy film interconnect structure system and a ZrCr co-doped copper alloy film interconnect structure system with the annealing temperature. From this figure it can be seen that: the resistivity of the alloy film is slightly increased after high vacuum annealing at 800 ℃ when Zr or Cr is singly doped, and the resistivity of the alloy film is further reduced to the lowest value of 3.23 mu omega cm after high vacuum annealing at 800 ℃ when ZrCr is co-doped.
FIG. 3 is an XRD spectrum of a Zr or Cr singly doped copper alloy film interconnect structure system annealed at 800 ℃ with a ZrCr co-doped copper alloy film interconnect structure system. From this figure it can be seen that: the alloy film of Zr or Cr single doping detects weak Cu 3 Si diffraction peaks, while the alloy film when ZrCr was co-doped did not detect any diffraction peaks of the Cu-Si compound.
TABLE 1
Figure BDA0004164135500000161
Figure BDA0004164135500000171
Figure BDA0004164135500000181
As can be seen from Table 1, the alloy film in the embodiment of the application has lower resistivity after high vacuum annealing at 800 ℃ than the comparative example, which is beneficial to reducing circuit power consumption and prolonging the service life of the circuit.
In summary, the copper interconnection structure system provided by the application adopts the embedded target or the alloy metal target, the multielement doped copper base alloy film 3 is prepared and obtained through a magnetron sputtering one-step method, the preparation process is simple, the process controllability and the repeatability are high, and the metal particles exist in the copper base alloy film 3 in a doped form, so that the thermal stability and the reliability of the copper interconnection structure system are further improved, meanwhile, the lower film resistivity is maintained, the circuit power consumption is reduced, and the copper interconnection structure system has important significance for improving the performance of an integrated circuit.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The copper interconnection structure system is characterized by comprising a dielectric layer arranged on the surface of a substrate and a copper-based alloy film arranged on the surface of the dielectric layer, wherein a diffusion barrier interconnection structure is formed between the copper-based alloy film and the dielectric layer;
doping elements are doped in the copper-based alloy film; the doping element comprises metal and refractory metal which are easy to form an oxide self-passivation layer, and an intermetallic compound is not formed between the doping element and copper; the doping amount of the doping element in the copper-based alloy film is 0.1-3 at%.
2. The copper interconnect structure of claim 1 wherein an atomic ratio between the metal of the self-passivating layer of readily formable oxide and the refractory metal is 1:1-1:2.
3. The copper interconnect structure system of claim 1 or 2, wherein the metal susceptible to forming an oxide self-passivation layer comprises at least one of Zr, ti and V; and/or the refractory metal comprises at least one of Cr, mo, and W.
4. The copper interconnect structure system of claim 1, wherein the copper-based alloy thin film has a thickness of 50-500nm.
5. The copper interconnect architecture of claim 1, wherein the substrate comprises a single crystal Si substrate;
and/or the dielectric layer comprises SiO 2 A dielectric layer;
and/or the thickness of the dielectric layer is 10-200nm.
6. The method of manufacturing a copper interconnect structure according to any of claims 1-5, comprising the steps of: and arranging the copper-based alloy film on the surface of the dielectric layer.
7. The preparation method according to claim 6, wherein the copper-based alloy film is prepared by a magnetron sputtering method;
preferably, the target material used in the magnetron sputtering process is a composite target or alloy target formed by embedding doped metal into a pure copper target;
preferably, the background vacuum degree in the magnetron sputtering process is better than 1×10 -3 Pa；
Preferably, the process conditions of magnetron sputtering include at least one of the following features:
characteristic one: the power of the magnetron sputtering is 30-500W;
and the second characteristic is: the working air pressure is 0.1-1.0Pa;
and (3) the following characteristics: the bias voltage is-50V to-150V;
and four characteristics: the deposition time is 300-3600s.
8. The method of claim 7, further comprising pre-treating the substrate with the dielectric layer prior to the magnetron sputtering;
preferably, the pretreatment includes cleaning and ion etching;
preferably, ion etching is performed by glow discharge;
preferably, the process conditions of the ion etching include at least one of the following features:
characteristic one: the working air pressure is 0.3-0.5Pa;
and the second characteristic is: the bias voltage is-400V to-800V;
and (3) the following characteristics: the cleaning time is 2-5min.
9. The method according to claim 7, wherein the magnetron sputtering is followed by vacuum annealing;
preferably, the process conditions of the vacuum annealing include at least one of the following features:
characteristic one: background vacuum degree is better than 2 multiplied by 10 -4 Pa；
And the second characteristic is: the annealing temperature is 400-800 ℃;
and (3) the following characteristics: the temperature rising rate is 5-10 ℃/min;
and four characteristics: the heat preservation time is 30-60min.
10. An electronic component comprising the copper interconnect architecture of any one of claims 1-5.
CN202310358315.2A 2023-04-04 2023-04-04 Copper interconnection structure system, preparation method thereof and electronic component Pending CN116247034A (en)

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